DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) submitted on December 7, 2023 and February 8, 2025 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Objections
Claim 13 is objected to because of the following informalities: “insulted” should read “insulated” (line 1). Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2020/0365525 A1 (hereinafter “Wu”).
Regarding claim 10, Wu discloses in Figs. 6C (top view), 13 (cross-sectional view after singulation, viewed upside down) and related text a structure, comprising:
a first semiconductor die (32; [0021]);
second semiconductor dies (28, 44; [0019] and [0027]) stacked over the first semiconductor die;
dummy dies (54’; [0040] and [0051]) stacked over the first semiconductor die; and
a gap filling layer (58, 58A; [0043]-[0044]) disposed on the first semiconductor die to laterally encapsulate the dummy dies and the second semiconductor dies, wherein each of the dummy dies comprises an outer sidewall, and the outer sidewall of each of the dummy dies is substantially aligned with a sidewall of the gap filling layer (an outer sidewall of portion 58A of encapsulant 58 after singulation; [0051]).
Regarding claim 11, Wu shows the dummy dies are electrically floated (they are positioned over dielectric material of the redistribution structure 40 and do not contact any of the conductive features of the redistribution structure 40; Fig. 7; [0023]).
Regarding claim 12, Wu shows the dummy dies are electrically insulated (by underfill material 52 and encapsulant 58) from the first semiconductor die and the second semiconductor dies (Fig. 13; [0034] and [0043]).
Regarding claim 13, Wu shows the dummy dies are electrically insulated (by underfill material 52 and encapsulant 58) from each other (Fig. 13).
Regarding claim 14, Wu discloses a first coefficient of thermal expansion (CTE) mismatch between the gap filling layer and the first semiconductor die is greater than a second CTE mismatch between the dummy dies and the first semiconductor die ([0039]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2 and 4-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0138101 A1 (hereinafter “Yu”) in view of US 2022/0102242 A1 (hereinafter “Modi”).
Regarding claim 1, Yu discloses in Figs. 13 (top view), 14 (cross-sectional view after singulation, viewed upside down) and related text a structure, comprising:
a first semiconductor die (96; [0019]);
second semiconductor dies (68, 88; [0025] and [0033]) disposed over and electrically connected to the first semiconductor die;
dummy dies (106’; [0037], [0051], [0053] and [0055]) disposed over the first semiconductor die to laterally surround the second semiconductor dies; and
a gap filling layer (112; [0043]) disposed on the first semiconductor die to laterally encapsulate the dummy dies and the second semiconductor dies.
Yu does not explicitly disclose a roughness of a bottom surface of each of the dummy dies is smaller than a roughness of a top surface of each of the dummy dies.
Modi teaches in Fig. 10B and related text a roughness of a bottom surface of each of the dummy dies (940; [0107]) is smaller than a roughness of a top surface (942; [0107]) of each of the dummy dies.
Yu and Modi are analogous art because they both are directed to semiconductor package structures including dummy dies and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yu with the specified features of Modi because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form a roughness of a bottom surface of each of the dummy dies to be smaller than a roughness of a top surface of each of the dummy dies, as taught by Modi, in order to enable the dummy dies to be formed by a high throughput additive manufacturing process such as cold spray deposition instead of by a pick-and-place process (as in Yu), thereby enabling an efficient formation of a material, the physical properties of which (in combination with physical properties of a mold compound) are to mitigate heat-induced stresses of a packaged device (Modi: [0041] and [0071]).
Regarding claim 2, Yu in view of Modi disclose the first semiconductor die comprises a first bonding structure (Yu: 77, 78; Fig. 3; [0023]), each of the second semiconductor dies comprises a second bonding structure (Yu: 79; Fig. 4; [0025]), and the second bonding structure of each of the second semiconductor dies is in contact with and electrically connected to the first bonding structure (Yu: [0033]).
Regarding claim 4, Yu in view of Modi disclose the dummy dies are spaced apart from the second bonding structure of each of the second semiconductor dies by the gap filling layer (Yu: Fig. 14).
Regarding claim 5, Yu in view of Modi disclose each of the dummy dies is laterally spaced apart from one of the second semiconductor dies by the gap filling layer (Yu: Fig. 14).
Regarding claim 6, Yu in view of Modi disclose each of the dummy dies comprises an outer sidewall, and the outer sidewall is substantially aligned with a sidewall of the first semiconductor die (Yu: Fig. 14; [0056]).
Regarding claim 7, Yu in view of Modi disclose two neighboring second semiconductor dies among the second semiconductor dies are laterally spaced apart from each other by the gap filling layer (Yu: Fig. 14).
Regarding claim 8, Yu in view of Modi disclose two neighboring dummy dies among the dummy dies are laterally spaced apart from each other by the gap filling layer (Yu: Fig. 14).
Regarding claim 9, Yu in view of Modi disclose die attachment films (Yu: 104; Fig. 6B; [0040]), wherein each of the dummy dies is attached onto the first semiconductor die through one of the die attachment films respectively.
Claim(s) 15-18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of US 2015/0093858 A1 (hereinafter “Hwang”).
Regarding claim 15, Wu discloses the structure of claim 10.
Wu does not explicitly disclose a first coefficient of thermal expansion (CTE) of the gap filling layer is greater than a second CTE of the dummy dies or the second semiconductor dies.
Hwang teaches in Figs. 1A-1B and related text a first coefficient of thermal expansion (CTE) of the gap filling layer (36; [0015] and [0017]) is greater than a second CTE of the dummy dies (30; [0015] and [0017]) or the second semiconductor dies.
Wu and Hwang are analogous art because they both are directed to semiconductor package structures including dummy dies and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wu with the specified features of Hwang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form a first coefficient of thermal expansion (CTE) of the gap filling layer to be greater than a second CTE of the dummy dies or the second semiconductor dies, as taught by Hwang, in order to reduce warpage in the manufacturing of the semiconductor package structure (Hwang: [0032]).
Regarding claim 16, Wu discloses in Figs. 6C (top view), 13 (cross-sectional view after singulation, viewed upside down) and related text a structure, comprising:
a bottom tier semiconductor die (32; [0021]);
top tier semiconductor dies (28, 44; [0019] and [0027]) disposed over the bottom tier semiconductor die;
a group of warpage control components (54’; [0040] and [0051]) disposed over the bottom tier semiconductor die; and
a gap filling layer (58, 58A; [0043]-[0044]) disposed on the bottom tier semiconductor die and laterally encapsulating the group of warpage control components and the top tier semiconductor dies.
Wu does not explicitly disclose a first coefficient of thermal expansion (CTE) of the gap filling layer is greater than a second CTE of the group of warpage control components and/or the top tier semiconductor dies.
Hwang teaches in Figs. 1A-1B and related text a first coefficient of thermal expansion (CTE) of the gap filling layer (36; [0015] and [0017]) is greater than a second CTE of the group of warpage control components (30; [0015] and [0017]) and/or the top tier semiconductor dies.
Wu and Hwang are analogous art because they both are directed to semiconductor package structures including dummy dies and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wu with the specified features of Hwang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form a first coefficient of thermal expansion (CTE) of the gap filling layer to be greater than a second CTE of the group of warpage control components and/or the top tier semiconductor dies, as taught by Hwang, in order to reduce warpage in the manufacturing of the semiconductor package structure (Hwang: [0032]).
Regarding claim 17, Wu in view of Hwang disclose each one warpage control component among the group of warpage control components comprises an outer sidewall, and the outer sidewall of each one warpage control component among the group of warpage control components is substantially aligned with a sidewall of the gap filling layer (an outer sidewall of portion 58A of encapsulant 58 after singulation, as shown in Fig. 13 of Wu; see also Wu [0051]).
Regarding claim 18, Wu in view of Hwang disclose each one warpage control component among the group of warpage control components comprises an outer sidewall, and the outer sidewall of each one warpage control component among the group of warpage control components is substantially aligned with a sidewall of the bottom tier semiconductor die (Wu: Fig. 13; [0052]).
Regarding claim 20, Wu in view of Hwang disclose the group of warpage control components are electrically floated (they are positioned over dielectric material of the redistribution structure 40 and do not contact any of the conductive features of the redistribution structure 40, as shown in Fig. 7 of Wu; see also Wu [0023]).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Hwang as applied to claim 16 above, and further in view of US 2018/0082987 A1 (hereinafter “Chen”).
Regarding claim 19, Wu in view of Hwang disclose the structure of claim 16.
Wu in view of Hwang do not explicitly disclose each one warpage control component among the group of warpage control components is laterally spaced apart from one of the top tier semiconductor dies by a lateral distance ranging from about 30 micrometers to about 50 micrometers.
Chen teaches in Fig. 1A and related text each one warpage control component (160; [0017] and [0022]) among the group of warpage control components is laterally spaced apart from one of the top tier semiconductor dies (140; [0017]) by a lateral distance ranging from about 30 micrometers to about 50 micrometers ([0036]).
Wu, Hwang and Chen are analogous art because they each are directed to semiconductor package structures including dummy dies and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wu in view of Hwang with the specified features of Chen because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to arrange each one warpage control component among the group of warpage control components to be laterally spaced apart from one of the top tier semiconductor dies by a lateral distance ranging from about 30 micrometers to about 50 micrometers, as taught by Chen, in order to ensure a margin adequate for a pick-and-place process that may be used to provide the warpage control components and the top tier semiconductor dies on the bottom tier semiconductor die.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Furthermore, it has been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1980). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Yu in view of Modi do not teach or suggest “a roughness of the outer sidewall is greater than the roughness of the top surface of each of the dummy dies,” as recited in claim 3, together with “a roughness of a bottom surface of each of the dummy dies is smaller than a roughness of a top surface of each of the dummy dies,” as recited in independent claim 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M ALBRECHT whose telephone number is (571)272-7813. The examiner can normally be reached M-F 9:30 AM - 6:30 PM (CT).
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/PETER M ALBRECHT/Primary Examiner, Art Unit 2811