Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
1. Applicant's election, without traverse, of claims 1-15 in the “Response to Restriction Requirement” filed on 03/25/2026 is acknowledged and entered by the Examiner.
This office action consider claims 1-20 pending for prosecution, wherein claims 16-20 are withdrawn from further consideration, and claims 1-15 are presented for examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
2. Claims 1-15 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to
particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding Claim 1, the instant claim recites limitations, wherein the metes and bounds of the claimed method are vague and ill-defined as a result of uncertainty in the different boundaries and new limitations “a conductive layer, including a first portion extending into the semiconductor substrate from the first surface of the semiconductor substrate and a second portion disposed over the doped member and coupled to the first portion” and “a first contact disposed over the conductive layer and surrounded by a first dielectric layer” (Claim 1; emphasis added). The claim is indefinite because of the following:
i) The claim is indefinite because “a conductive layer, including a first portion extending into the semiconductor substrate from the first surface of the semiconductor substrate and a second portion disposed over the doped member and coupled to the first portion” and “a first contact disposed over the conductive layer and surrounded by a first dielectric layer” (Claim 1) is ambiguous and lacks clarity. Claim 1 recites that the conductive layer comprises of a first potion and a second portion, where the second portion is disposed over the doped member. Claim 1 also recites that a first contact disposed over the conductive layer. It is not clear if it is meant that a first contact is disposed over a portion of the conductive layer, or a first contact is disposed over the first portion and the second portion of the conductive layer. Therefore, the limitation of “a conductive layer, including a first portion extending into the semiconductor substrate from the first surface of the semiconductor substrate and a second portion disposed over the doped member and coupled to the first portion” and “a first contact disposed over the conductive layer and surrounded by a first dielectric layer” (Claim 1) is indefinite and unclear.
The specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention, whereby the claims are rendered indefinite. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate clarification and/or correction are/is required within metes and bounds of the claimed invention.
As there is a great deal of confusion and uncertainty as to the proper interpretation of the limitations of the claim, it would not be proper for the examiner to reject such a claim on the basis of prior art. See MPEP § 706 and MPEP § 2173.II (second) wherein In re Steele, 305 F.2d 859, 134 USPQ 292 (CCPA 1962), a rejection under 35 U.S.C. 103 should not be based on considerable speculation about the meaning of terms employed in a claim or assumptions that must be made as to the scope of the claims.
Regarding Claims 2-15, those are rejected under 112(b) because of their dependency status from claim 1.
Double Patenting
3. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer
4. Claims 1, 6-7, and 9-15 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims of copending Application No. 18/398,239 (reference application).
Although the claims at issue are not identical, they are not patentably distinct from each other because: Regarding claims 1, 6-7, and 9-15, application 18/398,239 recites all the limitations of these claims (see table 1 below for claim-to-claim matching) See Table 1 below showing what claims of the current application are taught by claims of co-pending application 18/398,239.
Table 1
Current Application
Co-pending Application 18/398,239
1. A memory device, comprising:
a semiconductor substrate having a first surface (first surface is mentioned in highlighted in italics in the co-pending application to the right) and defined with an active area (construed as a first active area) under the first surface; a gate structure adjacent to the active area (construed as a first active area) and indented into the semiconductor substrate from the first surface;
a doped member extending into the semiconductor substrate and surrounded by the active area (construed as a first active area);
a conductive layer including a first portion extending into the semiconductor substrate from the first surface and a second portion disposed over the doped member and coupled to the first portion;
a first insulating layer disposed adjacent to the first portion of the conductive layer and between the doped member and the active area (construed as a first active area) of the semiconductor substrate;
a first contact (construed as a first contact) disposed over the conductive layer and surrounded by a first dielectric layer; and
a first conductive pillar (construed as a first conductive pillar) disposed over the first contact and disposed between the first contact and a capacitor,
wherein the first portion of the conductive layer is disposed between the gate structure and the doped member
1. A memory device, comprising:
a semiconductor substrate defined with a first active area and a second active area; a gate structure adjacent to the first and second active areas and indented into the semiconductor substrate from a first surface of the semiconductor substrate;
a doped member extending into the semiconductor substrate and surrounded by the first active area;
a conductive layer, including a first portion extending into the semiconductor substrate from the first surface of the semiconductor substrate and a second portion disposed over the doped member and coupled to the first portion;
a first insulating layer disposed adjacent to the first portion of the conductive layer and between the doped member and the first active area of the semiconductor substrate, and a second insulating layer disposed over the gate structure, wherein the first insulating layer and the second insulating layer are separated from each other;
a first contact and a second contact disposed over the conductive layer and surrounded by a first dielectric layer; and
a first conductive pillar and a second conductive pillar disposed over the first dielectric layer,
10. The memory device according to claim 9, wherein the capacitor is electrically connected to the first active area through the third contact, the landing pad, the first conductive pillar, the first contact and the conductive layer.
wherein the first portion of the conductive layer is disposed between the gate structure and the doped member
6. The memory device according to claim 1, wherein the conductive layer is disposed over the active area (construed as a first active area).
1. wherein the conductive layer is disposed over the first active area and the second active area
7. The memory device according to claim 1, wherein the first portion of the conductive layer is coupled to the first insulating layer.
2. The memory device according to claim 1, wherein the first portion of the conductive layer is coupled to the first insulating layer.
9. The memory device according to claim 1, wherein the first contact is disposed between the first conductive pillar and the conductive layer.
3. The memory device according to claim 1, wherein the first contact is disposed between the first conductive pillar and the conductive layer, and the second contact is disposed between the second conductive pillar and the second insulating layer.
10. The memory device according to claim 1, wherein the first conductive pillar is a single-layer structure or multi-layer structure.
4. The memory device according to claim 1, wherein each of the first and second conductive pillars forms a single-layer structure or a multi-layer structure.
11. The memory device according to claim 1, further comprising a landing pad disposed over the first conductive pillar.
5. The memory device according to claim 1, further comprising a landing pad disposed over the first conductive pillar.
12. The memory device according to claim 11, wherein the landing pad and the first conductive pillar are made of different conductive materials.
7. The memory device according to claim 6, wherein the landing pad, the bit line and the first and second conductive pillars are made of different conductive materials.
13. The memory device according to claim 12, wherein a resistivity of the landing pad is less than a resistivity of the first conductive pillar.
8. The memory device according to claim 7, wherein resistivities of the landing pad and the bit line are less than resistivities of the first and second conductive pillars.
14. The memory device according to claim 1, further comprising a second contact disposed over the landing pad and disposed between the capacitor and the landing pad.
9. The memory device according to claim 7, further comprising a third contact disposed over the landing pad and disposed between the first capacitor and the landing pad.
15. The memory device according to claim 14, wherein the capacitor is electrically connected to the active area through the second contact, the landing pad, the first conductive pillar, the first contact and the conductive layer.
10. The memory device according to claim 9, wherein the capacitor is electrically connected to the first active area through the third contact, the landing pad, the first conductive pillar, the first contact and the conductive layer.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Relevant Prior Art
5. The prior art made of record and not relied upon is considered pertinent to the applicant's disclosure.
Su et al. (US 20080197442 A1)
Pan et al. (US 20130001683 A1)
Gee et al. (US 20160351625 A1)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Omar Mojaddedi whose telephone number is 313-446-6582. The examiner can normally be reached on Monday – Friday, 8:00 a.m. to 4:00 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado, can be reached on 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/OMAR F MOJADDEDI/Examiner, Art Unit 2898
Prosecution Insights