DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
2. Applicant’s election without traverse of Group I (claims 1-16) filed on 03/25/2026 and withdrawn Group II (claims 17-20) has been acknowledged and considered.
Because Applicants did not distinctly and specifically point out the supposed error in the restriction requirement, the election has been treated as an election without traverse (MPEP 818.03(a)). Applicants have the right to file a divisional application covering the subject matter of the non-elected claims (claims 17-20).
Claims 1-20 are currently pending in the application.
Oath/Declaration
3. The oath/declaration filed on 12/07/2023 is acceptable.
Information Disclosure Statement
4. The office acknowledges receipt of the following items from the applicant:
Information Disclosure Statement (IDS) filed on 12/07/2023 and 12/18/2024.
Specification
5. The specification is objected to for the following reason: The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed (see MPEP 606.01).
A title such as – SEMICONDUCTOR PACKAGE INCLUDING A PACKAGE SUBSTRATE, AN INTEGRATED INTERCONNECT STRUCTURE, AN OPTICAL ENGINE MODULE AND AN INTEGRATED CIRCUITPACKAGE – or is suggested by the applicant.
Note that the claims are directed to a semiconductor device instead of a method of making a semiconductor device.
The specification needs to be updated.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless --
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by ZENG Z (CN-116893475-A).
Regarding claim 1, ZENG Z discloses a semiconductor package, comprising:
a package substrate (112) (refers as a substrate (112), see substrate (150), Fig. 1A and para [0033] in Dogiamis et al. (U.S. Publication No. 2022/0399294 A1));
an integrated interconnect structure (916) bonded over the package substrate (112) and comprising an insulation body (920) and a plurality of through vias (922) extending through the insulation body (920);
an optical engine module comprising an electronic die (904), a photonic die (912), and a waveguide (926), wherein a portion (926) of the optical engine module is embedded in the integrated interconnect structure (916); and
an integrated circuit package (918) bonded over the integrated interconnect structure (916) and electrically coupled to the optical engine module (904 of the optical engine module) (Fig. 9 and English Text).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. Claim 4 is rejected under 35 U.S.C. 103(a) as being unpatentable over ZENG Z in view of Wang et al., hereafter “Wang” (U.S. Patent No. 10,162,139 B1).
Regarding claim 4, ZENG Z discloses the features of the claimed invention as discussed above, but does not disclose wherein the waveguide comprises an optical dielectric waveguide.
Wang, however, discloses wherein the waveguide (122) comprises an optical dielectric waveguide (Fig. 1D and col. 3, lines 19-20).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of ZENG Z to provide wherein the waveguide comprises an optical dielectric waveguide as taught by Wang for a purpose of improving the transmission efficiency of the waveguide.
8. Claim 10 is rejected under 35 U.S.C. 103(a) as being unpatentable over ZENG Z in view of KIM et al., hereafter “KIM” (U.S. Publication No. 2022/0173082 A1).
Regarding claim 10, ZENG Z discloses the features of the claimed invention as discussed above, but does not disclose wherein the integrated circuit package comprises a processing die and a memory die bonded over an interposer, and an encapsulating material laterally encapsulating the processing die and the memory die.
KIM, however, discloses wherein the integrated circuit package comprises a processing die and a memory die (520, para [0043[) bonded over an interposer (200, para [0035]), and an encapsulating material (530, para [0037]) laterally encapsulating the processing die and the memory die (520) (Fig. 1B and para [0035]-[0051]).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of ZENG Z to provide wherein the integrated circuit package comprises a processing die and a memory die bonded over an interposer, and an encapsulating material laterally encapsulating the processing die and the memory die as taught by KIM for a purpose of improving the structural coupling between the interposer and package substrate.
Allowable Subject Matter
9. The following is a statement of reason for the indication of allowable subject matter:
Claims 11-16 would be allowed.
Regarding claim 11, ZENG Z (CN-116893475-A) discloses a semiconductor package, comprising: a package substrate (912); an integrated interconnect structure (916) comprising an insulation body (920) and a plurality of through vias (922) extending through the insulation body (920); an optical engine module bonded to the integrated interconnect structure (916) and comprising an electronic die (904), a photonic die (912) and a waveguide (26) (Fig. 9 and English Text).
PARK et al. (U.S. Publication No. 2023/0411263 A1) discloses an interconnect device (720, para [0080]) embedded in the integrated interconnect structure (780, para [0127]) (Fig. 16A).
ZENG Z and PARK, however, either alone or together in any combination, do not disclose, teach, or otherwise suggest a feature of “an integrated circuit package bonded over the integrated interconnect structure and electrically coupled to the optical engine module through the interconnect device” as cited in the independent claim 11.
Claims 12-16 are directly or indirectly depend on the independent claim 11, then, they are also being allowed.
Claims 2-3 and 5-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Cited Prior Arts
10. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Yu et al. (U.S. Publication No. 2023/0244043 A1) discloses an interconnect structure 80 is formed. The respective process is illustrated as process 324 in the process flow 300 as shown in FIG. 27. Interconnect structure 80 includes dielectric layers 82 and Redistribution Lines (RDLs) 84 in dielectric layers 82. RDLs 84 are connected to, and may interconnect, package components 34′, 44, and 46. RDLs 84 may include copper, titanium, nickel, or the like (Fig. 16 and 17 and para [0053]).
YU Z (CN-114883202-A1) discloses the package body 2301 is formed, the second photonic interconnect structure 2507 may be mounted to the package substrate 407 using the first external contact element 303 as described above. Once installed, a first bottom filler 409 can be formed between the second photonic interconnect structure 2507 and the package substrate 407 (Fig. 25 and English Text).
Conclusion
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Phuc T. Dang whose telephone number is 571-272-1776. The examiner can normally be reached on 8:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PHUC T DANG/Primary Examiner, Art Unit 2897
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