DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Preliminary Amendment
Claim 1 has been cancelled; claims 2-25 have been newly added; and claims 2-25 are currently pending.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d).
Information Disclosure Statement
The information disclosure statements filed on 12/26/2024, 04/19/2024, and 12/08/2023 have been acknowledged and signed copies of the PTO-1449 are attached herein.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-10, 12, 16-22, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon (US 2017/0011685 A1, hereinafter “Jeon”) in view of Lee et al. (KR 20160008020 A, hereinafter “Lee’).
In regards to claim 2, Jeon discloses (see, for example, Figs. 1, 4 and 7) an organic light emitting diode (OLED) display (See, Abstract), comprising:
a substrate (110);
a pixel (PX); and
a scan line (151, 152), a data line (171), and a driving voltage line (172) connected to the pixel (PX),
wherein the pixel (PX) includes:
an organic light emitting diode (OLED);
a first transistor (T1); and
a second transistor (T3) connected to the scan line (See, for example, 151),
the second transistor includes a semiconductor layer (131c/130, See Par [0147]), and
one end of the semiconductor layer (S3/131c_1) of the second transistor (T3) is connected to one end of a semiconductor layer (D1/137a) of the first transistor (T1) and the other end of the semiconductor layer (D3/137c_1) of the second transistor (T3) is electrically connected to a gate electrode (G1/155a) of the first transistor (T1) (See also, Figs. 1, 5 and Pars [0164] and [0189]).
Though Jeon recognizes that external light incident on the compensation transistor causes leakage current, which deteriorates luminance and causes flickering as discussed in Pars [0007]-[0009], and provides a light blocking member 74 formed above the compensation transistor to address this issue, See Pars [0192]-[0196]), it fails to explicitly teach
a bottom electrode on the substrate;
the bottom electrode, disposed between the second transistor and the substrate, includes a first portion disposed in an area that overlaps the second transistor on a plane,
the bottom electrode is exposed by a contact hole which is disposed outside of the pixel.
Lee while disclosing an organic light emitting display device teaches (See, for example, Figs. 5 and 7)
a bottom electrode (210, 220) on the substrate (100);
the bottom electrode (210, 220), disposed between the second transistor and the substrate, includes a first portion disposed in an area that overlaps the second transistor on a plane,
the bottom electrode is exposed by a contact hole which is disposed outside of the pixel (light shielding patterns are electrically connected through contact holes (H1, H2, See Figs. 5 and 7) to a source electrode 524 of the driving thin film transistor T2 to prevent crosstalk. The contact holes H1 and H2 connecting the light shielding layer patterns to the source electrode are disposed in the circuit/transistor region, outside of the light-emitting pixel area defined by the anode 800 and bank layer, See, pp. 9-10, and Figs. 5 and 7).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have modified the OLED display of Jeon by forming a bottom electrode between the substrate and the compensation transistor, the bottom electrode overlapping the compensation transistor and being exposed by a contact hole disposed outside the pixel area, in order to more effectively block external light from reaching the compensation transistor from below the substrate, thereby further suppressing leakage current and preventing luminance deterioration and flickering.
Furthermore, Jeon already identifies external light-induced leakage in the compensation transistor as a problem to be solved, Lee provides a complementary solution of blocking/shielding from bottom. The placement of contact hole outside the pixel or the light emitting area would have been an obvious design choice to maximize aperture ratio. See KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007) (combining known techniques to yield predictable result).
In regards to claim 17, Jeon discloses (See, for example, Fig. 7) an organic light emitting diode (OLED) display (See, abstract), comprising
a substrate (110);
a buffer layer (120, Par [0200]);
a semiconductor layer (130, Par [0202]) on the buffer layer (120);
a first gate insulation layer (141, Par [0207]) that covers the semiconductor layer (130);
a first gate layer (151, 152, 153, 155a, Par [0208]) on the first gate insulation layer (141);
an interlayer insulation layer (160) that covers the first gate layer (151, 152, 153, 155a) and the first gate insulation layer (141);
a data layer (data metal lines, 171, 172, 174, 175, 179, Par [0217]) on the first gate insulation layer (141);
a passivation layer (180) that covers the data layer (data metal lines, 171, 172, 174, 175, 179) and the interlayer insulation layer (160);
a transistor (T3) that includes a channel (See, for example, 131c) formed in the semiconductor layer (130) and a gate electrode (155c) formed in the first gate layer (151, 152, 153, 155a); and
an organic light emitting diode (OLED) electrically connected to the transistor (T1),
a pixel (PX, Par [0080]) includes the organic light emitting diode (OLED) and at least one transistor (T1-T7) electrically connected to the organic light emitting diode (OLED),
a pixel area (area that encompasses the transistors T1-T7, Fig. 1) is an area that the at least one transistor (T1-T7) included in the pixel (PX) is disposed on a plane (see, for example, Fig. 4),
the transistor of the pixel (PX) includes a plurality of transistors (T1-T7),
the plurality of transistors (T1-T7) include:
a first transistor (T1) electrically connected to the organic light emitting diode (OLED); and
a second transistor (T3) connected to a scan line (151),
the second transistor (T3) includes a semiconductor layer (131c), and one end of the semiconductor layer (S3/136c) of the second transistor (T3) is connected to one end of a semiconductor layer (D1/137a) of the first transistor (T1) and the other end of the semiconductor layer (D3/137c) of the second transistor (T3) is electrically connected to a gate electrode (G1/155a) of the first transistor (T1).
Though Jeon recognizes that external light incident on the compensation transistor causes leakage current, which deteriorates luminance and causes flickering as discussed in Pars [0007]-[0009], and provides a light blocking member 74 formed above the compensation transistor to address this issue, See Pars [0192]-[0196]), it fails to explicitly teach
a bottom electrode on the substrate;
the bottom electrode is exposed by the contact hole which is disposed in the pixel area,
wherein the bottom electrode overlaps the channel of the transistor on a plane, a contact hole is formed in at least a part of the buffer layer, the first gate insulation layer, or the interlayer insulation layer.
Lee discloses (See, for example, Figs. 5 and 7) a bottom electrode (210, 220) on the substrate (100);
the bottom electrode (210, 220) is exposed by the contact hole (H1, H2) which is disposed in the pixel area (the area that encompasses the transistors),
wherein the bottom electrode (210, 220) overlaps the channel (300) of the transistor on a plane, a contact hole (H1, H2) is formed in at least a part of the buffer layer (250), the first gate insulation layer, or the interlayer insulation layer (450).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have modified the OLED display of Jeon by forming a bottom electrode below the buffer layer, overlapping the channel of the compensation transistor, and providing a contact hole through the buffer layer and insulating layers within the pixel area to expose the bottom electrode for electrical connection in order to more effectively block external light from reaching the compensation transistor from below the substrate, thereby further suppressing leakage current and preventing luminance deterioration and flickering.
Furthermore, Jeon already identifies external light-induced leakage in the compensation transistor as a problem to be solved, Lee provides a complementary solution of blocking/shielding from bottom. The placement of contact hole outside the pixel or the light emitting area would have been an obvious design choice to maximize aperture ratio. See KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007) (combining known techniques to yield predictable result).
In regards to claim 3, Jeon as modified above discloses (See, for example, Fig. 7, LEE) the bottom electrode (210, 220) is electrically connected with one of the scan line, the data line, the driving voltage line, the second transistor, the first transistor, and one terminal of the organic light emitting diode through the contact hole (See, for example, page 6 last paragraph and page 7).
In regards to claim 4, Jeon as modified above discloses (See, Fig. 7, Lee) that the bottom electrode (210, 220) further includes a second portion disposed in an area that overlaps the first transistor on a plane (for example, the bottom electrode 210 is formed as a continuous pattern that covers both the switching transistor T1 and driving transistor T2, See Figs. 5 and 7-9).
In regards to claim 5, Jeon as modified above discloses (See, for example, Figs. 5-9, Lee) the second portion of the bottom electrode (210, 220), overlapping the first transistor (See, for example, any one of T1-T3), has a width that is wider than a width of a gate electrode of the first transistor (See, Figs. 7-9).
In regards to claim 6, Jeon as modified above discloses (See, for example, Figs. 5-9) the second portion of the bottom electrode (210, 220) is connected with the driving voltage line (See, for example, pp. 6-7) through the contact hole (H1, H2).
In regards to claim 7, Jeon as modified above discloses (See, for example, Fig. 7, Lee) the first portion of the bottom electrode and the second portion of the bottom electrode (210, 220) are separated from each other, the second portion has a second contact hole (See, for example, H1) exposing a part of the second portion, and the first portion and the second portion are electrically connected to different line from each other (the first light shielding layer pattern 210 and the second light shielding layer pattern 220 are spaced apart from each other… See, for example, page 6).
In regards to claim 8, Jeon as modified above discloses (See, for example, Fig. 1) an initialization voltage line (Vint) connected to the pixel (PX), wherein the pixel (PX) further includes a third transistor (T4) including a semiconductor layer (131d, Par [0147]), one end of the semiconductor layer (S4) of the third transistor (T4) is electrically connected to the initialization voltage line (Vint) and the other end of the semiconductor layer (D4) of the third transistor (T4) is electrically connected to a gate electrode (G1) of the first transistor (T1)
, and the bottom electrode (210, 220, Figs. 5-9, Lee) further includes a third portion disposed in an area that overlaps the third transistor on a plane (See, Figs. 5-9).
In regards to claim 9, Jeon as modified above discloses (See, for example, Fig. 1, Jeon; and Figs. 5-9, Lee) the bottom electrode (210, 220, Lee) is electrically connected with the initialization voltage line (directly or indirectly connected to Vint).
In regards to claim 10, Jeon as modified above diclosoes (See, for example, Figs. 5-9, Lee) the bottom electrode (210, 220) is connected with the driving voltage line (See, pp. 6-7) through the contact hole (H1, H2).
In regards to claim 12, Jeon as modified above discloses (See, for example, Fig. 1) an initialization voltage line (Vint) connected to the pixel (PX), wherein the pixel (PX) further includes at least one of: a fourth transistor (T5) that includes a first electrode (S5) connected with the driving voltage line (ELVDD) and a second electrode (D5) connected with an input side electrode (S1) of the first transistor (T1); a fifth transistor (T6) that includes a first electrode connected with an output side electrode (S6) of the first transistor (D1) and a second electrode (D6) connected with the organic light emitting diode (OLED); and a sixth transistor (T7) that includes a first electrode (S7) connected with the organic light emitting diode (OLED) and a second electrode (D7) connected with the initialization voltage line (Vint).
In regards to claim 16, Jeon as modified above discloses (See, for example, Fig. 5, Lee) the bottom electrode (see, for example, 210) does not overlap at least a part of the pixel (pixel includes the OLED, E, but it is not covered by 210).
In regards to claim 18, Jeon as modified above discloses (see, for example, Figs. 5-9, Lee) the bottom electrode (210, 220) is electrically connected with one of the scan line, a data line, a driving voltage line, an initialization voltage line, a previous scan line, a light emission control line, one terminal of one of the plurality of transistors, and one terminal of an organic light emitting diode (See, for example, pp. 6-7).
In regards to claim 19, Jeon as modified above discloses (See, for example, Figs. 5-9, Lee) the bottom electrode (210, 220) includes a first portion (area of 210, 220 covering T1) disposed in an area that overlaps (continuously formed layers 210, 220, See Fig. 7) the second transistor (See, for example, T2) on a plane.
In regards to claim 20, Jeon as modified above discloses (See, for example, Fig. 5) a channel of the first transistor is formed in the semiconductor layer, and the semiconductor layer has one of Q, inverted S, S, M, and W shapes (See, for example, Par [0153]).
In regards to claim 21, Jeon as modified above discloses that the bottom electrode (210, 220, Lee) is formed of a conductive material.
However, Jeon as modified by Lee fails to specifically teach that the bottom electrode is formed of metal or a semiconductor material.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to select a conductive material of either metal or semiconductor since it has been held to be wi thin the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
In regards to claim 22, Jeon as modified above discloses all limitations of claim 17 except that the substrate is provided in plural, and a barrier layer is further included in at least one portion between substrates.
It is readily known in the art to form a substrate as a multi-layer structure comprising plural substrate layers with a barrier layer, for example, inorganic layers such as silicon dioxide or silicon nitride, interposed between the substrate layers, in order to prevent moisture and oxygen from penetrating through the substrate and reaching the organic light emitting elements, thereby improving device reliability and lifespan.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to include plural substrates and a barrier layer in between the substrates because it is readily known in the art to form a substrate as a multi-layer structure comprising plural substrate layers with a barrier layer, for example, inorganic layers such as silicon dioxide or silicon nitride, interposed between the substrate layers, in order to prevent moisture and oxygen from penetrating through the substrate and reaching the organic light emitting elements, thereby improving device reliability and lifespan.
In regards to claim 25, Jeon as modified above discloses (See, for example, Fig. 5, Lee) the contact hole (H1, H2) exposing the bottom electrode (210, 220) is disposed in the pixel area (See, for example, PX, Jeon) which involves the channel of one of the plurality of transistors overlapping the bottom electrode (See, 300 overlapping 210, 220, Fig. 7).
Allowable Subject Matter
Claims 11, 13-15, and 23-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893