DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claim 1 has been cancelled; claims 17, 18, 20 and 22 have been amended; and claims 2-25 are currently pending.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d).
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 18 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In regards to claim 18, claim 18 re-introduces “a data line” and “a driving voltage line,” which claim 2 already recites. Those should read “the.”
In regards to claim 20, claim 20 recites “a plurality of substrates,” however, claim 17 recites “a substrate.” It is unclear whether “the substrate” is one of the plurality.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17, 19, 21 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon (US 2017/0011685 A1, hereinafter “Jeon”) in view of Lee et al. (KR 20160008020 A, hereinafter “Lee’) and Oh et al. (US 2016/0380039 A1, hereinafter “Oh”).
In regards to claim 17, Jeon discloses (See, for example, Fig. 7) an organic light emitting diode (OLED) display (See, abstract), comprising
a substrate (110);
a buffer layer (120, Par [0200]);
a semiconductor layer (130, Par [0202]) on the buffer layer (120);
a first gate insulation layer (141, Par [0207]) that covers the semiconductor layer (130);
a first gate layer (151, 152, 153, 155a, Par [0208]) on the first gate insulation layer (141);
an interlayer insulation layer (160) that covers the first gate layer (151, 152, 153, 155a) and the first gate insulation layer (141);
a data layer (data metal lines, 171, 172, 174, 175, 179, Par [0217]) on the first gate insulation layer (141);
a passivation layer (180) that covers the data layer (data metal lines, 171, 172, 174, 175, 179) and the interlayer insulation layer (160);
a transistor (T3) that includes a channel (See, for example, 131c) formed in the semiconductor layer (130) and a gate electrode (155c) formed in the first gate layer (151, 152, 153, 155a); and
an organic light emitting diode (OLED) electrically connected to the transistor (T1),
a pixel (PX, Par [0080]) includes the organic light emitting diode (OLED) and at least one transistor (T1-T7) electrically connected to the organic light emitting diode (OLED),
a pixel area (area that encompasses the transistors T1-T7, Fig. 1) is an area that the at least one transistor (T1-T7) included in the pixel (PX) is disposed on a plane (see, for example, Fig. 4),
the transistor of the pixel (PX) includes a plurality of transistors (T1-T7),
the plurality of transistors (T1-T7) include:
a first transistor (T1) electrically connected to the organic light emitting diode (OLED); and
a second transistor (T3) connected to a scan line (151),
the second transistor (T3) includes a semiconductor layer (131c), and one end of the semiconductor layer (S3/136c) of the second transistor (T3) is connected to one end of a semiconductor layer (D1/137a) of the first transistor (T1) and the other end of the semiconductor layer (D3/137c) of the second transistor (T3) is electrically connected to a gate electrode (G1/155a) of the first transistor (T1).
Though Jeon recognizes that external light incident on the compensation transistor causes leakage current, which deteriorates luminance and causes flickering as discussed in Pars [0007]-[0009], and provides a light blocking member 74 formed above the compensation transistor to address this issue, See Pars [0192]-[0196]), it fails to explicitly teach
a bottom electrode on the substrate;
the bottom electrode is exposed by the contact hole which is disposed in the pixel area,
wherein the bottom electrode overlaps the channel of the transistor on a plane, a contact hole is formed in at least a part of the buffer layer, the first gate insulation layer, or the interlayer insulation layer.
Lee discloses (See, for example, Figs. 5 and 7) a bottom electrode (210, 220) on the substrate (100);
the bottom electrode (210, 220) is exposed by the contact hole (H1, H2) which is disposed in the pixel area (the area that encompasses the transistors),
wherein the bottom electrode (210, 220) overlaps the channel (300) of the transistor on a plane, a contact hole (H1, H2) is formed in at least a part of the buffer layer (250), the first gate insulation layer, or the interlayer insulation layer (450).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have modified the OLED display of Jeon by forming a bottom electrode below the buffer layer, overlapping the channel of the compensation transistor, and providing a contact hole through the buffer layer and insulating layers within the pixel area to expose the bottom electrode for electrical connection in order to more effectively block external light from reaching the compensation transistor from below the substrate, thereby further suppressing leakage current and preventing luminance deterioration and flickering.
Furthermore, Jeon already identifies external light-induced leakage in the compensation transistor as a problem to be solved, Lee provides a complementary solution of blocking/shielding from bottom. The placement of contact hole outside the pixel or the light emitting area would have been an obvious design choice to maximize aperture ratio. See KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007) (combining known techniques to yield predictable result).
Jeon in view of Lee fails to explicitly teach that the bottom electrode is directly connected to one of the scan line, a data line, a driving voltage line, an initialization voltage line, a previous scan line, a light emission control line, and a common voltage line.
Oh while disclosing a display device teaches (See, for example, Figs. 8 and 18-24) the bottom electrode (151) is directly connected to one of the scan line, a data line, a driving voltage line, an initialization voltage line, a previous scan line, a light emission control line, and a common voltage line (“in order to connect the sensing line VREF to all of the first subpixel SPn1 to fourth subpixel SPn4, the horizontal sensing line VREFS is configured by using a light blocking layer 151 formed on a first substrate 150a and the horizontal sensing line VREFS and the vertical sensing line VREF are electrically connected.” See Par [0067]; “The horizontal sensing line VREFS is configured as the light blocking layer 151, and the light blocking layer 151 and the source/drain metal layer 157 are electrically connected through a first contact hole CH1.”, See Par [0068]; and “The source/drain metal layer 157 (one portion) corresponding to the horizontal sensing line of the first subpixel is connected to the light blocking layer 151 as a connection electrode through a first contact hole CH1. The source/drain metal layer 157 (the other portion) corresponding to the horizontal sensing line of the second subpixel is connected to the light blocking layer 151 as a connection electrode through a second contact hole CH2.”, See Par [0104], Sensing line VREF, VREFS/VREFM formed of source/drain metal line 157, which supplies the “initialization voltage”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to form a portion of Jeon/Lee’s bottom electrode so that it directly contacts Jeon’s initialization voltage line, as Oh’s does because the device prevents shortage between the data line and the sensing line due to utilization of a gate metal layer and the source/drain metal layer so as to improve image quality.
In regards to claim 19, Jeon as modified above discloses (See, for example, Figs. 5-9, Lee) the bottom electrode (210, 220) includes a first portion (area of 210, 220 covering T1) disposed in an area that overlaps (continuously formed layers 210, 220, See Fig. 7) the second transistor (See, for example, T2) on a plane.
In regards to claim 21, Jeon as modified above discloses that the bottom electrode (210, 220, Lee) is formed of a conductive material.
However, Jeon as modified by Lee fails to specifically teach that the bottom electrode is formed of metal or a semiconductor material.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to select a conductive material of either metal or semiconductor since it has been held to be wi thin the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
In regards to claim 25, Jeon as modified above discloses (See, for example, Fig. 5, Lee) the contact hole (H1, H2) exposing the bottom electrode (210, 220) is disposed in the pixel area (See, for example, PX, Jeon) which involves the channel of one of the plurality of transistors overlapping the bottom electrode (See, 300 overlapping 210, 220, Fig. 7).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Lee and Oh as applied to claim 17 above, and further in view of Seo et al. (US 2016/0141551 A1, hereinafter “Seo”).
In regards to claim 20, Jeon as modified above discloses (See, for example, Fig. 5) a channel of the first transistor is formed in the semiconductor layer, and the semiconductor layer has one of Q, inverted S, S, M, and W shapes (See, for example, Par [0153]).
However, Jeon as modified above fails to explicitly teach that the OLED display includes a plurality of substrates (stacked on each other that are flexible and comprised of plastic or polyimide.
Seo while disclosing an OLED display device teaches (See, for example, Fig. 1) the OLED display (100) includes a plurality of substrates (a first plastic layer 1PL, a second plastic layer 2PL) stacked on each other that are flexible (FS, See Par [0060]) and comprised of plastic or polyimide (See also, Par [0061]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to form the substrate of Jeon as modified by Lee and Oh as a plurality of stacked flexible substrates, as taught by Seo because this would provide a flexible display whose barrier layers between the plastic layers give a low water vapor transmission rate, protecting the TFT and the OLED from moisture and oxygen, while the intermediate layers improve adhesion between layers.
Allowable Subject Matter
Claims 23-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 2 is allowed over the prior art of record.
The following is an examiner’s statement of reasons for allowance:
The prior art of record, taken alone or in combination, fails to teach or reasonably suggest an organic light emitting diode (OLED) display comprising, in combination with the other recited limitations of claim 2, a bottom electrode underlying such a compensation connected second transistor and exposed by a contact hole disposed outside of the pixel that includes the OLED, the first transistor and the second transistor, as shown in Applicant’s Figs. 5-7 and 13 (contact hole 57 in an adjacent pixel, See applicant’s remarks pp. 8-14 as filed on 6/12/2026).
Claims 3-16, 18 and 22 are allowable by virtue of their dependency on claim 2.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments, see pp. 8-14, filed on 6/12/2026, with respect to claim 2 have been fully considered and are persuasive. The rejection of claim 2 has been withdrawn.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893
Prosecution Insights