Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I in the reply filed on 04/20/2026 is acknowledged. Claims 1-20 are examined below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20170186782 A1) in view of Kim (US 20220392984 A1).
Re: Independent Claim 1, Lee discloses a display apparatus comprising:
a first transistor including a first semiconductor layer including a silicon semiconductor, wherein the first transistor controls a magnitude of a driving current flowing to a display element (Lee teaches, in Fig. 3 and ¶ [0058], first transistor T1 in pixel 200 includes silicon semiconductor layer, and T1 is used to drive light emitting diode D1);
a data line which transmits a data voltage (Lee teaches, in ¶ [0089], data line Data, wherein the voltage of data line (Data) is a data write voltage (Vdata) during a data- writing period);
a second transistor (Lee Fig. 3, Transistor T3) including a second semiconductor layer including an oxide semiconductor (Lee ¶ [0074], T3 comprises the oxide semiconductor layer), wherein the second transistor connects the data line to the first transistor in response to a scan signal (Lee Fig. 3 and ¶ [0082], T3 is controlled by signal Sn, connects data line Data to the control terminal c2 of first transistor T1, and writes data voltage Vdata from the data line to node G during the data-writing period); and
a first capacitor including a first electrode and a second electrode (Lee, Fig. 3, first capacitor Cst with first electrode connected to the control terminal c2 of first transistor T1 and second electrode connected to terminal b2 of first transistor T1).
Lee is silent regarding
wherein the first electrode is disposed on the first semiconductor layer, and the second electrode at least partially overlaps the first electrode; and a first gate electrode below the first semiconductor layer.
However, Kim teaches wherein the first electrode is disposed on the first semiconductor layer, and the second electrode at least partially overlaps the first electrode (Kim teaches, in Figs. 2-4 and ¶ [0077], a first capacitor corresponding to storage capacitor Cst, wherein the first electrode corresponds to capacitor electrode CE and the second electrode corresponds to second gate electrode GE2. Kim teaches, in Fig. 4, that capacitor electrode CE is disposed on active layer ACT of driving transistor DRT, and second gate electrode GE2 is overlapping capacitor electrode CE (GE2 and CE overlap each other) to form storage capacitor Cst); and a first gate electrode below the first semiconductor layer (Kim teaches, in Fig. 4, gate electrode GE1 that is below the active layer ACT, such that first gate electrode GE1 is a bottom gate electrode).
Kim teaches a display-subpixel driving transistor and storage capacitor in the same field as Lee and directed to the same goal of current stability and area reduction. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee’s silicon driving transistor T1 and storage capacitor using Kim’s bottom-gate driving-transistor and stacked storage-capacitor structure to improve current output and stability while reducing subpixel circuit area (Kim, ¶ [0016]).
Re: Claim 2, Lee and Kim disclose all the limitations of claim 1 on which this claim depends.
Kim further teaches
wherein the second electrode is electrically connected to the first gate electrode (Kim teaches, in ¶ [0071], that GE1 and GE2 form double gate electrodes that generate an electric field to increase output current of driving transistor DRT. Kim further teaches, in ¶ [0128], the driving transistor DRT can include two gate electrodes electrically connected to the first node N1 which the data voltage is applied, confirming that GE2 functions as a gate electrode electrically tied to the same driving-transistor gate node as GE1).
Re: Claim 3, Lee and Kim disclose all the limitations of claim 2 on which this claim depends.
Kim further teaches
further comprising: a sub-voltage line disposed on the second electrode (As explained for claim 1, CE is the claimed first electrode and GE2 is the claimed second electrode. Kim further teaches, in Fig. 2, first driving voltage line DVL1 supplying first driving voltage Vdd, where first driving voltage line DVL1 corresponds to the claimed sub-voltage line. Kim further teaches, in Fig. 4, that second gate electrode GE2 is disposed over the active layer ACT, capacitor electrode CE is disposed over second gate electrode GE2, and an interlayer insulating layer ILD is disposed over capacitor electrode CE, and first driving voltage line DVL1 is disposed over the ILD (see ¶ [0073]). Thus, first driving voltage line DVL1 is disposed on second gate electrode GE2).
and electrically connected to the first electrode (Kim teaches, in Fig. 2 and ¶ [0077], that a constant voltage, e.g., first driving voltage Vdd, is applied to capacitor electrode CE, and that the storage capacitor Cst is electrically connected between first node N1 and second node N2, to which driving voltage Vdd is supplied. To the extent Kim does not expressly disclose a direct contact between DVL1 and CE, it would have been obvious to electrically connect DVL1 to CE because Kim teaches that DVL1 supplies Vdd, and CE is the capacitor/gate electrode to which the constant voltage Vdd is applied. Providing a conductive contact or via from the Vdd line to the electrode receiving Vdd would have been a routine interconnection needed to implement Kim’s disclosed circuit).
Re: Claim 4, Lee and Kim disclose all the limitations of claim 3 on which this claim depends.
Kim further teaches
wherein the first gate electrode, the first electrode, the second electrode, and the sub-voltage line at least partially overlap each other (Kim teaches, in Fig. 4, first gate electrode GE1, first electrode CE, second electrode second electrode GE2 overlap each other. Further, as shown in Fig. 3 where DVL1 runs along GE2, and DVL1 being disposed over ILD as explained for claim 3 above, the sub-voltage line DVL1 also overlaps GE1/GE2/CE).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20170186782 A1) in view of Kim (US 20220392984 A1) further in view of Sun (US 20060121310 A1).
Re: Claim 5, Lee and Kim disclose all the limitations of claim 3 on which this claim depends.
Lee and Kim are silent regarding
further comprising: a second capacitor including the first gate electrode and the first electrode; and a third capacitor including the second electrode and the sub-voltage line, wherein the first capacitor, the second capacitor, and the third capacitor are connected in parallel with each other.
However, Sun teaches further comprising: a second capacitor including the first gate electrode and the first electrode; and a third capacitor including the second electrode and the sub-voltage line, wherein the first capacitor, the second capacitor, and the third capacitor are connected in parallel with each other (Sun teaches, in Fig. 1, an OLED pixel having multiple vertically stacked storage capacitors 108 and 112 formed over the same area and connected in parallel. Sun further teaches, in ¶ [0046] and Fig. 11, including more than two capacitors may be formed over the same area (area A) of substrate 200 and connected in parallel with one another. Thus, Sun teaches alternating stacked conductive layers connected to two common nodes to form parallel storage capacitors.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to apply Sun’s stacked parallel capacitor arrangement to Kim’s stacked conductors so that additional capacitors are formed between Kim’s common gate node N1 and common Vdd/constant voltage node N2. Specifically, it would have been obvious to form a second capacitor between GE1 and CE, because GE1 is tied to node N1 and CE is tied to node N2, and to form a third capacitor between GE2 and DVL1, because GE2 is tied to node N1 and DV1 is tied to node N2. These capacitors would have been connected in parallel with Kim’s first capacitor formed by CE and GE2 because all three capacitors are connected between the same two nodes, N1 and N2. The motivation would have been to increase storage capacitance without increasing the occupied pixel area, as taught by Sun in ¶ [0047]).
Claim(s) 6-7, 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20170186782 A1) in view of Kim (US 20220392984 A1) further in view of Son (US 20210265437 A1).
Re: Claim 6, Lee and Kim disclose all the limitations of claim 1 on which this claim depends.
Lee and Kim are silent regarding
wherein the second transistor further includes: a second lower gate electrode below the second semiconductor layer; and a second upper gate electrode above the second semiconductor layer.
However, Son teaches
wherein the second transistor further includes: a second lower gate electrode below the second semiconductor layer; and a second upper gate electrode above the second semiconductor layer (Although Lee teaches the claimed second transistor T3, wherein T3 includes an oxide semiconductor layer, Lee does not expressly teach that the second transistor further includes a second lower gate electrode below the second semiconductor layer and a second upper gate electrode above the second semiconductor layer. However, Son teaches, in Figs. 3 and 10, and ¶ [0089], ¶ [0126], compensation transistor T3 having compensation semiconductor layer A3, first lower gate electrode G3a arranged under compensation semiconductor layer A3, and first upper gate electrode G3b arranged over compensation semiconductor layer A3.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement Lee’s oxide semiconductor data-writing transistor T3 using Son’s double-gate oxide transistor structure, including lower gate electrode G3a below oxide semiconductor layer A3 and upper gate electrode G3b above oxide semiconductor layer A3, in order to reduce the space occupied by the oxide thin film transistor and provide high quality images while being highly integrated (Son, ¶ [0183])).
Re: Claim 7, Lee, Kim and Son disclose all the limitations of claim 6 on which this claim depends.
Son further teaches
wherein the second lower gate electrode is disposed in a same layer as a layer in which the first electrode is disposed, and the second upper gate electrode is disposed in a same layer as a layer in which the second electrode is disposed (As explained for claim 1, Lee teaches the claimed first capacitor Cst in the pixel circuit, which includes first and second capacitor electrodes. Son teaches, in ¶ [0106], storage capacitor Cap having first electrode CE1 and second electrode CE2. Son teaches, in Fig. 10 and ¶ [0112], compensation transistor T3 including oxide semiconductor layer A3, first lower gate electrode G3a under A3, and first upper gate electrode G3b over A3. Son also teaches, in ¶ [0130], first initialization transistor T4 including oxide semiconductor layer A4, second lower gate electrode G4a under A4, second upper gate electrode G4b over A4. Son teaches, in ¶ [0130], that second electrode CE2 of the storage capacitor Cap and lower gate electrodes G3a/G4a are arranged in the same layer and include same material. Son further teaches upper gate electrodes G3b/G4b are arranged over the oxide semiconductor layers in an upper conductive layer).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form Lee’s first capacitor electrodes in the same conductive layers used for Son’s lower and upper gate electrodes, so that the lower gate electrode is in the same layer as one capacitor electrode and the upper gate electrode is in the same layer as the other capacitor electrode, in order to use existing conductive layers, reduce additional masks/process steps, reduce TFT area, and provide a highly integrated high-resolution display panel as taught by Son.
Re: Claim 10, Lee and Kim disclose all the limitations of claim 1 on which this claim depends.
Lee and Kim are silent regarding
further comprising: an emission control line which transmits an emission control signal; an initialization voltage line which transmits an initialization voltage; a fifth transistor which connects a driving voltage line to a side of the first semiconductor layer in response to the emission control signal; a sixth transistor which connects another side of the first semiconductor layer to an anode of the display element in response to the emission control signal; and a seventh transistor which connects the initialization voltage line to the anode of the display element in response to another scan signal.
However, Son teaches
further comprising: an emission control line which transmits an emission control signal (Son teaches, in Fig. 2 and ¶ [0057], emission control line EL configured to transmit an emission control signal En); an initialization voltage line which transmits an initialization voltage (Son teaches, in Fig. 2 and ¶ [0058], initialization voltage line VIL may be configured to transmit an initialization voltage Vint); a fifth transistor which connects a driving voltage line to a side of the first semiconductor layer in response to the emission control signal (Son teaches, in Fig. 2 and ¶¶ [0057] - [0059], operation control transistor T5 has an operation control gate electrode connected to emission control line EL, an operation control source area connected to driving voltage line PL, and an operation control drain area connected to a driving source area of driving transistor T1. Thus, Son teaches operation control transistor T5 connects driving voltage line PL to the driving source area of driving transistor T1 in response to emission control signal En on emission control line EL); a sixth transistor which connects another side of the first semiconductor layer to an anode of the display element in response to the emission control signal (Son further teaches, in Fig. 2 and ¶ [0065], emission control transistor T6 having a emission control gate electrode connected to emission control line EL, an emission control source area of T6 connected to the driving drain area of driving transistor T1, and an emission control drain area of T6 electrically connected to the pixel electrode/ anode of OLED. Thus, Son teaches that emission control transistor T6 connects the driving drain area of driving transistor T1 to the pixel electrode/anode of OLED in response to emission control signal En on emission control line EL); and a seventh transistor which connects the initialization voltage line to the anode of the display element in response to another scan signal (Son teaches in Fig. 2 and related descriptions, second initialization transistor T7 has a gate electrode connected to next scan line SLn, a source area connected to initialization voltage line VIL, and a drain area connected to the pixel electrode/anode of OLED. Thus, Son teaches seventh transistor T7 which connects the initialization voltage line VIL to the anode of the display element OLED in response to another scan signal SLn).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Son’s emission-control and initialization transistor arrangement into the display apparatus of Lee and Kim in order control an emission period of the OLED and initialize the OLED pixel electrode/anode, thereby improving display-pixel operation. The modification applies a known OLED pixel circuit emission/initialization arrangement of Lee’s known active-matrix OLED pixel circuit, yielding the predictable result of a display apparatus including an emission control line, initialization voltage line, and fifth, sixth and seventh transistors arranged as claimed.
Re: Claim 11, Lee, Kim and Son disclose all the limitations of claim 10 on which this claim depends.
Son further teaches
wherein the fifth transistor includes a fifth semiconductor layer, the sixth transistor includes a sixth semiconductor layer, the seventh transistor includes a seventh semiconductor layer, and each of the fifth to seventh semiconductor layers includes the oxide semiconductor (Son teaches, in ¶ [0089], T5 includes an operation control semiconductor layer A5, T6 includes an emission control semiconductor layer A6 and T7 includes a second initialization semiconductor layer A7. Son further teaches, in ¶ [0079], at least one of the transistors T1, T2, T3, T4, T5, T6, and T7 may include a semiconductor layer including oxide).
Claim(s) 8, 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20170186782 A1) in view of Kim (US 20220392984 A1) further in view of Kim’474 (US 20200211474 A1).
Re: Claim 8, Lee and Kim disclose all the limitations of claim 1 on which this claim depends.
Lee and Kim are silent regarding
further comprising: a display panel including a display area and a non-display area outside the display area, wherein the display area includes a first display area and a second display area at least partially surrounded by the first display area, and the first and second transistors are disposed in the display area; and a component disposed below the display panel to correspond to the second display area.
However, Kim’474 teaches
further comprising: a display panel including a display area and a non-display area outside the display area, wherein the display area includes a first display area and a second display area at least partially surrounded by the first display area (Kim’474 teaches, in Figs. 11, first display area DA1 and second display area DA2, and a peripheral area PA outside the display area. DA2 is surrounded by DA1), and the first and second transistors are disposed in the display area (Kim’474 teaches, in Fig. 5, pixels PXa in the display area includes circuits and transistors for driving light-emitting elements. As explained for claim 1 above, Lee teaches transistors T1 and T3 in pixel circuit 200 of display panel 100. Therefore, Lee in view of Kim teaches that T1 and T3 are disposed in the display area); and a component disposed below the display panel to correspond to the second display area (Kim’474 teaches, in ¶ [0050] and ¶ [0052], an optical element 500 provided below display panel 30 and overlapping second display area DA2, wherein optical element 500 may be a camera, a flash, a sensor, etc.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the under-display component arrangement of Kim’474 into the display apparatus of Lee and Kim in order to provide a wider/fuller display screen while accommodating an optical component, such as camera or sensor, below a transmissive second display area of the display panel. The modification applies a known under-display optical component arrangement to a known OLED display panel and pixel-circuit structure, yielding the predictable result of a display apparatus including first display area, a second display area at least partially surrounded by the first display area, and a component below the display panel corresponding to the second display area.
Re: Independent Claim 12, Lee discloses a display apparatus comprising:
a display panel including: a first transistor including a first semiconductor layer including a silicon semiconductor, wherein the first transistor controls a magnitude of a driving current flowing to a display element (Lee teaches, in Fig. 3 and ¶ [0058], first transistor T1 in pixel 200 includes silicon semiconductor layer, and T1 is used to drive light emitting diode D1);
a data line which transmits a data voltage (Lee teaches, in ¶ [0089], data line Data, wherein the voltage of data line (Data) is a data write voltage (Vdata) during a data- writing period);
a second transistor (Lee Fig. 3, Transistor T3) including a second semiconductor layer including an oxide semiconductor (Lee ¶ [0074], T3 comprises the oxide semiconductor layer), wherein the second transistor connects the data line to the first transistor in response to a scan signal (Lee Fig. 3 and ¶ [0082], T3 is controlled by signal Sn, connects data line Data to the control terminal c2 of first transistor T1, and writes data voltage Vdata from the data line to node G during the data-writing period); and
a first capacitor including a first electrode and a second electrode (Lee, Fig. 3, first capacitor Cst with first electrode connected to the control terminal c2 of first transistor T1 and second electrode connected to terminal b2 of first transistor T1).
Lee is silent regarding
wherein the first electrode is disposed on the first semiconductor layer, and the second electrode is spaced apart from the first electrode.
However, Kim teaches wherein the first electrode is disposed on the first semiconductor layer, and the second electrode is spaced apart from the first electrode (Kim teaches, in Figs. 2-4 and ¶ [0077], a first capacitor corresponding to storage capacitor Cst, wherein the first electrode corresponds to capacitor electrode CE and the second electrode corresponds to second gate electrode GE2. Kim teaches, in Fig. 4, that second gate electrode GE2 is spaced apart from capacitor electrode CE).
Kim teaches a display-subpixel driving transistor and storage capacitor in the same filed as Lee and directed to the same goal of current stability and area reduction. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee’s silicon driving transistor T1 and storage capacitor using Kim’s stacked storage-capacitor structure to improve current output and stability while reducing subpixel circuit area (Kim, ¶ [0016]).
Lee is further silent regarding
the display panel including a display area and a non-display area outside the display area, wherein the display area includes a first display area and a second display area at least partially surrounded by the first display area; and
a component disposed below the display panel to correspond to the second display area.
However, Kim’474 teaches
the display panel including a display area and a non-display area outside the display area, wherein the display area includes a first display area and a second display area at least partially surrounded by the first display area (Kim’474 teaches, in Figs. 11, first display area DA1 and second display area DA2, and a peripheral area PA outside the display area. DA2 is surrounded by DA1; and
a component disposed below the display panel to correspond to the second display area (Kim’474 teaches, in ¶ [0050] and ¶ [0052], an optical element 500 provided below display panel 30 and overlapping second display area DA2, wherein optical element 500 may be a camera, a flash, a sensor, etc.).
It would have been further obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the under-display component arrangement of Kim’474 into the display apparatus of Lee and Kim in order to provide a wider/fuller display screen while accommodating an optical component, such as camera or sensor, below a transmissive second display area of the display panel. The modification applies a known under-display optical component arrangement to a known OLED display panel and pixel-circuit structure, yielding the predictable result of a display apparatus including first display area, a second display area at least partially surrounded by the first display area, and a component below the display panel corresponding to the second display area.
Re: Claim 13, Lee, Kim and Kim’474 disclose all the limitations of claim 12 on which this claim depends.
Kim further teaches
wherein the first transistor further includes a first gate electrode below the first semiconductor layer (Kim teaches, in Fig. 4, gate electrode GE1 that is below the active layer ACT, such that first gate electrode GE1 is a bottom gate electrode).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee’s silicon driving transistor T1 using Kim’s bottom-gate driving-transistor structure to improve current output and stability while reducing subpixel circuit area (Kim, ¶ [0016]).
Re: Claim 14, Lee, Kim and Kim’474 disclose all the limitations of claim 13 on which this claim depends.
Kim further teaches
further comprising: a sub-voltage line disposed on the second electrode (As explained for claim 12, CE is the claimed first electrode and GE2 is the claimed second electrode. Kim further teaches, in Fig. 2, first driving voltage line DVL1 supplying first driving voltage Vdd, where first driving voltage line DVL1 corresponds to the claimed sub-voltage line. Kim further teaches, in Fig. 4, that second gate electrode GE2 is disposed over the active layer ACT, capacitor electrode CE is disposed over second gate electrode GE2, and an interlayer insulating layer ILD is disposed over capacitor electrode CE, and first driving voltage line DVL1 is disposed over the ILD (see ¶ [0073]). Thus, first driving voltage line DVL1 is disposed on second gate electrode GE2).
and electrically connected to the first electrode (Kim teaches, in Fig. 2 and ¶ [0077], that a constant voltage, e.g., first driving voltage Vdd, is applied to capacitor electrode CE, and that the storage capacitor Cst is electrically connected between first node N1 and second node N2, to which driving voltage Vdd is supplied. To the extent Kim does not expressly disclose a direct contact between DVL1 and CE, it would have been obvious to electrically connect DVL1 to CE because Kim teaches that DVL1 supplies Vdd, and CE is the capacitor/gate electrode to which the constant voltage Vdd is applied. Providing a conductive contact or via from the Vdd line to the electrode receiving Vdd would have been a routine interconnection needed to implement Kim’s disclosed circuit).
Re: Claim 15, Lee, Kim and Kim’474 disclose all the limitations of claim 14 on which this claim depends.
Kim further teaches
wherein the sub-voltage line is electrically connected to a driving voltage line (Kim teaches, in Fig. 2, electrical current path between DVL1 and DVL2 through driving transistor DRT and light-emitting element ED during operation).
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20170186782 A1) in view of Kim (US 20220392984 A1) further in view Kim’474 (US 20200211474 A1) and further in view of Ma (US 20210208633 A1).
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Re: Claim 9, Lee, Kim and Kim’474 disclose all the limitations of claim 8 on which this claim depends.
Lee, Kim and Kim’474 are silent regarding
a plurality of first display elements disposed in the first display area; a plurality of second display elements disposed in the second display area; a plurality of second sub-pixel circuits electrically connected to the plurality of second display elements, respectively; and a plurality of connection lines electrically connecting the plurality of second display elements with the plurality of second sub-pixel circuits, respectively, wherein the plurality of second sub-pixel circuits are disposed between the first display area and the second display area or in the non-display area.
However, Ma teaches
a plurality of first display elements disposed in the first display area; a plurality of second display elements disposed in the second display area (Ma teaches, in Fig. 2(Annotated) above, first light emitting units EM1 in first display area AA1’, and second light-emitting units EM2 in second display area AA2’); a plurality of second sub-pixel circuits electrically connected to the plurality of second display elements (second pixel circuit PD2 is connected to EM2), respectively ; and a plurality of connection lines electrically connecting the plurality of second display elements with the plurality of second sub-pixel circuits, respectively (Ma, Fig. 2(Annotated), connection line RL connecting PD2 and EM2), wherein the plurality of second sub-pixel circuits are disposed between the first display area and the second display area or in the non-display area (Ma, Fig. 2(annotated), PD2 is disposed between AA1’ and AA2’).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to arrange the second sub-pixel circuits taught by Ma, while connecting the second display elements in the second display area to those second sub-pixel circuits by connecting lines, in order to further remove light-blocking pixel-circuit structures for the light transmitting second display area and thereby further increase light transmittance for the under-panel component.
Claim(s) 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20170186782 A1) in view of Kim (US 20220392984 A1) further in view of Kim’474 (US 20200211474 A1) and further in view of Sun (US 20060121310 A1).
Re: Claim 16, Lee, Kim and Kim’474 disclose all the limitations of claim 14 on which this claim depends.
Lee, Kim and Kim’474 are silent regarding
further comprising: a second capacitor including the first gate electrode and the first electrode; and a third capacitor including the second electrode and the sub-voltage line.
However, Sun teaches further comprising: a second capacitor including the first gate electrode and the first electrode; and a third capacitor including the second electrode and the sub-voltage line (Sun teaches, in Fig. 1, an OLED pixel having multiple vertically stacked storage capacitors 108 and 112 formed over the same area and connected in parallel. Sun further teaches, in ¶ [0046] and Fig. 11, including more than two capacitors may be formed over the same area (area A) of substrate 200. Thus, Sun teaches alternating stacked conductive layers connected to two common nodes to form the storage capacitors.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to apply Sun’s stacked parallel capacitor arrangement to Kim’s stacked conductors so that additional capacitors are formed between Kim’s common gate node N1 and common Vdd/constant voltage node N2. Specifically, it would have been obvious to form a second capacitor between GE1 and CE, because GE1 is tied to node N1 and CE is tied to node N2, and to form a third capacitor between GE2 and DVL1, because GE2 is tied to node N1 and DV1 is tied to node N2. The motivation would have been to increase storage capacitance without increasing the occupied pixel area, as taught by Sun in ¶ [0047]).
Re: Claim 17, Lee, Kim and Kim’474 disclose all the limitations of claim 13 on which this claim depends.
Lee, Kim and Kim’474 are silent regarding
further comprising: an emission control line which transmits an emission control signal;
a first initialization voltage line which transmits a first initialization voltage;
a second initialization voltage line which transmits a second initialization voltage;
a fifth transistor which connects a driving voltage line to a side of the first semiconductor layer in response to the emission control signal;
a sixth transistor which connects another side of the first semiconductor layer to an anode of the display element in response to the emission control signal; and
a seventh transistor which connects the second initialization voltage line to the anode of the display element in response to another scan signal.
However, Son teaches
further comprising: an emission control line which transmits an emission control signal (Son teaches, in Fig. 2 and ¶ [0057], emission control line EL configured to transmit an emission control signal En);
a first initialization voltage line which transmits a first initialization voltage (Son teaches, in Fig. 2 and ¶ [0058], one branch of initialization voltage line VIL connected to first initialization transistor T4 is configured to transmit first initialization voltage Vint to initialize the gate of driving transistor T1);
a second initialization voltage line which transmits a second initialization voltage (Son teaches, in Fig. 2 and ¶ [0058], second branch of initialization voltage line VIL connected to second initialization transistor T7 is configured to transmit second initialization voltage Vint to initialize the pixel electrode/anode of OLED);
a fifth transistor which connects a driving voltage line to a side of the first semiconductor layer in response to the emission control signal (Son teaches, in Fig. 2 and ¶¶ [0057] - [0059], operation control transistor T5 has an operation control gate electrode connected to emission control line EL, an operation control source area connected to driving voltage line PL, and an operation control drain area connected to a driving source area of driving transistor T1. Thus, Son teaches operation control transistor T5 connects driving voltage line PL to the driving source area of driving transistor T1 in response to emission control signal En on emission control line EL);
a sixth transistor which connects another side of the first semiconductor layer to an anode of the display element in response to the emission control signal (Son further teaches, in Fig. 2 and ¶ [0065], emission control transistor T6 having a emission control gate electrode connected to emission control line EL, an emission control source area of T6 connected to the driving drain area of driving transistor T1, and an emission control drain area of T6 electrically connected to the pixel electrode/ anode of OLED. Thus, Son teaches that emission control transistor T6 connects the driving drain area of driving transistor T1 to the pixel electrode/anode of OLED in response to emission control signal En on emission control line EL); and
a seventh transistor which connects the second initialization voltage line to the anode of the display element in response to another scan signal (Son teaches in Fig. 2 and related descriptions, second initialization transistor T7 has a gate electrode connected to next scan line SLn, a source area connected to second branch of initialization voltage line VIL, and a drain area connected to the pixel electrode/anode of OLED. Thus, Son teaches seventh transistor T7 which connects the second initialization voltage line VIL to the anode of the display element OLED in response to another scan signal SLn).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Son’s emission-control and initialization transistor arrangement into the display apparatus of Lee and Kim in order control an emission period of the OLED and initialize the OLED pixel electrode/anode, thereby improving display-pixel operation. The modification applies a known OLED pixel circuit emission/initialization arrangement of Lee’s known active-matrix OLED pixel circuit, yielding the predictable result of a display apparatus including an emission control line, initialization voltage line, and fifth, sixth and seventh transistors arranged as claimed.
Re: Claim 18, Lee, Kim, Kim’474 and Son disclose all the limitations of claim 17 on which this claim depends.
Son further teaches
wherein the fifth transistor includes a fifth semiconductor layer, the sixth transistor includes a sixth semiconductor layer, the seventh transistor includes a seventh semiconductor layer, and each of the fifth to seventh semiconductor layers includes the oxide semiconductor (Son teaches, in ¶ [0089], T5 includes an operation control semiconductor layer A5, T6 includes an emission control semiconductor layer A6 and T7 includes a second initialization semiconductor layer A7. Son further teaches, in ¶ [0079], at least one of the transistors T1, T2, T3, T4, T5, T6, and T7 may include a semiconductor layer including oxide).
Re: Claim 19, Lee, Kim, Kim’474 and Son disclose all the limitations of claim 18 on which this claim depends.
Son further teaches
further comprising:
a third transistor (Son, Fig. 2 and ¶ [0089], compensation transistor T3) including a third semiconductor layer (compensation semiconductor layer A3) having a side connected to the first gate electrode (compensation source area of the compensation transistor T3 is connected to first electrode CE1 of the storage capacitor Cap and the driving gate electrode of the driving transistor T1 via a node connection line 161) and another side connected to the sixth semiconductor layer (Son further teaches that emission control transistor T6 includes emission control semiconductor layer A6, and, in ¶ [0065], that T6/A6 is also connected to the driving drain area of T1. Thus, Son teaches that the third semiconductor layer A3 having one side connected to the first gate electrode and another side connected to the sixth semiconductor layer A6); and
a fourth transistor (Son Fig. 2, first initialization transistor T4) including a fourth semiconductor layer (first initialization semiconductor layer A4) having a side connected to the first gate electrode (one side of T4/A4 is connected to first electrode CE1 of the storage capacitor Cap and the driving gate electrode of the driving transistor T1 via a node connection line 161) and another side connected to the first initialization voltage line (another side of T4/A4 is connected to the first branch of initialization voltage line VIL),
wherein each of the third semiconductor layer and the fourth semiconductor layer includes the oxide semiconductor (Son further teaches, in ¶ [0090], A3 and A4 are semiconductor layer including oxide semiconductor).
Re: Claim 20, Lee, Kim, Kim’474 and Son disclose all the limitations of claim 19 on which this claim depends.
Kim’474 further teaches
wherein the third semiconductor layer, the fourth semiconductor layer, and the sixth semiconductor layer are integrally formed with each other as a single unitary and indivisible part (Kim’474 teaches, in ¶ [0110], the active pattern 130 may include channel regions 131c_1 and 131c_2 for third transistor T3_1 and T3_2, channel regions 131d_1 and 131d_2 for fourth transistor T4_1 and T4_2, and channel region 131f of sixth transistor T6. Kim’474 also teaches that active pattern 130 may include amorphous silicon, polysilicon, or an oxide semiconductor. Thus, the channel/semiconductor regions of the third, fourth, and sixth transistors are formed as respective portion of the same active pattern 130).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form the third, fourth, and sixth transistors in the modified display apparatus as respective portion of a common active pattern, as taught by Kim’474, rather than as separately patterned semiconductor islands in order to simplify patterning and alignment).
Conclusion
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/BIPANA ADHIKARI DAWADI/ Examiner, Art Unit 2898
/JESSICA S MANNO/ SPE, Art Unit 2898
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