Prosecution Insights
Last updated: July 17, 2026
Application No. 18/533,891

GATE-ALL-AROUND TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME

Non-Final OA §103
Filed
Dec 08, 2023
Priority
May 09, 2023 — CN 202310519529.3
Examiner
CLINTON, EVAN GARRETT
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Chinese Academy of Sciences
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
504 granted / 570 resolved
+20.4% vs TC avg
Moderate +5% lift
Without
With
+5.3%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
25 currently pending
Career history
589
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
90.4%
+50.4% vs TC avg
§102
5.4%
-34.6% vs TC avg
§112
3.9%
-36.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 570 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (U.S. Publication No. 2022/0254776) in view of Peng et al. (U.S. Publication No. 2016/0181245). Regarding claim 1, Cheng teaches a gate-all-around (GAA) transistor, comprising: a semiconductor substrate (Fig. 31 and 33, substrate 202, labeled in Fig. 31); an active structure (active structure 500) disposed on the semiconductor substrate, wherein the active structure comprises a source (240), a drain (also labeled 240), and a channel (channel 2080, labeled in Fig. 31) between the source and the drain (Fig. 33); a doped structure (doped structure 206) inlaid in the semiconductor substrate (Fig. 33), wherein primary carriers of the doped epitaxial structure are opposite in polarity to primary carriers of the source and the drain (paragraph [0015]), and the doped epitaxial structure is disposed beneath the channel and not beneath the source and the drain (Fig. 33); and a gate stack structure (gate stack 256, labeled in Fig. 31) surrounding the channel, wherein a portion of the gate stack structure beneath the channel is disposed between the doped epitaxial structure and the channel (Fig. 31 and 33). Cheng does not teach that the doped structure is epitaxial. However, Peng teaches that instead of the implantation method of Cheng, a doped epitaxial anti punch-through can be formed (Peng Fig. 5A-D, epitaxial APT 512). It would have been obvious to a person of skill in the art at the time of the effective filing date that the implanted APT layer of Cheng could have been replaced by a doped epitaxial APT layer because Peng teaches that this allows for more customization in the material of the APT layer, such as thickness and material (Peng paragraph [0052]). Regarding claim 2, Cheng in view of Peng teaches the GAA transistor according to claim 1, wherein a thickness of the doped epitaxial structure ranges from 10nm to 40nm (Peng paragraph [0052], 10nm). Regarding claim 3, Cheng in view of Peng teaches the GAA transistor according to claim 1, wherein a concentration of dopants in the doped epitaxial structure is greater than a concentration of dopants in a portion of the semiconductor substrate in contact with the source and a portion of the semiconductor substrate in contact with the drain (Cheng paragraph [0015] and Peng paragraph [0022]). Regarding claim 4, Cheng in view of Peng teaches the GAA transistor according to claim 1, wherein a concentration of dopants in the doped epitaxial structure ranges from 1x1018cm-3 to 1x1019cm-3 (Peng paragraph [0052]). Regarding claim 5, Cheng in view of Peng teaches the GAA transistor according to claim 1, wherein a material of a matrix of the doped epitaxial structure is identical to one or both of: a material of a matrix of the semiconductor substrate (Peng paragraph [0052], can be same or different material that substrate), and a material of the channel. Regarding claim 6, Cheng teaches a method for manufacturing a GAA transistor, comprising: providing a semiconductor substrate (Fig. 33, substrate 202); forming a doped structure (doped structure 206) inlaid in the semiconductor substrate (Fig. 31 and 33), wherein primary carriers of the doped epitaxial structure are opposite in polarity to primary carriers of the source and the drain (paragraph [0015]); forming an active structure (active structure 500) on the semiconductor substrate, wherein the active structure comprises a source (240), a drain (240), and a channel (2080) between the source and the drain, and the doped structure is disposed beneath the channel and not beneath the source and the drain (Fig. 33); and forming a gate stack structure (256) surrounding the channel, wherein a portion of the gate stack structure beneath the channel is disposed between the doped structure and the channel (Fig. 31 and 33). Cheng does not teach the doped structure is epitaxial. However, Peng teaches that instead of the implantation method of Cheng, a doped epitaxial anti punch-through can be formed (Peng Fig. 5A-D, epitaxial APT 512). It would have been obvious to a person of skill in the art at the time of the effective filing date that the implanted APT layer of Cheng could have been replaced by a doped epitaxial APT layer because Peng teaches that this allows for more customization in the material of the APT layer, such as thickness and material (Peng paragraph [0052]). Allowable Subject Matter Claims 1-8 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claims 7-8 and 12, the prior art, alone or in combination, fails to teach or suggest forming a doped epitaxial material which fills the groove fully. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Evan G Clinton whose telephone number is (571)270-0525. The examiner can normally be reached Monday-Friday at 8:30am to 5:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EVAN G CLINTON/Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Dec 08, 2023
Application Filed
May 18, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12682944
METHOD FOR MANUFACTURING SEMICONDUCTOR-ELEMENT-CONTAINING MEMORY DEVICE
2y 7m to grant Granted Jul 14, 2026
Patent 12666964
PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
2y 0m to grant Granted Jun 23, 2026
Patent 12660653
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
3y 5m to grant Granted Jun 16, 2026
Patent 12660654
INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF
3y 4m to grant Granted Jun 16, 2026
Patent 12653028
Packaged Semiconductor Device Including Liquid-Cooled Lid and Methods of Forming the Same
2y 2m to grant Granted Jun 09, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
94%
With Interview (+5.3%)
1y 11m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 570 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month