DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/11/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2 and 4-6, 8-12, 14-16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al (US 2019/0355812; hereinafter Li) in view of Walker (US 2017/0025437; hereinafter Walker).
Regarding claim 1, Fig 2H of Li discloses a semiconductor substrate comprising:
a silicon-on-insulator (SOI) substrate (104/114; Fig 2H; ¶ [0035]) comprising a device layer (104; Fig 2H; ¶ [0035]) and a buried oxide layer (114; Fig 2H; ¶ [0044]) being contiguous (Fig 2H) with the device layer (104; Fig 2H; ¶ [0035]);
at least one transistor (206; Fig 2H; ¶ [0037]) disposed on the device layer (104; Fig 2H; ¶ [0035]);
a dielectric layer (116; Fig 2H; ¶ [0045]) surrounding the at least one transistor (206; Fig 2H; ¶ [0037]);
an interconnect structure (130; Fig 2H; ¶ [0056]) disposed on the dielectric layer (116; Fig 2H; ¶ [0045]) and being electrically connected to a gate (206; Fig 2H; ¶ [0037]) of the at least one transistor;
a dielectric layer (106; Fig 2H; ¶ [0036]) comprising silicon nitride (¶ [0036]) being contiguous (Fig 2H) with the buried oxide layer (114; Fig 2H; ¶ [0044]);
a capping layer (102; Fig 2H; ¶ [0034]) being contiguous with the dielectric layer comprising silicon nitride (106; Fig 2H; ¶ [0036]); and
a conductive via (124/122; Fig 2H; ¶ [0051]) penetrating through the capping layer (102; Fig 2H; ¶ [0034]), the dielectric layer comprising silicon nitride (106; Fig 2H; ¶ [0036]), the buried oxide layer (114; Fig 2H; ¶ [0044]), the device layer (104; Fig 2H; ¶ [0035]) and the dielectric layer (116; Fig 2H; ¶ [0045]), wherein the conductive via (124/122; Fig 2H; ¶ [0051]) is electrically connected to the interconnect structure (130; Fig 2H; ¶ [0056]) and is further electrically connected (Fig 2H) to the at least one transistor through the interconnect structure.
However Li does not disclose a dielectric layer comprising silicon nitride is a charge trapping layer.
In the same field of endeavor, a charge trapping layer comprises a dielectric material such as silicon nitride (¶ [0056]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a dielectric layer comprising silicon nitride will function as charge trapping layer as it is well known and suitable material known in the art for forming charge trapping layer (¶ [0056]).
Regarding claim 2, Fig 2H of Li discloses the at least one transistor is a fully-depleted silicon-on-insulator metal-oxide semiconductor transistor (Fig 2H).
Regarding claim 4, Fig 2H of Li discloses the charge trapping layer has a thickness of 300 Angstroms. (¶ [0036])
However Li does not expressly disclose the charge trapping layer has a thickness of about 80-120 angstroms.
In the same field of endeavor, Walker discloses a charge trapping layer comprising silicon nitride can have thickness from 5 angstroms and 500 angstroms which overlaps the claimed range. Therefore it is obvious that a person in the ordinary skill in the art can vary the thickness of silicon nitride within the claimed range even though the Li teaches the specific range. (¶ [0056])
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that the thickness of charge trapping layer comprising silicon nitride is within the claimed range in order to form the charge trapping layer with desired thickness and that thickness of silicon nitride very well known in the art (¶ [0056])
However, the ordinary artisan would have recognized the material chosen, temperature and pressure at which charge trapping layer is grown to be a result effective variable affecting the thickness of the charge trapping layer. Thus, it would have been obvious to vary the growth parameters in order to achieve the thickness within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B
Regarding claim 5, Fig 2H of Li discloses the capping layer (102; Fig 2H; ¶ [0034]) comprises a silicon oxide layer (¶ [0034]).
However Li does not expressly disclose the capping layer comprises silicon nitride layer.
In the same field of endeavor, Walker discloses a dielectric layer can comprise silicon oxide or silicon nitride layer (¶ [0057]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that the capping layer can comprise silicon oxide or silicon nitride layer for the purpose of substituting art recognized equivalents known to be used for the same purpose (MPEP 2144.06).
Regarding claim 6, Fig 2H of Li discloses the conductive via (124/122; Fig 2H; ¶ [0051]) comprises copper (¶ [0052]).
Regarding claim 8, Fig 2H of Li discloses an insulating layer (142; Fig 2H; Bottom layer; ¶ [0057]) being contiguous with the capping layer (102; Fig 2H; ¶ [0034]);
a passivation layer (142; Top layer; Fig 2H; ¶ [0057]) being contiguous with the insulating layer (142; Fig 2H; Bottom layer; ¶ [0057]); and
a metal wiring layer (144a/144b; Fig 2H; ¶ [0057]) disposed in the insulating layer and the passivation layer.
Regarding claim 9, Fig 2H of Li discloses the insulating layer (142; Fig 2H; Bottom layer; ¶ [0057]) comprises a silicon oxide layer (¶ [0057]) and the passivation layer (142; Top layer; Fig 2H; ¶ [0057]) comprises a silicon nitride layer (¶ [0057]).
Regarding claim 10, Fig 2H of Li discloses the metal wiring layer (144a/144b; Fig 2H; ¶ [0057]) is an aluminum wiring layer (¶ [0057]).
Regarding claim 11, Fig 2H of Li discloses a method for forming a semiconductor substrate comprising:
providing a silicon-on-insulator (SOI) substrate (104/114; Fig 2H; ¶ [0035]) comprising a device layer (104; Fig 2H; ¶ [0035]) and a buried oxide layer (114; Fig 2H; ¶ [0044]) being contiguous (Fig 2H) with the device layer (104; Fig 2H; ¶ [0035]);
forming at least one transistor (206; Fig 2H; ¶ [0037]) disposed on the device layer (104; Fig 2H; ¶ [0035]);
forming a dielectric layer (116; Fig 2H; ¶ [0045]) surrounding the at least one transistor (206; Fig 2H; ¶ [0037]);
forming an interconnect structure (130; Fig 2H; ¶ [0056]) on the dielectric layer (116; Fig 2H; ¶ [0045]), wherein the interconnect structure is electrically connected to a gate (206; Fig 2H; ¶ [0037]) of the at least one transistor;
forming a dielectric layer (106; Fig 2H; ¶ [0036]) comprising silicon nitride (¶ [0036]) being contiguous (Fig 2H) with the buried oxide layer (114; Fig 2H; ¶ [0044]);
forming a capping layer (102; Fig 2H; ¶ [0034]) being contiguous with the dielectric layer comprising silicon nitride (106; Fig 2H; ¶ [0036]); and
forming a conductive via (124/122; Fig 2H; ¶ [0051]) penetrating through the capping layer (102; Fig 2H; ¶ [0034]), the dielectric layer comprising silicon nitride (106; Fig 2H; ¶ [0036]), the buried oxide layer (114; Fig 2H; ¶ [0044]), the device layer (104; Fig 2H; ¶ [0035]) and the dielectric layer (116; Fig 2H; ¶ [0045]), wherein the conductive via (124/122; Fig 2H; ¶ [0051]) is electrically connected to the interconnect structure (130; Fig 2H; ¶ [0056]) and is further electrically connected (Fig 2H) to the at least one transistor through the interconnect structure.
However Li does not disclose a dielectric layer comprising silicon nitride is a charge trapping layer.
In the same field of endeavor, a charge trapping layer comprises a dielectric material such as silicon nitride (¶ [0056]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a dielectric layer comprising silicon nitride will function as charge trapping layer as it is well known and suitable material known in the art for forming charge trapping layer (¶ [0056]).
Regarding claim 12, Fig 2H of Li discloses the at least one transistor is a fully-depleted silicon-on-insulator metal-oxide semiconductor transistor (Fig 2H).
Regarding claim 14, Fig 2H of Li discloses the charge trapping layer has a thickness of 300 Angstroms. (¶ [0036])
However Li does not expressly disclose the charge trapping layer has a thickness of about 80-120 angstroms.
In the same field of endeavor, Walker discloses a charge trapping layer comprising silicon nitride can have thickness from 5 angstroms and 500 angstroms which overlaps the claimed range. Therefore it is obvious that a person in the ordinary skill in the art can vary the thickness of silicon nitride within the claimed range even though the Li teaches the specific range. (¶ [0056])
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that the thickness of charge trapping layer comprising silicon nitride is within the claimed range in order to form the charge trapping layer with desired thickness and that thickness of silicon nitride very well known in the art (¶ [0056])
However, the ordinary artisan would have recognized the material chosen, temperature and pressure at which charge trapping layer is grown to be a result effective variable affecting the thickness of the charge trapping layer. Thus, it would have been obvious to vary the growth parameters in order to achieve the thickness within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B
Regarding claim 15, Fig 2H of Li discloses the capping layer (102; Fig 2H; ¶ [0034]) comprises a silicon oxide layer (¶ [0034]).
However Li does not expressly disclose the capping layer comprises silicon nitride layer.
In the same field of endeavor, Walker discloses a dielectric layer can comprise silicon oxide or silicon nitride layer (¶ [0057]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that the capping layer can comprise silicon oxide or silicon nitride layer for the purpose of substituting art recognized equivalents known to be used for the same purpose (MPEP 2144.06).
Regarding claim 16, Fig 2H of Li discloses the conductive via (124/122; Fig 2H; ¶ [0051]) comprises copper (¶ [0052]).
Regarding claim 18, Fig 2H of Li discloses forming an insulating layer (142; Fig 2H; Bottom layer; ¶ [0057]) being contiguous with the capping layer (102; Fig 2H; ¶ [0034]);
forming a passivation layer (142; Top layer; Fig 2H; ¶ [0057]) being contiguous with the insulating layer (142; Fig 2H; Bottom layer; ¶ [0057]); and
forming a metal wiring layer (144a/144b; Fig 2H; ¶ [0057]) disposed in the insulating layer and the passivation layer.
Regarding claim 19, Fig 2H of Li discloses the insulating layer (142; Fig 2H; Bottom layer; ¶ [0057]) comprises a silicon oxide layer (¶ [0057]) and the passivation layer (142; Top layer; Fig 2H; ¶ [0057]) comprises a silicon nitride layer (¶ [0057]).
Regarding claim 20, Fig 2H of Li discloses the metal wiring layer (144a/144b; Fig 2H; ¶ [0057]) is an aluminum wiring layer (¶ [0057]).
Claim(s) 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al (US 2019/0355812; hereinafter Li) in view of Walker (US 2017/0025437; hereinafter Walker) and further in view of Lin et al (US 2014/0286105; hereinafter Lin).
Regarding claim 3, Li in view of Walker discloses the charge trapping layer comprises a dielectric material (106; Fig 2H; ¶ [0036]) such as silicon nitride (¶ [0036]).
In the same field of endeavor, Lin discloses charge trapping layer may be composed of a dielectric material such as silicon nitride or phosphosilicate glass (PSG) (¶ [0035]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a charge trapping layer comprises a silicon nitride or phosphosilicate glass for the purpose of substituting art recognized equivalents known to be used for the same purpose (MPEP 2144.06).
Regarding claim 13, Li in view of Walker discloses the charge trapping layer comprises a dielectric material (106; Fig 2H; ¶ [0036]) such as silicon nitride (¶ [0036]).
In the same field of endeavor, Lin discloses charge trapping layer may be composed of a dielectric material such as silicon nitride or phosphosilicate glass (PSG) (¶ [0035]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a charge trapping layer comprises a silicon nitride or phosphosilicate glass for the purpose of substituting art recognized equivalents known to be used for the same purpose (MPEP 2144.06).
Claim(s) 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al (US 2019/0355812; hereinafter Li) in view of Walker (US 2017/0025437; hereinafter Walker) and further in view of Hsieh (US 2022/0336390; hereinafter Hsieh).
Regarding claim 7, Fig 2H of Li discloses the dielectric layer (116; Fig 2H; ¶ [0045]) is an interlevel dielectric layer and is made of silicon oxide (¶ [0045]).
However Li does not expressly disclose the dielectric layer comprises an undoped silicate glass (USG) layer.
In the same field of endeavor, Hsieh discloses an interlayer dielectric can comprise silicon oxide or undoped silicate glass (¶ [0046]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that an interlayer dielectric layer comprises a silicon nitride or undoped silicate glass for the purpose of substituting art recognized equivalents known to be used for the same purpose (MPEP 2144.06).
Regarding claim 17, Fig 2H of Li discloses the dielectric layer (116; Fig 2H; ¶ [0045]) is an interlevel dielectric layer and is made of silicon oxide (¶ [0045]).
However Li does not expressly disclose the dielectric layer comprises an undoped silicate glass (USG) layer.
In the same field of endeavor, Hsieh discloses an interlayer dielectric can comprise silicon oxide or undoped silicate glass (¶ [0046]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that an interlayer dielectric layer comprises a silicon nitride or undoped silicate glass for the purpose of substituting art recognized equivalents known to be used for the same purpose (MPEP 2144.06).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Smeys et al (US 2011/0260248)
Hou et al (US 2022/0238800)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RATISHA MEHTA whose telephone number is (571)270-7473. The examiner can normally be reached Monday-Friday: 9:00am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos Feliciano can be reached at 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RATISHA MEHTA/Primary Examiner, Art Unit 2817