Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I in the reply filed on 03/12/26 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang, US 2020/0161450 in view of Usami, US 2015/0372102 and further in view of Welmer et al., US 2020/0027725.
Huang shows the invention substantially as claimed including a semiconductor device, comprising:
A substrate 210;
A gate electrode 224 disposed on the substrate;
A source region 240 and a drain region 242 disposed in the substrate and on opposite sides of the gate electrode;
An isolating layer 270 disposed over the substrate and the gate electrode;
A plurality of metal contacts 320 disposed on the gate electrode, the source region, and the drain region;
A contact liner 330 disposed in the isolating layer;
A plurality of conductive plugs 350 disposed in the isolating layer and surrounded by the contact liner, and electrically coupled to the metal contacts (see figs. 2-16 and paragraphs 0033-0048).
Huang does not expressly disclose a filling layer disposed in the isolating layer and wherein the filling layer comprises boron carbonitride. Usami discloses forming a filling layer DL1 in the isolating layer DL2 (see fig. 32 and paragraphs 0114-0120). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Hung so as to comprise the filling layer and process of Usami because this is shown as a way in which to eliminate any potential air gaps in the layer that will degrade device performance. Additionally, Welmer et al. discloses the use of boron carbonitride as a filling layer 141 in order to seal pores and air gaps (see, for example, abstract and paragraphs 0021 and 0095-0102). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Hung modified by Usami so as use boron carbonitride as the filling layer because Welmer et al. shows boron carbonitride to be a suitable filling material.
Concerning dependent claim 2, note that in the device of Huang modified by Usami and Welmer et al. discloses wherein a plurality of air gaps are disposed in the filling layer and enclosed by the filling layer (see, for example, fig. 12 of Usami and its description).
With respect to dependent claim 3, note that Huang discloses wherein the semiconductor device further includes a barrier layer 335 disposed between the plurality of conductive plugs 350 and the contact liner 330 (see fig. 17).
Regarding dependent claim 4, note that Huang discloses wherein the isolating layer includes an underlying dielectric layer 270 and an overlying dielectric layer 280, wherein the underlying dielectric layer is disposed on the substrate and surrounds the gate electrode, and the overlying dielectric layer is disposed over the underlying dielectric layer and the gate electrode (see fig. 5).
Concerning dependent claim 5, note that the device of Huang modified by Usami and Welmer et al. discloses wherein a top portion of the air gap is located at a vertical level lower than a top surface of the overlying dielectric layer (see, for example, fig. 12 of Usami).
With respect to dependent claim 6, note that Huang discloses wherein a top surface of the plurality of metal contacts in the gate electrode is coplanar with an upper surface of the underlying dielectric layer, and top surfaces of the other metal contacts in the source region and the drain region are coplanar with a front surface of the substrate (see, for example, fig. 17).
As to dependent claim 7, note that Huang discloses wherein the semiconductor device further includes a gate dielectric 222 and a gate spacer 230, wherein the gate dielectric is disposed between the substrate and the gate electrode, and the gate spacer is disposed on sidewalls of the gate electrode and the gate dielectric (see fig. 3).
Concerning dependent claim 8, note that Huang discloses wherein the semiconductor device further includes a plurality of isolating regions 214 disposed in the substrate to define and electrically isolate one or more active areas comprising the gate electrode, the source region, and the drain region (see paragraph 0033).
With respect to dependent claim 9, note that in Huang the insulating regions 214 are shallow trench isolation structures (again, see paragraph 0033).
Regarding dependent claim 10, note that neither Huang, Usami and Welmer et al. do not expressly disclose the particular ratio of width of the filling layer to the width of air gaps. However, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to determine through routine experimentation the optimum width of the filling layer to the width of air gaps depending upon a variety of factors including, for example, the desired capacitance of the filling layer and such limitation would not lend patentability to the instant application absent a showing of unexpected results.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571)272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00.
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/RICHARD A BOOTH/ Primary Examiner, Art Unit 2812
March 29, 2026