DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is response to Application 18/535,546 filed on 12/11/2023. Claims 1-20 are pending in the office action.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1-7, 9-12, and 14-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,100,273. Although the claims at issue are not identical, they are not patentably distinct from each other because both claimed inventions are disclosed substantially similar subject matter.
There are different claim limitations arrangement between independent claims and dependent claim, but the subject matter is similar.
It would have bee obvious to one of ordinary skill in the art at the time of the effective filling date of claimed invention use either one of claimed inventions would yield the similar result without undue experiment (see the follow analysis).
As per claim 1: A system for manufacturing an integrated circuit, the system comprises (‘273, claim 1, col. 47, ll. 44-45):
a non-transitory computer readable medium configured to store executable instructions (‘273, claim 1, col. 47, ll. 46-47); and
a processor coupled to the non-transitory computer readable medium, wherein the processor is configured to execute the instructions for (‘273, claim 1, col. 47, ll. 48-50):
generating a layout design of the integrated circuit, the layout design having a set of design rules, wherein the generating of the layout design (‘273, claim 1, col. 47, ll. 51-53 and claim 8, col. 49, ll. 59-61) comprises:
generating a set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, each of the layout patterns of the set of gate layout patterns being separated from an adjacent layout pattern of the set of gate layout patterns in a first direction, the set of gate layout patterns being on a first layout level, and extending in a second direction different from the first direction (‘273, claim 8, col. 50, ll. 1-9, at second layout level);
generating a cut feature layout pattern corresponding to a cut region of a first gate of the set of gate structures of the integrated circuit, the cut feature layout pattern extending in the first direction, and overlapping at least a first gate layout pattern of the set of gate layout patterns (‘273claim 8, col. 50, ll. 10-20);
generating a first conductive feature layout pattern corresponding to fabricating a first conductive structure of the integrated circuit, the first conductive feature layout pattern extending in the first direction, and being on a second layout level different from the first layout level (‘273, claim 10, col. 50, ll.35-41, third layout level and claim 12, col. 51, ll. 10-15); and
generating a first via layout pattern corresponding to a first via, the first via layout pattern being between the first conductive feature layout pattern and the first gate layout pattern of the set of gate layout patterns, and the first via layout pattern being located where the first conductive feature layout pattern overlaps the first gate layout pattern of the set of gate layout patterns (‘273, claim 9, col. 50, ll. 26-32).
As per claim 2: The system of claim 1, wherein the processor configured to execute the instructions for the generating of the layout design further comprises:
generating a first active region layout pattern corresponding to fabricating a first active region, and the first active region layout pattern extending in the first direction, and being on a third layout level different from the first layout level and the second layout level (‘273, claim 8, col. 49, ll. 62-67, (first layout level), set of active region layout pattern includes first active regions);
generating a second active region layout pattern corresponding to fabricating a second active region, the second active region layout pattern being on the third layout level, extending in the first direction and being separated from the first active region layout pattern in the second direction by a first distance (S1), the set of design rules of the layout design including the first distance (‘273, claim 8, col. 49, ll. 62-67, , set of active region layout pattern includes second active regions);
generating a first contact layout pattern corresponding to fabricating a first contact, the first contact layout pattern being on the first layout level, extending in the second direction and overlapping the first active region layout pattern and the second active region layout pattern (‘273, claim 13, col. 51, ll. 37-42); and
generating a second contact layout pattern corresponding to fabricating a second contact, the second contact layout pattern being on the first layout level, extending in the second direction, overlapping the first active region layout pattern and the second active region layout pattern, and being separated from the first contact layout pattern in the first direction (‘273, claim 13, col. 51, ll. 43-49).
As per claim 3: The system of claim 2, wherein the processor configured to execute the instructions for the generating of the layout design, the set of design rules of the layout design further including:
a second distance between the cut feature layout pattern and the first active region layout pattern or the second active region layout pattern in the second direction, and being expressed by: S2 ≥ 0.2 * S1 (‘273, claim 3, col. 49, ll. 39-48).
As per claim 4: The system of claim 3, wherein the processor configured to execute the instructions for the generating of the layout design, the set of design rules of the layout design further including:
a third distance between the first via layout pattern and the cut feature layout pattern in the second direction, and being expressed by: S3 ≥ 0.3 * S1 (‘273, claim 4, col. 49, ll. 49-57).
As per claim 5: The system of claim 2, wherein the processor configured to execute the instructions for the generating of the layout design further comprises:
generating a second conductive feature layout pattern corresponding to fabricating a second conductive structure of the integrated circuit, the second conductive feature layout pattern being on the second layout level, extending in the first direction, being over the first active region layout pattern, overlapping a second gate layout pattern of the set of gate layout patterns, and being separated from the first conductive feature layout pattern in the first direction (‘273, claim 5, col. 48, ll. 62-67, claim 10, col. 50, ll.35-41, third layout level and claim 12, col. 51, ll. 16-25); and
generating a second via layout pattern corresponding to a second via, the second via layout pattern being between the second conductive feature layout pattern and the second gate layout pattern of the set of gate layout patterns, and the second via layout pattern being located where the second conductive feature layout pattern overlaps the second gate layout pattern of the set of gate layout patterns; wherein the second gate layout pattern is separated from the first gate layout pattern by a first poly pitch (P1) in the first direction (‘273, claim 5, col. 49, ll. 1-7; claim 12, col. 51, ll. 16-25); and
the second via layout pattern is separated from the first via layout pattern by a second distance in the first direction, and is expressed by: 1.1 * P1 ≥ DVG1 ≥ 0.9 * P1, wherein the set of design rules of the layout design further includes the first poly pitch and the second distance (‘273, claim 5, col. 49, ll. 11-17).
As per claim 6: The system of claim 2, wherein the processor configured to execute the instructions for the generating of the layout design further comprises:
generating a second conductive feature layout pattern corresponding to fabricating a second conductive structure of the integrated circuit, the second conductive feature layout pattern being on the second layout level, the second conductive feature layout pattern extending in the first direction, being over the second active region layout pattern, overlapping the first gate layout pattern of the set of gate layout patterns, and being separated from the first conductive feature layout pattern in the second direction (‘273, claim 6, col. 49, ll. 21-27, claim 12, col. 51, ll. 16-25); and
generating a second via layout pattern corresponding to a second via, the second via layout pattern being between the second conductive feature layout pattern and the first gate layout pattern of the set of gate layout patterns, and the second via layout pattern being located where the second conductive feature layout pattern overlaps the first gate layout pattern of the set of gate layout patterns (‘273, claim 6, col. 49, ll. 28-34, claim 11, col. 50, ll. 59-64, and claim 13, col. 51, ll. 43-48);
wherein the second via layout pattern is separated from the first via layout pattern by a second distance in the second direction, and is expressed by: 1.5 * S1 ≥ DVG2 ≥ 0.8 * S1 wherein the set of design rules of the layout design further includes the second distance (‘273, claim 6, col. 49, ll. 35-41).
As per claim 7: the system of claim 2, wherein the processor configured to execute the instructions for the generating of the layout design further comprises:
generating a second conductive feature layout pattern corresponding to fabricating a second conductive structure of the integrated circuit, the second conductive feature layout pattern being on the second layout level, the second conductive feature layout pattern extending in the first direction, and being separated from the first conductive feature layout pattern in the second direction (‘273, claim 6, col. 49, ll. 21-27, claim 12, col. 51, ll. 16-25); and
generating a second via layout pattern corresponding to a second via, the second via layout pattern being between the second conductive feature layout pattern and the first contact layout pattern or the second contact layout pattern, the second via layout pattern being located where the second conductive feature layout pattern overlaps the first contact layout pattern or the second contact layout pattern (‘273, claim 6, col. 49, ll. 28-34, claim 11, col. 50, ll. 59-64, and claim 13, col. 51, ll. 43-48).
Claim 8 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,100,273 in view of claims 1-20 of U.S. Pat. 11,842,137.
As per claim 8: ‘273 does not claim “generating a set of fin layout patterns corresponding to fabricating a set of fins of the first active region or the second active region, the set of fin patterns extending in the first direction, each fin pattern of the set of fin patterns being separated from an adjacent fin pattern of the set of fin patterns in the second direction by a pitch (P2), and P2 is related to S1 by the following expression: S1 ≤ 2.5 * P2”. However, its specification, col. 45, ll. 35-40, a set of fins of the first active region or the second active region, the set of fin patterns extending in the first direction, each fin pattern of the set of fin patterns being separated from an adjacent fin pattern of the set of fin patterns in the second direction by a pitch (P2), and P2 is related to S1 by the following expression: S1 ≤ 2.5 * P2”
‘137 claim “generating a set of fin layout patterns corresponding to fabricating a set of fins of the first active region or the second active region, the set of fin patterns extending in the first direction, each fin pattern of the set of fin patterns being separated from an adjacent fin pattern of the set of fin patterns in the second direction by a pitch (P2), and P2 is related to S1 by the following expression: S1 ≤ 2.5 * P2” (‘137, claim 3, col. 46, ll. 12-19).
It would have been obvious to one of ordinary skill the art at the time of the effective filling date of claimed invention to combine U.S. Pat. 137 and ‘273 to claim the set of fins that is similar to claim 8 of the current claimed invention without undue experiment.
As per claim 9-20 are similar rejected as above analysis.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 10,503,863 in view of claims 1-20 of U.S. Pat. 11,842,137.
There are different limitations arrangement recited in the current claimed invention compare to the prior arts U.S. Pat. ‘863 and ‘137.
However, the combination of the U.S. Pat. ‘863 and ‘137 are address all the feature and limitations of claims 1-20 current claimed invention and yield the similar result.
It would have been obvious to one of ordinary skill the art at the time of the effective filling date of claimed invention to combine U.S. Pat. 137 and ‘273 would achieve similar result without undue experiment.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 10,503,863 in view of claims 1-20 of U.S. Pat. 11,842,137.
There are different limitations arrangement recited in the current claimed invention compare to the prior arts U.S. Pat. ‘863 and ‘137.
However, the combination of the U.S. Pat. ‘863 and ‘137 are address all the feature and limitations of claims 1-20 current claimed invention and yield the similar result.
It would have been obvious to one of ordinary skill the art at the time of the effective filling date of claimed invention to combine U.S. Pat. 137 and ‘273 would achieve similar result without undue experiment.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 10,503,863 in view of claims 1-20 of U.S. Pat. 11,842,137.
There are different limitations arrangement recited in the current claimed invention compare to the prior arts U.S. Pat. ‘863 and ‘137.
However, the combination of the U.S. Pat. ‘863 and ‘137 are address all the feature and limitations of claims 1-20 current claimed invention and yield the similar result.
It would have been obvious to one of ordinary skill the art at the time of the effective filling date of claimed invention to combine U.S. Pat. ‘137 and ‘863 would achieve similar result without undue experiment.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 10,489,548 in view of claims 1-20 of U.S. Pat. 11,842,137.
There are different limitations arrangement recited in the current claimed invention compare to the prior arts U.S. Pat. ‘548 and ‘137.
However, the combination of the U.S. Pat. ‘548 and ‘137 are address all the feature and limitations of claims 1-20 current claimed invention and yield the similar result.
It would have been obvious to one of ordinary skill the art at the time of the effective filling date of claimed invention to combine U.S. Pat. 137 and ‘548 would achieve similar result without undue experiment.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,062,075 in view of claims 1-20 of U.S. Pat. 11,842,137.
There are different limitations arrangement recited in the current claimed invention compare to the prior arts U.S. Pat. ‘075 and ‘137.
However, the combination of the U.S. Pat. ‘075 and ‘137 are address all the feature and limitations of claims 1-20 current claimed invention and yield the similar result.
It would have been obvious to one of ordinary skill the art at the time of the effective filling date of claimed invention to combine U.S. Pat. 137 and ‘075 would achieve similar result without undue experiment.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,138,361 in view of claims 1-20 of U.S. Pat. 11,842,137.
There are different limitations arrangement recited in the current claimed invention compare to the prior arts U.S. Pat. ‘361 and ‘137.
However, the combination of the U.S. Pat. ‘361 and ‘137 are address all the feature and limitations of claims 1-20 current claimed invention and yield the similar result.
It would have been obvious to one of ordinary skill the art at the time of the effective filling date of claimed invention to combine U.S. Pat. 137 and ‘361 would achieve similar result without undue experiment.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 7, 8-12, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al., (U.S. Pat. 9,336,348).
With respect to claims 1-2, 7, 8-12, and 19-20: Hsieh teaches a method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design; and generating a set of layout patterns overlapping the identified one or more areas (‘348, the abstract). The integrated circuit layout includes set of gate layout pattern (‘348, fig. 1A-1C, gates 121, 123, 125, 127, and 129) and a gate structure cutting layout pattern (‘348, fig. 1A-1B, 166), a plurality (included first and second) of conductive feature layout patterns (‘348, fig. 1A-1C, 132, 134, 136, 142, 144, and 146), a plurality of via layout pattern (‘348, fig. 1A-1B, via 150), a plurality of contact layout patterns (fig. 1A-1B, shown connect between power/ground 162/164 and conductive patterns 132, 134, 142, and 144), and plurality of active regions layout pattern (‘348, fig. 1A-1B, 102 and 104), and plurality of fins structure layout pattern (‘348, fig. 1B-1C, 106 and 108).
The gate, conductor, via, conductor, and fin patterns are arranged in different direction (‘348, fig. 1A-1C) or are arranged in different level or layers (‘348, fig. 4A-5B). However, Hsieh’s the directions and level/layers arrangement may be not consist with the current claimed invention.
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of claimed invention would able to modify Hsieh’s the features layout pattern in the directions and level/layers arrangement consist to the current claimed invention claim language without undue experiment. (see In reJapikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950), rearrangement the parts).
Allowable Subject Matter
Claims 3-6, 8, and 13-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record does not teach the space, pitches, and distance as recited in claims 3-6, 8, and13-18.
Conclusion
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NGHIA M. DOAN
Primary Examiner
Art Unit 2851
/NGHIA M DOAN/Primary Examiner, Art Unit 2851
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