Attorney’s Docket Number: 0941-5058PUS1
Filing Date: 12/11/2023
Claimed Foreign Priority Date: none
Applicant(s): Tzou et al.
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the Amendment filed 07/20/2026.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The Amendment filed on 07/20/2026, responding to the Office action mailed on 05/07/2026, has been entered. The present Office action is made with all the suggested amendments being fully considered. Applicant cancelled claim 6. Accordingly, pending in this application are claims 1-5 and 7-20, with Claims 9-11 and 15-20 standing withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim.
Response to Amendment
Applicant’s amendments to the Claims have overcome the respective claim rejections under 35 U.S.C. 112, 35 U.S.C. 102, and 35 U.S.C. 103, as previously formulated in the Non-Final Office action mailed on 05/07/2026. Accordingly, all previous claim rejections are hereby withdrawn. However, Applicant’s amendments have raised new issues, and new grounds for rejection are presented below, as necessitated by Applicant’s amendments to the claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 8, and 12-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mori et al. (US2023/0170410).
Regarding Claim 1, Mori (see, e.g., Figs. 2, 6, and 8) shows all aspects of the instant invention, including a semiconductor device, comprising:
- a substrate (e.g., substrate region 10)
- an epitaxial layer disposed on the substrate, wherein the epitaxial layer has a first conductivity type (e.g., n-type epitaxial semiconductor region 11)
- a pair of well regions disposed in the epitaxial layer, wherein the pair of well regions has a second conductivity type that is different from the first conductivity type (e.g., p-type body regions 23)
- a pair of doping regions disposed in the pair of well regions, wherein the pair of doping regions has the first conductivity type (e.g., n-type source regions 24)
- a pair of first conductive structures (e.g., pair of structures comprising 41,110) disposed on sides of the pair of well regions, respectively, wherein each of the first conductive structures comprises a first conductive layer (e.g., electrode 44) and a first dielectric layer (e.g., insulating film 110) covering a top surface of the first conductive layer (see, e.g., Fig. 8)
- a second conductive structure (e.g., structure comprising 31,91) disposed on the pair of well regions.
Regarding Claim 2, Mori (see, e.g., Fig. 8) shows a pair of shielding layers (e.g., p-type regions 71) disposed under the pair of first conductive structures, respectively, wherein the pair of shielding layers has the second conductivity type.
Regarding Claim 3, Mori (see, e.g., Fig. 8) shows a shielding layer (e.g., p-type regions 71) disposed in the epitaxial layer, wherein the shielding layer is spaced apart from the second conductive structure by the epitaxial layer, wherein the shielding layer has the second conductivity type.
Regarding Claim 4, Mori (see, e.g., Fig. 8) shows that the second conductive structure comprises a second conductive layer (e.g., electrode 34) and a second dielectric layer (e.g., insulating film 33) surrounding the second conductive layer.
Regarding Claim 8, Mori (see, e.g., Fig. 8) shows that the pair of well regions (e.g., 23) is disposed between the pair of first conductive structures.
Regarding Claim 12, Mori (see, e.g., Figs. 2 and 8) shows an upper electrode layer (e.g., electrode 131) and a lower electrode layer (e.g., electrode 170) respectively disposed on the epitaxial layer and under the substrate.
Regarding Claim 13, Mori (see, e.g., Figs. 2, 6, and 8) shows all aspects of the instant invention, including a semiconductor device, comprising:
- a substrate (e.g., substrate region 10)
- an epitaxial layer disposed on the substrate, wherein the epitaxial layer has a first conductivity type (e.g., n-type epitaxial semiconductor region 11)
- at least one structural unit (see, e.g., Fig. 8), wherein each of the structural units comprises:
a pair of first conductive structures (e.g., pair of structures comprising 41,110) disposed on an outermost side of the structural unit, wherein each of the first conductive structures comprises a first conductive layer (e.g., electrode 44) and a first dielectric layer (e.g., insulating film 110) covering a top surface of the first conductive layer
a second conductive structure (e.g., structure comprising 31,91) disposed on the epitaxial layer
a pair of well regions disposed between the pair of first conductive structures, wherein the pair of well regions has a second conductivity type that is different from the first conductivity type (e.g., p-type body regions 23)
a pair of doping regions disposed in the pair of well regions, wherein the pair of doping regions has the first conductivity type (e.g., n-type source regions 24)
- wherein each of the structural units is symmetrical to a center of the second conductive structure.
Regarding Claim 14, Mori (see, e.g., Fig. 8) shows that the structural unit further comprises at least two shielding layers (e.g., any two p-type regions 71 associated with corresponding 41), wherein in a top view, the shielding layers are connected to each other (e.g., 71 are electrically connected at least through continuous p-doped regions).
Claims 1, 3-4, 8, and 12-13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yasutake et al. (US2025/0107142).
Regarding Claim 1, Yasutake (see, e.g., Figs. 2-4 and 9-10) shows all aspects of the instant invention, including a semiconductor device, comprising:
- a substrate (e.g., drain region 28)
- an epitaxial layer disposed on the substrate, wherein the epitaxial layer has a first conductivity type (e.g., n-type epi drift region 21)
- a pair of well regions disposed in the epitaxial layer, wherein the pair of well regions has a second conductivity type that is different from the first conductivity type (e.g., p-type base regions 22)
- a pair of doping regions disposed in the pair of well regions, wherein the pair of doping regions has the first conductivity type (e.g., n-type source regions 23)
- a pair of first conductive structures (e.g., structure comprising 14,32,51) disposed on sides of the pair of well regions, respectively, wherein each of the first conductive structures comprises a first conductive layer (e.g., FP electrode 14) and a first dielectric layer (e.g., insulating layer 32,51) covering a top surface of the first conductive layer (see, e.g., Fig. 8)
- a second conductive structure (e.g., structure comprising 13,31) disposed on the pair of well regions.
Regarding Claim 3, Yasutake (see, e.g., Fig. 10) shows a shielding layer (e.g., p-type region 24) disposed in the epitaxial layer, wherein the shielding layer is spaced apart from the second conductive structure by the epitaxial layer, wherein the shielding layer has the second conductivity type.
Regarding Claim 4, Yasutake (see, e.g., Figs. 4 and 10) shows that the second conductive structure comprises a second conductive layer (e.g., electrode 13) and a second dielectric layer (e.g., insulating part 31) surrounding the second conductive layer.
Regarding Claim 8, Yasutake (see, e.g., Figs. 4 and 10) shows that the pair of well regions (e.g., 22) is disposed between the pair of first conductive structures.
Regarding Claim 12, Yasutake (see, e.g., Figs. 4 and 10) shows an upper electrode layer (e.g., source electrode 12) and a lower electrode layer (e.g., drain electrode 11) respectively disposed on the epitaxial layer and under the substrate.
Regarding Claim 13, Yasutake (see, e.g., Figs. 2-4 and 9-10) shows all aspects of the instant invention, including a semiconductor device, comprising:
- a substrate (e.g., substrate region 10)
- an epitaxial layer disposed on the substrate, wherein the epitaxial layer has a first conductivity type (e.g., n-type epitaxial semiconductor region 11)
- at least one structural unit (see, e.g., Fig. 8), wherein each of the structural units comprises:
a pair of first conductive structures (e.g., pair of structures comprising 41,110) disposed on an outermost side of the structural unit, wherein each of the first conductive structures comprises a first conductive layer (e.g., electrode 44) and a first dielectric layer (e.g., insulating film 110) covering a top surface of the first conductive layer
a second conductive structure (e.g., structure comprising 31,91) disposed on the epitaxial layer
a pair of well regions disposed between the pair of first conductive structures, wherein the pair of well regions has a second conductivity type that is different from the first conductivity type (e.g., p-type body regions 23)
a pair of doping regions disposed in the pair of well regions, wherein the pair of doping regions has the first conductivity type (e.g., n-type source regions 24)
- wherein each of the structural units is symmetrical to a center of the second conductive structure.
Claims 1-3, 8, and 13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tawara et al. (US2024/0363692).
Regarding Claim 1, Tawara (see, e.g., Fig. 1) shows all aspects of the instant invention, including a semiconductor device, comprising:
- a substrate (e.g., substrate 31)
- an epitaxial layer disposed on the substrate, wherein the epitaxial layer has a first conductivity type (e.g., n-type epi drift layer 32,33)
- a pair of well regions disposed in the epitaxial layer, wherein the pair of well regions has a second conductivity type that is different from the first conductivity type (e.g., p-type base regions 4)
- a pair of doping regions disposed in the pair of well regions, wherein the pair of doping regions has the first conductivity type (e.g., n-type source regions 5)
- a pair of first conductive structures (e.g., structure comprising 8,9,12) disposed on sides of the pair of well regions, respectively, wherein each of the first conductive structures comprises a first conductive layer (e.g., electrode 9) and a first dielectric layer (e.g., insulating films 8,12) covering a top surface of the first conductive layer
- a second conductive structure (e.g., electrode 14) disposed on the pair of well regions.
Regarding Claim 2, Tawara (see, e.g., Fig. 1) shows a pair of shielding layers (e.g., p-type regions 11a) disposed under the pair of first conductive structures, respectively, wherein the pair of shielding layers has the second conductivity type.
Regarding Claim 3, Tawara (see, e.g., Fig. 1) shows a shielding layer (e.g., p-type region 11a) disposed in the epitaxial layer, wherein the shielding layer is spaced apart from the second conductive structure by the epitaxial layer, wherein the shielding layer has the second conductivity type.
Regarding Claim 8, Tawara (see, e.g., Fig. 1) shows that the pair of well regions (e.g., 4) is disposed between the pair of first conductive structures.
Regarding Claim 13, Tawara (see, e.g., Fig. 1) shows all aspects of the instant invention, including a semiconductor device, comprising:
- a substrate (e.g., substrate 31)
- an epitaxial layer disposed on the substrate, wherein the epitaxial layer has a first conductivity type (e.g., n-type epi drift layer 32,33)
- at least one structural unit (see, e.g., Fig. 1), wherein each of the structural units comprises:
a pair of first conductive structures (e.g., structure comprising 8,9,12) disposed on an outermost side of the structural unit, wherein each of the first conductive structures comprises a first conductive layer (e.g., electrode 9) and a first dielectric layer (e.g., insulating films 8,12) covering a top surface of the first conductive layer
a second conductive structure (e.g., electrode 14) disposed on the epitaxial layer
a pair of well regions disposed between the pair of first conductive structures, wherein the pair of well regions has a second conductivity type that is different from the first conductivity type (e.g., p-type body regions 4)
a pair of doping regions disposed in the pair of well regions, wherein the pair of doping regions has the first conductivity type (e.g., n-type source regions 5)
- wherein each of the structural units is symmetrical to a center of the second conductive structure.
Claims 1, 4-5, 7-8, and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Challa et al. (US2006/0214222).
Regarding Claim 1, Challa (see, e.g., Fig. 3B, with reference to Figs. 1-2 for unlabeled analogous features) shows all aspects of the instant invention, including a semiconductor device (e.g., MOSFET 300B), comprising:
- a substrate (e.g., substrate region 214)
- an epitaxial layer disposed on the substrate, wherein the epitaxial layer has a first conductivity type (e.g., n-type epi drift region 306)
- a pair of well regions disposed in the epitaxial layer, wherein the pair of well regions has a second conductivity type that is different from the first conductivity type (e.g., p-type body regions 204)
- a pair of doping regions disposed in the pair of well regions, wherein the pair of doping regions has the first conductivity type (e.g., n-type source regions 212)
- a pair of first conductive structures (e.g., structure comprising 313,222) disposed on sides of the pair of well regions, respectively, wherein each of the first conductive structures comprises a first conductive layer (e.g., one of electrodes 313) and a first dielectric layer (e.g., dielectric material 222) covering a top surface of the first conductive layer
- a second conductive structure (e.g., structure comprising 310,311,226) disposed on the pair of well regions.
Regarding Claim 4, Challa (see, e.g., Fig. 3B, with reference to Figs. 1-2 for unlabeled analogous features) shows that the second conductive structure comprises a second conductive layer (e.g., electrode 310) and a second dielectric layer (e.g., dielectric layer 226) surrounding the second conductive layer.
Regarding Claim 5, Challa (see, e.g., Fig. 3B, with reference to Figs. 1-2 for unlabeled analogous features) shows that the second conductive structure comprises a pair of second conductive layers (e.g., electrodes 310 and 311) and a second dielectric layer (e.g., dielectric layer 226) surrounding the pair of second conductive layers.
Regarding Claim 7, Challa (see, e.g., Fig. 3B, with reference to Figs. 1-2 for unlabeled analogous features) shows that the pair of first conductive structures further comprises a pair of bottom conductive layers (e.g., pair of bottom 313s), wherein the pair of bottom conductive layers are spaced apart from the pair of first conductive layers by the pair of first dielectric layers (e.g., bottom 313s spaced apart from top 313s by 222).
Regarding Claim 8, Challa (see, e.g., Fig. 3B, with reference to Figs. 1-2 for unlabeled analogous features) shows that the pair of well regions (e.g., 204) is disposed between the pair of first conductive structures.
Regarding Claim 13, Challa (see, e.g., Fig. 3B, with reference to Figs. 1-2 for unlabeled analogous features) shows all aspects of the instant invention, including a semiconductor device (e.g., MOSFET 300B), comprising:
- a substrate (e.g., substrate region 214)
- an epitaxial layer disposed on the substrate, wherein the epitaxial layer has a first conductivity type (e.g., n-type epi drift region 306)
- at least one structural unit (see, e.g., Fig. 3B), wherein each of the structural units comprises:
a pair of first conductive structures (e.g., structure comprising 313,222) disposed on an outermost side of the structural unit, wherein each of the first conductive structures comprises a first conductive layer (e.g., one of electrodes 313) and a first dielectric layer (e.g., dielectric material 222) covering a top surface of the first conductive layer
a second conductive structure (e.g., structure comprising 310,311,226) disposed on the epitaxial layer
a pair of well regions disposed between the pair of first conductive structures, wherein the pair of well regions has a second conductivity type that is different from the first conductivity type (e.g., p-type body regions 204)
a pair of doping regions disposed in the pair of well regions, wherein the pair of doping regions has the first conductivity type (e.g., n-type source regions 212)
- wherein each of the structural units is symmetrical to a center of the second conductive structure.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Tawara et al. (US2024/0363692) in view of Imam et al. (US2023/0207682).
Regarding Claim 7, Tawara (see, e.g., Fig. 1) shows a pair of gate electrodes 9, each surrounded by insulating films 8,12. However, Tawara is silent about the pair of first conductive structures further comprises a pair of bottom conductive layers, as well as the remaining associated limitations. Imam (see, e.g., Fig. 1 and Par. [0024]-[0026]), on the other hand and in the same field of endeavor, teaches implementing a trench gate 160 as a “split-gate”, wherein the trench gate comprises a bottom conductive layer 160A, wherein the bottom conductive layer is spaced apart from a first conductive layer 160B by a pair of first dielectric layers 150, to reduce the on-resistance while maintaining the breakdown voltage.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the pair of first conductive structures comprising a par of bottom conductive layers as claimed in the structure of Tawara, as taught by Imam, to reduce the on-resistance while maintaining the breakdown voltage.
Response to Arguments
Applicant’s remarks with respect to the claims filed on 07/20/2026 have been considered but are moot in view of the new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul whose telephone number is (571) 270-5514. The examiner can normally be reached Monday-Friday 9am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814
