Attorney’s Docket Number: 0941-5058PUS1
Filing Date: 12/11/2023
Claimed Foreign Priority Date: none
Applicant(s): Tzou et al.
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the Election filed 03/30/2026.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's elections with traverse of Species 1 (directed to Figs. 1-5), in the reply filed on 03/30/2026, is acknowledged. Applicant indicated that claims 1-8 and 12-14 read on the elected Species. The examiner agrees. The traversal of the Species restriction is on the grounds that “it should be no undue burden on the Examiner to consider all claims in the single application.” This is not found persuasive.
As set forth in the restriction requirement mailed on 02/11/2026, the examiner additionally set forth that the application contained species including mutually exclusive characteristics. Fig. 1, for example, illustrates a structural unit U1 that is symmetrical to a center of a planar gate 600, wherein said planar gate is in direct contact with a pair of well regions 300. This arrangement of features, however are not present and/or illustrated in Fig. 6. Fig. 6, on the other hand, differently illustrates a structural unit U6 that is asymmetrical to a center of a planar gate 600, wherein said planar gate is in direct contact with a recessed gate 500, and overlaps an electron accumulation layer AC. This arrangement of features, however, are not present and/or illustrated on Fig. 1. Accordingly, at least Figs. 1 and 6 are not obvious variants of each other as they illustrate substantially different VMOSFET architectures, and therefore the unpatentability of one species would not necessarily imply the unpatentability of the other species.
Because of the above, and because the applicant failed to distinctly and specifically point out that the species are not patentably distinct (emphasis added), and did not present evidence or identify evidence on record showing the species to be obvious variations of one another, the requirement is still deemed proper and is, therefore, made FINAL.
Accordingly, pending in this application are claims 1-20, with Claims 9-11 and 15-20 standing withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 7 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 7 recites the limitation “wherein the pair of bottom conductive layers are spaced apart from the pair of first conductive layers by the pair of first dielectric layers.” in L. 2-4. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the claim will be construed as reciting -- wherein the pair of bottom conductive layers are spaced apart from the pair of first conductive layers by the pair of
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-6, 8, and 12-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Baliga (US2004/0099905).
Regarding Claim 1, Baliga (see, e.g., Figs. 1-2, 5, 9K, and 10) shows all aspects of the instant invention, including a semiconductor device, comprising:
- a substrate (e.g., substrate 100/200)
- an epitaxial layer disposed on the substrate, wherein the epitaxial layer has a first conductivity type (e.g., n-type epitaxial drift region 102/202)
- a pair of well regions disposed in the epitaxial layer, wherein the pair of well regions has a second conductivity type that is different from the first conductivity type (e.g., p-type base regions 126/226)
- a pair of doping regions disposed in the pair of well regions, wherein the pair of doping regions has the first conductivity type (e.g., n-type source regions 133/233)
- a pair of first conductive structures disposed on sides of the pair of well regions, respectively (e.g., trench-based electrodes 110,106/210,206)
- a second conductive structure disposed on the pair of well regions (e.g., insulated gate electrode 118,116/218,216).
Regarding Claim 4, Baliga (see, e.g., Figs. 1-2, 5, and 9K) shows that the second conductive structure comprises a second conductive layer and a second dielectric layer surrounding the second conductive layer (e.g., poly gate electrode 118/218 surrounded by gate oxide layer).
Regarding Claim 5, Baliga (see, e.g., Fig. 10) shows that the second conductive structure comprises a pair of second conductive layers and a second dielectric layer surrounding the pair of second conductive layer (e.g., pair of poly gate electrode 118a and 118b surrounded by gate oxide layer).
Regarding Claim 6, Baliga (see, e.g., Figs. 1-2, 5, 9K, and 10) shows that each of the first conductive structures comprises a first conductive layer (e.g., conductive region 110/210) and a dielectric layer surrounding the first conductive layer (e.g., trench insulating layer 106/206).
Regarding Claim 8, Baliga (see, e.g., Figs. 1-2, 5, 9K, and 10) shows that the pair of well regions (e.g., 126/226) is disposed between the pair of first conductive structures.
Regarding Claim 12, Baliga (see, e.g., Figs. 1-2, 5, 9K, and 10) shows an upper electrode layer (e.g., source electrode 138/238) and a lower electrode layer (e.g., drain electrode 136/236) respectively disposed on the epitaxial layer and under the substrate.
Regarding Claim 13, Baliga (see, e.g., Figs. 1-2, 5, and 9K) shows all aspects of the instant invention, including a semiconductor device, comprising:
- a substrate (e.g., substrate 100/200)
- an epitaxial layer disposed on the substrate, wherein the epitaxial layer has a first conductivity type (e.g., n-type epitaxial drift region 102/202)
- at least one structural unit, wherein each of the structural units comprises:
a pair of first conductive structures (e.g., trench-based electrodes 110,106/210,206) disposed on an outermost side of the structural unit
a second conductive structure (e.g., insulated gate electrode 118,116/218,216) disposed on the epitaxial layer
a pair of well regions disposed between the pair of first conductive structures, wherein the pair of well regions has a second conductivity type that is different from the first conductivity type (e.g., p-type base regions 126/226)
a pair of doping regions disposed in the pair of well regions, wherein the pair of doping regions has the first conductivity type (e.g., n-type source regions 133/233)
- wherein each of the structural units is symmetrical to a center of the second conductive structure (see, e.g., Figs. 1-2, 5, and 9K).
Claims 1-4, 6, 8, and 12-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lei et al. (CN113327976 and associated Machine Translation).
Regarding Claim 1, Lei (see, e.g., Figs. 9a, 13a) shows all aspects of the instant invention, including a semiconductor device, comprising:
- a substrate (e.g., semiconductor substrate 2)
- an epitaxial layer disposed on the substrate, wherein the epitaxial layer has a first conductivity type (e.g., epitaxial layer 3 of a first conductive type)
- a pair of well regions disposed in the epitaxial layer, wherein the pair of well regions has a second conductivity type that is different from the first conductivity type (e.g., body regions 10 of a second conductivity type)
- a pair of doping regions disposed in the pair of well regions, wherein the pair of doping regions has the first conductivity type (e.g., source regions 11 of the first conductivity type)
- a pair of first conductive structures disposed on sides of the pair of well regions, respectively (e.g., structures including trench gate 7 and portion of gate oxide layer 6)
- a second conductive structure disposed on the pair of well regions (e.g., structure including planar gate 8, and portions of gate oxide layer 6 and passivation layer 13).
Regarding Claim 2, Lei (see, e.g., Figs. 9a, 13a) shows a pair of shielding layers disposed under the pair of first conductive structures, respectively, wherein the pair of shielding layers has the second conductivity type (e.g., sub-portions 41 of the second conductive type).
Regarding Claim 3, Lei (see, e.g., Figs. 9a, 13a) shows a shielding layer disposed in the epitaxial layer, wherein the shielding layer is spaced apart from the second conductive structure by the epitaxial layer, wherein the shielding layer has the second conductivity type (e.g., sub-portion 41 of the second conductive type).
Regarding Claim 4, Lei (see, e.g., Figs. 9a, 13a) shows that the second conductive structure comprises a second conductive layer and a second dielectric layer surrounding the second conductive layer (e.g., planar gate 8 surrounded by dielectric layer including portions of gate oxide layer 6 and passivation layer 13).
Regarding Claim 6, Lei (see, e.g., Figs. 9a, 13a) shows that each of the first conductive structures comprises a first conductive layer and a dielectric layer surrounding the first conductive layer (e.g., poly trench gate 7 surrounded by dielectric layer including portions of gate oxide layer 6).
Regarding Claim 8, Lei (see, e.g., Figs. 9a, 13a) shows that the pair of well regions (e.g., 10) is disposed between the pair of first conductive structures.
Regarding Claim 12, Lei (see, e.g., Figs. 9a, 13a) shows an upper electrode layer (e.g., source electrode 9) and a lower electrode layer (e.g., drain electrode 1) respectively disposed on the epitaxial layer and under the substrate.
Regarding Claim 13, Lei (see, e.g., Figs. 9a, 13a) shows all aspects of the instant invention, including a semiconductor device, comprising:
- a substrate (e.g., semiconductor substrate 2)
- an epitaxial layer disposed on the substrate, wherein the epitaxial layer has a first conductivity type (e.g., epitaxial layer 3 of a first conductive type)
- at least one structural unit, wherein each of the structural units comprises:
a pair of first conductive structures (e.g., structures including trench gate 7 and portion of gate oxide layer 6) disposed on an outermost side of the structural unit
a second conductive structure (e.g., structure including planar gate 8, and portions of gate oxide layer 6 and passivation layer 13) disposed on the epitaxial layer
a pair of well regions disposed between the pair of first conductive structures, wherein the pair of well regions has a second conductivity type that is different from the first conductivity type (e.g., body regions 10 of a second conductivity type)
a pair of doping regions disposed in the pair of well regions, wherein the pair of doping regions has the first conductivity type (e.g., source regions 11 of the first conductivity type)
- wherein each of the structural units is symmetrical to a center of the second conductive structure (see, e.g., Figs. 9a and 13a).
Regarding Claim 14, Lei (see, e.g., Figs. 9a, 13a) discloses that each superjunction 41 comprises a plurality of sub-portions 41 that are vertically merged by a temperature annealing step (see, e.g., Fig. 4-5). Therefore, Lei also shows that the structural unit further comprises at least two shielding layers, wherein in a top view, the shielding layers are connected to each other (e.g., any two sub-potions 41 that are vertically stacked).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lei et al. (CN113327976 and associated Machine Translation) in view of Imam et al. (US2023/0207682).
Regarding Claim 7, Lei (see, e.g., Figs. 9a, 13a) shows a pair of poly trench gates 7, each surrounded by portions of gate oxide layer 6. However, Lei is silent about the pair of first conductive structures further comprises a pair of bottom conductive layers, as well as the remaining associated limitations. Imam (see, e.g., Fig. 1 and Par. [0024]-[0026]), on the other hand and in the same field of endeavor, teaches implementing a trench gate 160 as a “split-gate”, wherein the trench gate comprises a bottom conductive layer 160A, wherein the bottom conductive layer is spaced apart from a first conductive layer 160B by a pair of first dielectric layers 150, to reduce the on-resistance while maintaining the breakdown voltage.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the pair of first conductive structures as claimed in the structure of Lei, as taught by Imam, to reduce the on-resistance while maintaining the breakdown voltage.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional references cited disclose VDMOSFETs devices with planar gates and conductive trenches, and having arrangements of features anticipating the instant inventions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul whose telephone number is (571) 270-5514. The examiner can normally be reached Monday-Friday 9am-6pm EST), or by e-mail via younes.boulghassoul@uspto.gov. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814
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