DETAILED ACTION
This Office action responds to the patent application no. 18/536,343 filed on December 12, 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because there is missing a pattern in the box having a thickness TH6 in Fig. 9 where the same box having a pattern and being labeled as 160DN in Fig. 8. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “forming a pattern layer … to expose a plurality of exposing portions on a surface of the second hard mask layer; etching the second hard mask layer” must be shown or the feature(s) canceled from Claim 11. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: Although the similar method of manufacturing a capacitor array is described in paragraph (¶) [0014] as Claim 11, ¶ [0042] states “an N-type impurity is doped in a hard mask layer in the peripheral area” and ¶ [0044] states “the exposed portion of the hard mask layer is doped with the N-type impurity to form a doped hard mask layer 160DN” and ¶ [0045] states “a pattern layer 180 … to expose a plurality of third portion PR3 of a surface of the hard mask layer 106 and cover … a surface of the doped hard mask layer 160DN” and “the hard mask layer 160, the second cap layer 150 and the first cap layer 140 at the third portions (such as the third portion PR3 in Fig. 8) are etched”. The second embodiment with N-type impurity, does NOT teach the N-type doped second mask layer in the peripheral area, being etched away to form a plurality of trenches as described in Claim 11.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 11-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Although the similar method of manufacturing a capacitor array is described in paragraph (¶) [0014] as Claim 11, ¶ [0042] states “an N-type impurity is doped in a hard mask layer in the peripheral area” and ¶ [0044] states “the exposed portion of the hard mask layer is doped with the N-type impurity to form a doped hard mask layer 160DN” and ¶ [0045] states “a pattern layer 180 … to expose a plurality of third portion PR3 of a surface of the hard mask layer 106 and cover … a surface of the doped hard mask layer 160DN” and “the hard mask layer 160, the second cap layer 150 and the first cap layer 140 at the third portions (such as the third portion PR3 in Fig. 8) are etched”. The second embodiment with N-type impurity, does NOT teach the N-type doped second mask layer in the peripheral area, being etched away to form a plurality of trenches as described in Claim 11. The ¶ [0043] to ¶ [0047] of the specification only teach the undoped mask layer 160 and the first and second cap layers in the array area 110, are etched away to form a plurality of capacitor trenches and the doped mask layer 160DN and the first and second cap layers in the peripheral area 120, are NOT etched away to form a plurality of capacitor trenches.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Bhat et al. (Bhat hereinafter) (US 2007/0238259) in view of Lee et al. (Lee hereinafter) (US 8,846,540) and further in view of Wei et al. (We hereinafter) (US 2021/0134659).
Bhat (see FIGs. 1, 2, and 16) teaches {1} a method of manufacturing a capacitor array 25, comprising: providing a substrate 10 including a first cap layer 24 over the substrate, a second cap layer 26 on the first cap layer and, wherein the substrate is defined with an array area 25 and a peripheral area 75; etching the second cap layer and the first cap layer at the plurality of exposing portions to form a plurality of trenches 30; and forming a capacitor in each of the plurality of trenches; {8} the substrate comprises: a plurality of active areas, disposed in an upper portion of the substrate in the array area; and a contacting layer, disposed on the plurality of active areas in the array area and the peripheral area, and comprising a plurality of contact plugs 14; {9} the plurality of trenches expose a surface of the contacting layer, and positions of the plurality of trenches is corresponding to the plurality of contact plugs, respectively; {10} forming the capacitor in each of the plurality of trenches comprises: depositing a first conductive layer 32 on an inner surface of each of the plurality of trenches, wherein the first conductive layer directly contacts each of the plurality of contact plugs; depositing an insulating layer 60 on the first conductive layer; and depositing a second conductive layer 70 on the insulating layer.
Bhat (see ¶ [0050], [0051], [0052]) teaches “Substrate 10 … comprising a capacitor array area 25, a circuitry area 75 other than capacitor array area 25 … comprises a peripheral circuitry area”; “an insulative material 12 having electrically conductive storage node pillars 14 … be fabricated over some suitable underlying material, for example bulk monocrystalline and/or underlying circuitry”; and “Some insulative material 24 … might be homogeneous or comprise multiple different compositions and/or layers”.
However, Bhat does not explicitly teach {1} a first hard mask layer on the second cap layer; forming a photoresist layer on the first hard mask layer in the peripheral area and exposing the first hard mask layer in the array area; doping a P-type impurity in the first hard mask layer exposed by the photoresist layer to form a second hard mask layer; forming a pattern layer on the first hard mask layer and the second hard mask layer to expose a plurality of exposing portions on a surface of the second hard mask layer; etching the second hard mask layer; {2} a concentration of the P-type impurity is a range from 2×1014 to 2×1018 ions/cm2; {3} the P-type impurity is boron; {4} the plurality of trenches is performed by a dry etching process with halogen-based gas; {5} the first cap layer has a first thickness, the second cap layer has a second thickness, the first hard mask layer has a third thickness, and the photoresist layer has a fourth thickness
Lee (see FIGs. 1A-2F and col.2/ll.48-57, col.3/ll.23-61, col.4/ll.12-49, col.5/ll.10-58) teaches a photoresist pattern 160 on a carbon-containing pattern/a third hard mask layer 150 on a second hard mask layer 14 on a first hard mask layer 13 on an etch target layer 12 on a substrate 11 and “the etch target layer 12 may include an oxide layer and a nitride layer … a plurality of oxide layers …a plurality of oxide layers and nitride layers that are alternately stacked”; “The first hard mask layer 13 may include an undoped polysilicon layer. The second hard mask layer 14 may include an impurity-doped polysilicon layer … to form the first hard mask layer 13 to have a larger thickness than the second hard mask layer 14 … to form the second hard mask layer 14 to have larger thickness than the first hard mask layer 13 … may have the same thickness … the impurity doped into the second hard mask layer 14 may include boron (B) … doping concentration of boron may range from about 1x1017 atoms/cm3 to 1x1018 atoms/cm3”; “During a dry etch process using plasma or the like, a polysilicon layer has a larger etch rate than an amorphous silicon layer … a phosphorus-doped polysilicon layer has the largest etch rate … the boron-doped polysilicon layer has a small etch rate … the boron-doped polysilicon layer may be formed to a minimum thickness, a tapered profile may be suppressed”; and “When the first and second hard mask layers 13 and 14 are etched, a gas having a high selectivity with respect to the etch target layer 12 may be used as an etching gas … a gas mixture of HBr, NF3, and O3 may be used … The etch target layer 12 may be etched by dry etching … When the etch target layer 12 includes oxide, an etching gas having a high selectivity with respect to the first and second hard mask layers 13 and 14 may be used to etch the etch target layer 12”
Wei (see FIGs. 1-2 and ¶ [0015], [0016], [0035]) teaches a mask material layer 13 on an etch stop layer 12 on a substrate 10 and “The mask material layer 13 includes a doped mask layer 13a doped with ions and a sacrificial mask layer 13c not doped with ions … Etching resistance of the doped mask layer 13a is greater than etching resistance of the sacrificial mask layer 13c”; “first trench 16 are formed in the mask layer 13 on both sides of the sacrificial mask layer 13c”; “the step of the doping treatment includes: forming a first pattern layer (not shown) on the mask material layer 130 … performing doping treatment on the mask material layer 130 exposed by the first pattern layer by using an ion implantation process; and after the doping treatment, removing the first pattern layer … by adjusting the implantation dose, the etch selectivity between the sacrificial mask layer 130c and the doped mask layer 130a can be easily adjusted”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Bhat to include the teaching of Lee to add additional doped and undoped mask layers and photoresist layer on the silicon nitride layer to better control the dry etching rates when trenches with a high aspect ratio, are etched and to further include the teaching of Wei to arrange the doped and undoped mask layers laterally and to place the doped mask layers in the capacitor array area where capacitor trenches are formed, to improve the accuracy of pattern transfer.
Allowable Subject Matter
Claims 6 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALICE W TANG whose telephone number is (571)272-7227. The examiner can normally be reached Monday-Friday: 8:30 am to 5 pm..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALICE W TANG/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814