Prosecution Insights
Last updated: July 17, 2026
Application No. 18/536,597

SEMICONDUCTOR DEVICE STRUCTURE WITH BACKSIDE PICK-UP REGION AND METHOD OF MANUFACTURING THE SAME

Non-Final OA §102
Filed
Dec 12, 2023
Examiner
CHEN, JACK S J
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
NANYA TECHNOLOGY Corporation
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
82%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
438 granted / 572 resolved
+8.6% vs TC avg
Moderate +5% lift
Without
With
+5.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
49 currently pending
Career history
610
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
53.6%
+13.6% vs TC avg
§102
23.8%
-16.2% vs TC avg
§112
9.9%
-30.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 572 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Species I, with claims 1-7 and 12-18 indicated by Applicant to read thereon, in the reply filed on 3/9/2026 is acknowledged. While Examiner acknowledges that Applicant indicated that claims 7 and 12-13 read on the elected species I, claim 7 is drawn to non-elected species 5 and/or 6 and is hereby withdrawn from further consideration therefor. Similarly, claims 12-13 does not read on the elected species because the elected specie at least fails to show having a second pick-up region abutting the second surface of the substrate and having the second conductive type. Claims 7-13 and 19-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/9/2026. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-2, 6, 14 and 18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee, US Pub. No. 2024/0105838 A1. Re claim 1, Lee discloses a semiconductor device structure, comprising: a substrate 110 (or a portion of 110, e.g., fig. 1) having a first surface and a second surface opposite to the first surface; a first well region 134 abutting the second surface of the substrate and having a first conducive type (e.g., P-type, fig. 1); a source/drain (S/D) feature 136/138 abutting the second surface of the substrate and having a second conductive type (e.g., N-type, fig. 1) different from the first conductive type; and a first pick-up region 131 and/or 132 (e.g., fig. 1, in this case, the layer/well region 131/132 is considered as the pick-up region) abutting the first surface of the substrate and having the first conductive type, see figs. 1-8 and pages 1-7 for more details. Re claim 2, The semiconductor device structure of claim 1, wherein the first pick-up region is exposed by the first surface of the substrate (e.g., fig. 1). Re claim 6, The semiconductor device structure of claim 1, further comprising: an isolation structure 140 (e.g, fig. 1) embedded within the substrate and abutting the second surface, wherein the first pick-up region 132 is spaced apart from the isolation structure 140 (e.g., fig. 1). Re claim 14, Lee discloses a semiconductor device structure, comprising: a substrate 110 (or a portion of 110, e.g., fig. 1) having a first surface and a second surface opposite to the first surface; a first well region 134 abutting the second surface of the substrate and having a first conducive type (e.g., P-type, fig. 1); a source/drain (S/D) feature 136/138 abutting the second surface of the substrate and having a second conductive type (e.g., N-type, fig. 1) different from the first conductive type; an isolation structure 140 (e.g., fig. 1) embedded within the substrate and extending from the second surface toward the first surface of the substrate; and a first pick-up region 132/131 (e.g, fig. 1) having the first conductive type situated between the first surface of the substrate and the isolation structure, see figs. 1-8 and pages 1-7 for more details. Re claim 18, The semiconductor device structure of claim 13, wherein the first pick-up region 132 is spaced apart from the isolation structure 140 (e.g., fig. 1). Allowable Subject Matter Claims 3-5 and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Prior art fails to further show an electrical connector disposed on the first surface and electrically connected to the first pick-up region. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK CHEN whose telephone number is (571)272-1689. The examiner can normally be reached Monday to Friday, 8am to 4pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571)270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JACK S CHEN/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Dec 12, 2023
Application Filed
Jun 18, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12684829
FIELD EFFECT TRANSISTOR
2y 5m to grant Granted Jul 14, 2026
Patent 12677458
HYBRID COMPONENT WITH SILICON AND WIDE BANDGAP SEMCONDUCTOR MATERIAL IN SILICON RECESS
4y 9m to grant Granted Jul 07, 2026
Patent 12666669
Field-Effect Transistor Device with Equivalent Source and Drain Region Optimization
2y 4m to grant Granted Jun 23, 2026
Patent 12656670
Display System and Method for Making and Using Same
4y 1m to grant Granted Jun 16, 2026
Patent 12660216
LOW-LEAKAGE SCHOTTKY DIODES AND METHOD OF MAKING A POWER SEMICONDUCTOR DEVICE
3y 5m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
82%
With Interview (+5.2%)
2y 11m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 572 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month