DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of the Invention I and identified claims 1-11 in the reply filed on 03/09/26is acknowledged.
Claims 12-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 03/09/26.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-11 are rejected under 35 U.S.C. 103 as being unpatentable over Youn (US 20100221889 A1) in view of Zhong (US 7, 169, 676), and further in view of Sasaki et al. (US 20010017400 A1; hereafter Sasaki).
As of Claim 1: Youn semiconductor device (¶0021 and note that semiconductor devices of FIG. 5 and FIG. 9 and FIGS. 5 and 9 are cross-sectional views of the semiconductor devices cut along the line A-A of FIGS. 6 and 10, respectively), comprising: a bottom portion, comprising a first stack structure, a first impurity region (¶0024 and note that first impurity regions 126), and a conductive plug; and an upper portion, disposed over the bottom portion, comprising a second stack structure and a second impurity region (¶0024 and note that second impurity regions 128 ), wherein the first stack structure comprises a plurality of gate assemblies coupled to the first impurity region, and the second stack structure comprises a plurality of capacitor sub-units coupled to the second impurity region (¶¶0028 and note that capacitors electrically connected to the first impurity regions 126 through the exposed first contact plugs 142 ), wherein the first impurity region is electrically coupled to the second impurity region through the conductive plug, wherein the conductive plug comprises: a plurality of conductive layer; a dielectric layer (¶¶0028 and note that FIG. 4, a dielectric material layer 152a ).
Zhong is a similar or analogous system to the claimed invention as evidenced Zhong teaches semiconductors having electrically coupled gate and impurity doped regions and methods for fabricating that would have prompted a predictable variation of Youn by applying Zhong ’s known principal of surrounding the plurality of conductive layers; and a top conductive layer, electrically coupled to the plurality of conductive layers, wherein each of the plurality of conductive layers are extended along a direction (Col. 2, lines 36-48).
In view of the motivations such as providing a semiconductor device utilizing only one contact to regulate the voltage of both the gate electrode and one of the drain or source electrode. thereby eliminate redundancy of contacts to reduce device size further improving image quality one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Youn.
Therefore, the claimed invention would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Sasaki is a similar or analogous system to the claimed invention as evidenced Sasaki teaches efficiently promoting the expansion of the depletion layer (19) than the electrically insulating film (14) having a suppressor electrode layer (20) buried therein is arranged between narrow portions (23b) of the suppressor electrode layer to control the expansion of the depletion layer that would have prompted a predictable variation of Youn by applying Sasaki ’s known principal of wherein the direction and a top surface of the first impurity region form an acute angle (¶¶0025,0101,0118).
In view of the motivations such as reducing the width of the respective slits, in other words, the spacing between the narrow portions thereby to produce semiconductor devices in reduced sizes further improving compactness of the device one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Youn.
Therefore, the claimed invention would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
As of Claim 2: Youn in view of Zhong in view of Sasaki further teaches the bottom portion further comprises: a substrate; and a middle insulation layer, wherein the first stack structure is disposed over the substrate (Youn ¶¶0038-0039 and note that a fifth insulating layer 136 may be formed on the first and second metal studs 162 and 166 and the fourth insulating layer 135. The fifth insulating layer 136 may include an interlayer insulating layer. The fifth insulating layer 136 may have a thickness corresponding to height of via holes that are to be formed in a later process. A sixth insulating layer 137 may be formed on the fifth insulating layer 136. The sixth insulating layer 137 may include an interlayer insulating layer. The sixth insulating layer 137 may have a thickness corresponding to height of trenches that are to be formed in a later process), and the middle insulation layer is disposed over the first stack structure, wherein the conductive plug penetrates through the middle insulation layer to be in contact with the first stack structure (Youn ¶¶0022,0025).
As of Claim 3: Youn in view of Zhong in view of Sasaki further teaches the bottom portion further comprises: a buried bit line, buried in the substrate; a third impurity region, wherein the first impurity region and the third impurity region are disposed on opposite sides of the first stack structure (Youn ¶¶0030,0032 and note that FIGS. 5 and 6, a photosensitive layer (not illustrated) is formed on the second etching stop layer 155a. The photosensitive layer may expose a part of the second etching stop layer 155a corresponding to another one of the first contact plugs 142 in the cell area 101 and may expose the entire surface of the second etching stop layer 155a in the logic area 105. The exposed first contact plug 142 may include the contact plug contacting the first impurity region 126 corresponding to the drain region in the first impurity regions 126.); a insulation material, disposed over the first stack structure, the first impurity region, the third impurity region, and the substrate; and an insulation layer, disposed over the insulation material, wherein the middle insulation layer is in contact with the insulation layer, the insulation material, and the first stack structure (Zhong Col. 4, paragraph II and note that "semiconductor substrate" is also used to encompass the substrate itself together with metal or insulator layers that may overly the substrate. Silicon substrate 142 may be a bulk silicon wafer or a thin layer of silicon 143 on an insulating layer 145 at commonly know as a silicon-on-insulator wafer or SOI wafer) that, in turn, is supported by a silicon carrier wafer 147. A layer of gate insulator 144 is formed on the surface of silicon substrate 142. The gate insulator may be a thermally grown silicon dioxide formed by heating the silicon substrate in an oxidizing ambient, or may be a deposited insulator such as a silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant insulator).
As of Claim 4: Youn in view of Zhong in view of Sasaki further teaches the conductive plug further penetrates the insulation layer and insulation material (Zhong Col. 4, paragraph II and note that a conductive plug 54. Conductive plug 54 is formed through openings in an insulator layer 66, which provides electrical isolation between transistor 40 and overlying layers of interconnecting metal.).
As of Claim 5: Youn in view of Zhong in view of Sasaki further teaches each of the plurality of conductive layers are separated from each other by the dielectric layer (Zhong Col. 4, paragraph II and note that FIG. 18, a layer of dielectric insulating material 206 is deposited and subsequently photolithographically patterned and etched to form opening 210 extending through the insulating material 206 and exposing a portion of first metal silicide contact 202 on drain region 160. The insulating layer may be planarized by a chemical mechanical planarization (CMP) process before patterning. Conductive plug 208 is then formed in opening 210 so that the drain region 160 can be appropriately electrically connected to other devices in the integrated circuit to implement the desired circuit function. ).
As of Claim 6: Youn in view of Zhong in view of Sasaki further teaches the first impurity region is in contact with the plurality of conductive layers and the dielectric layer, the second impurity region is in contact with the top conductive layer (Youn ¶¶0032 and note the upper electrode 153 of the capacitor in the cell area 101 may be formed as a front electrode in which the window 154 is disposed in correspondence with a part on which metal plugs for bit lines are to be formed in a later process. The window 154 may expose a part of the second insulating layer 132 corresponding to the first contact plug 142 that contacts the first impurity region 126 corresponding to the drain region. ).
As of Claim 7: Youn in view of Zhong in view of Sasaki further teaches the upper portion further comprises a fourth impurity region, wherein the second impurity region and the fourth impurity region are disposed on opposite sides of the second stack structure (Youn ¶¶0024-0026).
As of Claim 8: Youn in view of Zhong in view of Sasaki further teaches each of the plurality of gate assemblies comprises: a gate electrode; a gate dielectric, enclosing the gate electrode; and a first semiconductor layer (Youn ¶¶0023, 0026 and note that the semiconductor substrate 100 and a logic transistor may be formed in the logic area 105 of the semiconductor substrate 100. First gates 120 may be formed on the semiconductor substrate 100 in the cell area 101 and a second gate 125 may be formed on the semiconductor substrate 100 in the logic area 105. The first and second gates 120 and 125 may include a gate insulating layer 121, a gate electrode layer 122 disposed on the gate insulating layer 121, and a gate spacer 124 disposed on a side wall of the gate electrode layer 122. The first and second gates 120 and 125 may further include a silicide layer 123 formed on the gate electrode layer 122.).
As of Claim 9: Youn in view of Zhong in view of Sasaki further teaches the first stack structure further comprises: a first inner spacer; and a second inner spacer, wherein the first inner spacer and the second inner spacer are disposed on opposite sides of the first stack structure (Youn ¶¶0023 and note that First gates 120 may be formed on the semiconductor substrate 100 in the cell area 101 and a second gate 125 may be formed on the semiconductor substrate 100 in the logic area 105. The first and second gates 120 and 125 may include a gate insulating layer 121, a gate electrode layer 122 disposed on the gate insulating layer 121, and a gate spacer 124 disposed on a side wall of the gate electrode layer 122. The first and second gates 120 and 125 may further include a silicide layer 123 formed on the gate electrode layer 122.), wherein each of the first semiconductor layer of plurality of gate assemblies protrudes from the first inner spacer, and protruding portions of the each of the first semiconductor layer are electrically coupled to the first impurity region (Zhong Col. 4, paragraph II and note that a layer preferably of polycrystalline silicon 146 is deposited onto the layer of gate insulator. The layer of polycrystalline silicon can be deposited as an impurity doped layer, but is preferably deposited as undoped polycrystalline silicon and is subsequently impurity doped by ion implantation. A layer 148 of hard mask material such as silicon oxide, silicon nitride, or silicon oxynitride can be deposited onto the surface of the polycrystalline silicon to aid in subsequently patterning the polycrystalline silicon.).
As of Claim 10: Youn in view of Zhong in view of Sasaki further teaches each of the plurality of capacitor sub-units comprises: a capacitor electrode; and a capacitor dielectric, enclosing the capacitor electrode, wherein the second stack structure further comprises a plurality of second semiconductor layers, wherein the plurality of second semiconductor layers and the plurality of capacitor sub-units are interposed (Youn ¶¶0028-0033 and note that FIG. 7, a third insulating layer 134 may be formed on the second insulating layer 132 including capacitors 150 that include the lower electrodes 151, the dielectric material layers 152, and the upper electrodes 153. The third insulating layer 134 may include an interlayer insulating layer. A step difference in the third insulating layer 134 is generated between the cell area 101 and the logic area 105 due to formation of the capacitors 150 in the cell area 101).
As of Claim 11: Youn in view of Zhong in view of Sasaki further teaches the second stack structure further comprises: a third inner spacer; and a fourth inner spacer, wherein the third inner spacer and the fourth inner spacer are disposed on opposite sides of the second stack structure (Zhong Col. 4, paragraph IV and note that FIG. 4, zero spacers 157 disposed along side surfaces 151 and 153 of gate electrode 150 and offset spacers 159 disposed proximate to zero spacers 157, as illustrated in FIG. 5. Zero spacers 157 serve to protect the thin gate insulator that would otherwise be exposed at the edge of gate electrode 150. Zero spacers 157 also provide a barrier separating the polycrystalline silicon of gate electrode 150 from the material of offset spacers 159.), wherein each of the second semiconductor layers protrudes from the third inner spacer, and protruding portions of the each of the second semiconductor layers are electrically coupled to the second impurity region (Zhong Col. 3, paragraph II and note that FIG. 1 illustrates schematically, in cross section, an MOS transistor 40 in accordance with an embodiment of the invention. MOS transistor 40 includes a silicon substrate 42, or a layer of silicon on an insulating substrate, with a gate insulator 44 formed on the substrate surface. A gate electrode 46 is formed on the gate insulator. In an exemplary embodiment of the invention, a thin zero spacer 60 is disposed about a first side surface 56 and a second side surface 58 of gate electrode 46 and an offset spacer 62 is disposed proximate to the zero spacer 60. An oxide liner 64 is disposed proximate to the offset spacer 62 and proximate to first and second side surfaces 56, 58 of gate electrode 46 ).
Conclusion
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/MEKONNEN D DAGNEW/Primary Examiner, Art Unit 2638