DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims.
Specifically, Claims 11 and 12 include the Claim 11 step c) limitation of “forming doped areas in the first doped region under and in contact with a lower surface of the first insulating trenches, the doped areas having a doping level greater than a doped level of the first doped region”. However, the “doped areas” (33, Fig. 3D) are formed before the formation of “the first doped region” (25, Fig. 3F). Therefore, Claim 11 step c) is not shown in any of the drawings because they do not show “forming doped areas in the first doped region”.
These features must be shown or canceled from the claims. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the claim includes the limitations:
“a second doped region of the first conductivity type in a first portion of the first doped region (the second doped region has a second conductivity type);
a third doped region of the second conductivity type located in a second portion of the first doped region below and in contact with the second doped region;
a doped area in the first doped region under and in contact with a lower surface of each first insulating trench, wherein each doped area has a doping level greater than a doped level of the first doped region”
As to the first claim limitation above, the claims of a second doped region in a first portion of the first doped region appears to be contradictory, because the first doped region is specifically a second conductivity type and the second doped region is a first conductivity type, it is unclear how a region of one conductivity type would be considered part of region of a different conductivity type – it seems these would be ‘different regions having their own boundaries’ and not one inside the other (one could surround the other, but both would have their own boundaries). Based on the specification and the method claims present, it appears Applicant may be conflating ‘forming’ a second region from a part of the first region, with a device claim in which only the end product is given patentable weight.
As to the second limitation of ‘a third doped region of the second conductivity type located in a second portion of the first doped region’ because these regions are both of the second conductivity type, one could be a sub region of the other, but it would more clear to describe the boundary than being described as a region within the same conductivity type in another region of the same conductivity type.
The third limitation describes a doped area in the first doped region, but then says that each doped area has a doping level greater than a doped level of the first doped region, but if the doped areas are part of the doped region (because the doped areas are in the doped region) how would they have a greater doping level than themselves? This limitation may be best stated as “a doped area in the first doped region under and in contact with a lower surface of each first insulating trench, wherein each doped area has a doping level greater than a doped level of the other sections of the first doped region. (this is only an example and may be different based on how the other parts of the claim are changed).
Claims 2-10 include all of the limitations of Claim 1 and do not clarify the ambiguity described supra. Therefore, they fall under the same rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Anderson et al. (“Anderson”), US 2008/0203537 (listed in the IDS) in view of Ohguro, US 2003/0122155 (listed in the IDS).
Regarding Claim 1, Anderson discloses a variable-capacitance diode (105C; Figs. 3A-3B; ¶ 0010, 0030), comprising:
a semiconductor substrate (100; Fig. 3B; ¶ 0024);
a first doped region (110, 115, 125, 130, 140C; Fig. 3B; ¶ 0023, 0026, 0027, 0030) of a second conductivity type opposite (N-type; ¶ 0026) to the first conductivity type in the doped semiconductor substrate;
a second doped region (120A, 120B; Fig. 3B; ¶ 0026) of the first conductivity type (P-type; ¶ 0026) in a first portion of the first doped region (Fig. 3B);
a third doped region (140C; Fig. 3B; ¶ 0030) of the second conductivity type located in a second portion of the first doped region below and in contact with the second doped region (Fig. 3B), wherein an interface between the second and third doped regions defines a PN junction of the variable-capacitance diode (Fig. 3B; ¶ 0027, 0030);
first insulating trenches (135; Fig. 3B; ¶ 0027, 0030) laterally delimiting said PN junction (Fig. 3B), the first insulating trenches having a depth smaller than a depth of the first doped region (Fig. 3B; ¶ 0030);
contacting areas (125; Fig. 3B; ¶ 0023) for the first doped region located in a third portion of the first doped region at an opposite side of the first insulating trenches from the PN junction (Fig. 3B; ¶ 0023 “contact 125 is isolated from both first and second anodes 120A and 120B by regions of dielectric isolation 135”); and
a doped area (140C; Fig. 3B see areas in annotated Fig. 3B infra) in the first doped region under and in contact with a lower surface of each first insulating trench (Fig. 3B see annotated Fig 3B infra), wherein each doped area has a doping level greater than (N+; Fig. 3B; ¶ 0028) a doped level (N; Fig. 3B) of the first doped region.
Anderson does not disclose a doped semiconductor substrate of a first conductivity type.
Ohguro discloses a doped semiconductor substrate (11; Fig. 1; ¶ 0042 “P type semiconductor substrate 11”) of a first conductivity type (Fig. 1; ¶ 0042 “P-type”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Anderson to have a doped semiconductor substrate of a first conductivity type, as taught by Ohguro, because it lowers resistance to increase conductivity (Ohguro ¶ 0042) thereby improving the performance of the variable-capacitance diode.
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Regarding Claim 2, Anderson discloses wherein the first doped region has a doping in the range from 1x1017 atoms/cm3 to 1x1019 atoms/cm3 (¶ 0026 “between about 1E11 atoms/cm.sup.3 and about 1E21 atoms/cm.sup.3”).
Regarding Claim 3, Anderson discloses wherein the doped areas have a doping in the range from 1x1017 atoms/cm3 to 1x1020 atoms/cm3 (¶ 0028 “between about 1E11 atoms/cm.sup.3 and about 1E19 atoms/cm.sup.3”).
Regarding Claim 4, Anderson discloses wherein the first doped region is delimited in a ring shape (Fig. 3A; ¶ 0030) by a second insulating trench (135; Figs. 3A-3B; ¶ 0030 the outside ring 135 in Fig. 3A, the leftmost and rightmost 135 in Fig. 3B).
Regarding Claim 5, Anderson discloses wherein the second insulating trench has a depth greater than a depth of the first doped region (Fig. 3B second insulating trench 135 has a depth greater than region 125).
Regarding Claim 6, Anderson discloses wherein the contacting areas are more heavily doped than the first doped region (Fig. 3B contacting areas 125 are N+ and first doped region has N).
Regarding Claim 7, Anderson discloses wherein the contacting areas provide cathode contacts for the variable-capacitance diode (Fig. 3B; ¶ 0023 “cathode contact 125”).
Regarding Claim 8, Anderson discloses wherein the second doped regions provide anode contacts for the variable-capacitance diode (Fig. 3B; ¶ 0023 “anodes 120A and 120B extend from the top surface of the substrate into the substrate”, ¶ 0030 “anodes 120A and 120B”).
Regarding Claim 9, Anderson does not disclose wherein the doped areas provide decreased parasitic resistance under the first insulating trenches.
Ohguro discloses wherein the doped areas provide decreased parasitic resistance under the first insulating trenches (¶ 0043 an area “higher in impurity concentration” is “lower in resistive value”, therefore the Anderson N+ doped area 140C provides decreased parasitic resistance under the first insulating trenches 135).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Anderson to have wherein the doped areas provide decreased parasitic resistance under the first insulating trenches, as taught by Ohguro, because the lower resistance increases conductivity (Ohguro ¶ 0042) thereby improving the performance of the variable-capacitance diode.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Anderson et al. (“Anderson”), US 2008/0203537 (listed in the IDS) and Ohguro, US 2003/0122155 (listed in the IDS) in view of Welch et al. (“Welch”), US 2011/0031588 (listed in IDS).
Regarding Claim 11, Anderson discloses a method (all instances of forming below are being interpreted as when a structure is formed in relation to another structure, the presence of the first structure means it was formed at some time in relation to the other structure) of manufacturing a variable-capacitance diode (105C; Figs. 3A-3B; ¶ 0030), comprising:
a) forming a first doped region (110, 115, 125, 130, 140C; Fig. 3B; ¶ 0023, 0026, 0027, 0030) in a semiconductor substrate (100; Fig. 3B; ¶ 0024), the first doped region being doped with a second conductivity type (N-type; ¶ 0026) opposite to the first conductivity type;
b) forming first insulating trenches (135; Fig. 3B; ¶ 0027, 0030) having a depth smaller than a depth of the first doped region (Fig. 3B; ¶ 0030);
c) forming doped areas (140C; Fig. 3B see areas in annotated Fig. 3B supra) in the first doped region under and in contact with a lower surface of the first insulating trenches (Fig. 3B see annotated Fig. 3B supra), the doped areas having a doping level greater than (N+, Fig. 3B) a doped level (N, Fig. 3B) of the first doped region;
d) forming a second doped region (120A, 120B; Fig. 3B; ¶ 0026) of the first conductivity type (P-type; ¶ 0026);
e) forming a third doped region (140C; Fig. 3B; ¶ 0030) of the second conductivity type in a second portion of the first region under and in contact with the second doped regions (Fig. 3B third doped region 140C is in contact with second doped regions 120A and 120B), wherein an interface between the second and third doped regions defines a PN junction of the variable-capacitance diode (Fig. 3B; ¶ 0027), and wherein each PN junction is laterally delimited by the first insulating trenches (Fig. 3B); and
f) forming contacting areas (125; Fig. 3B; ¶ 0023) in another portion of the first doped region on either side of the first insulating trenches (Fig. 3B; ¶ 0023 “contact 125 is isolated from both first and second anodes 120A and 120B by regions of dielectric isolation 135”).
Anderson does not disclose a doped semiconductor substrate of a first conductivity type, and d) forming a second doped region of the first conductivity type in a first portion of the first region.
Ohguro discloses a doped semiconductor substrate (11; Fig. 1; ¶ 0042 “P type semiconductor substrate 11”) of a first conductivity type (Fig. 1; ¶ 0042 “P-type”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Anderson to have a doped semiconductor substrate of a first conductivity type, as taught by Ohguro, because it lowers resistance to increase conductivity (Ohguro ¶ 0042) thereby improving the performance of the variable-capacitance diode.
Anderson as modified does not specifically disclose d) forming a second doped region of the first conductivity type in a first portion of the first region.
Welch discloses d) forming a second doped region of the first conductivity type in a first portion of the first region (Fig. 12; ¶ 0033 “Implant F is provided to form relatively shallow highly doped contact region 36(P+) of depth 363 in HA region 34(N)”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Anderson as modified to have d) forming a second doped region of the first conductivity type in a first portion of the first region, as taught by Welch, in order to form a varactor junction (Welch ¶0033).
Regarding Claim 12, Anderson as modified does not specifically disclose wherein step c) is carried out after step b). However, Anderson discloses “isolation 135 extends into but not through abrupt cathode junction region 140C” (Fig. 3B; ¶ 0030). It would be obvious to form the insulating trenches 135 of Anderson (Fig. 3B) before forming the doped area 140C of Anderson because forming the insulating trenches 135 first will allow the doped area 140C to penetrate deeper into first doped region 115 to help ensure that insulating trenches 135 do not penetrate doped area 140C.
Regarding Claim 13, Anderson as modified by Ohguro does not disclose wherein the first insulating trench and the doped areas are formed through a same masking layer.
Welch discloses wherein the first insulating trench (882, 883;Fig. 4; ¶ 0023 “cavities 882, 883 (which will be filled with dielectric to provide STI regions 282, 283 in finished device”) and the doped areas (261(N), 262(N); Fig. 6; ¶ 0025 “Implant A is provided through openings 872, 873 so as to form sub-isolation buried layer (SIBL) regions 261(N) and 262(N), collectively 26(N) in cavities or trenches 882, 883”) are formed through a same masking layer (86, 861, 861, 863; Figs. 4, 6; ¶ 0022 “Mask 86 of thickness 864 is applied and patterned to have closed portions 861, 862, 863 and openings 871, 872, 873, 874 collectively 87”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Anderson as modified by Ohguro to have wherein the first insulating trench and the doped areas are formed through a same masking layer, as taught by Welch, in order to efficiently form the first insulating trench and the doped areas (Welch ¶ 0023-0025) and reduce the cost of manufacturing a variable-capacitance diode.
Allowable Subject Matter
Claim 10 would likely be allowable if Claim 1 was rewritten to overcome the rejections under 35 U.S.C. 112(b) described supra, and Claim 10 was rewritten in independent form to include all of the limitations of the base Claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Coolbaugh et al., US 2006/0145300, discloses a varactor having a semiconductor substrate, a junction, and a cathode contact region. Collins et al., US 2007/0278614, discloses a PN diode having a deep trench annular insulating trench. Taya et al., US 2021/0398860, discloses a variable-capacitance diode in a P-type semiconductor substrate and a PN junction.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Rose Keagy whose telephone number is (571) 270-3455. The examiner can normally be reached Mon-Fri. 8am-5pm (CT).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/R.K./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818