Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
OFFICE ACTION
This is a response to the election filed on 9/21/2026.
The Applicant elects group 3 (claims 12-20) with traverse and request rejoinder and/or filing divisional application for the non-elected claims.
The Applicant traverses on the grounds that:
The group share significant overlapping subject matter;
All group employing batteries to distribute/provide/delivery power to electronic modules/components/circuits;
Distributing batteries within/embedded/integrated/packed in a 3D-IC;
Common subject matter/elements and not independent inventions
. 5. Each group involves same fundamental components within/ embedded in IC package;
The prior art applicable to one group is highly likely to be applicable to the other groups; and
Prior art relevant to any one group would inherently encompass prior art relevant to the other groups.
According to the above Applicant reasons for traversal, the Examiner withdraws the restriction and considers all 3 groups claims 1-20, claims 1, 9, 12, are independent claims, for examination as having similar subject matter. Any prior art references being used to rejection one group will used to reject other groups for the same reason that the Applicant admits above; and/or for the same reason as having similar subject matter based on the Applicant ground traversal above.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) The claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) The claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 9-10,12-20 are rejected under 35 U.S.C. 102(a) (1) being anticipated by the prior art of record Matsumoto (US 2019/0074552)
Regarding claim 1, the prior art discloses
A 3D-IC (battery embedded structure, stacked battery (title, abstract))) comprising:
a first electronic module (first one on electronic components (par 3-6)) disposed on a substrate of the 3D-IC;
a first battery (first one of six stack battery units/cells (par 41, 96)) disposed on the first electronic module and electronically coupled to the first electronic module, wherein the first battery (first one on electronic components (par 3-6)) is configured to provide power to the first electronic module (first one on electronic components (par 3-6)) ;
a second electronic module (second one on electronic components (par 3-6)) disposed on the first battery; and
a second battery (second one of six stack battery units/cells (par 41, 96)) disposed on the second electronic module (second one on electronic components (par 3-6)) and electronically coupled to the second electronic module, wherein the second battery (second one of six stack battery units/cells (par 41, 96)) is configured to provide power to the second electronic module.
(Claim 2) wherein the first electronic module comprises at least one of a first processor, a first memory, a first radio frequency circuit, or first a sensor circuit and the second electronic module comprises at least one of a second processor, a second memory, a second radio frequency circuit, or a second sensor circuit (par 3, 24, 47, 82-98)
(Claims 3-4) TSV connections (par 49-53)
(Claims 5-6) disposing six batteries + housing (par 41, 96)
Claims 9-10 and 12-20 in groups 2-3 are rejected for the same reason based on the Application grounds of traverse above and/or similar subject matter. For interposer see fig 2-3, 11. For voltage regulator see par 3, 24.
Claims 1-2, 9-10, 12 and 19 are rejected under 35 U.S.C. 102(a) (1) being anticipated by the prior art of record Matsumura (US 2017/0163048)
Regarding claim 9 and similarly recited/ inherently encompass claims 1,
And 12, the prior art discloses:
A three-dimensional integrated circuit 3D-IC (fig 1, 10, 11) comprising:
two or more electronic modules (par 32-35);
two or more batteries (fig 14-15), wherein a battery of the two or more batteries is configured to provide power to at least a corresponding electronic module of the two or more electronic modules (par 32-35); and
two or more power deliver interfaces (charge controller, transistors, amplifiers, charger IC (par 24, 32-33, 55-57, 59, 64)), wherein a power delivery interface of the two or more power delivery interfaces corresponds to the battery, and the power delivery interface comprises an amplifier (par 33, 64) configured to receive an output of the battery and provide an amplified output to at least the corresponding electronic module.
(Claim 2) wherein the first electronic module comprises at least one of a first processor, a first memory, a first radio frequency circuit, or first a sensor circuit and the second electronic module comprises at least one of a second processor, a second memory, a second radio frequency circuit, or a second sensor circuit (par 32-33, 56, 62-64)
(Claim 10) , wherein the amplifier is a linear amplifier and comprises a power transistor configured to: receive the output of the battery at the source of the power transistor; and generate the amplified output at a drain of the power transistor (par 32-33, 64).
(claim 19) For voltage regulator, see par 56.
Claims 1-4, 9-10 and 12-20 are rejected under 35 U.S.C. 102(a) (1) being anticipated by the prior art of record Strong (US 2023/0198058)
Regarding claim 1, the prior art discloses:
A 3D-IC (par26) comprising:
a first electronic module (first one of memories, transistor logic devices, circuit elements, RF devices, sensors, processor, CPU, GPU, audio devices, LEDs (in par 28, 60, 62-65, 85 89-90, 100)) disposed on a substrate of the 3D-IC;
a first battery (first one of embedded batteries (abstract, par 1)) disposed on the first electronic module and electronically coupled to the first electronic module, wherein the first battery is configured to provide power to the first electronic module;
a second electronic module (second one of memories, transistor logic devices, circuit elements, RF devices, sensors, processor, CPU, GPU, audio devices, LEDs (in par 28, 60, 62-65, 85 89-90, 100)) disposed on the first battery; and
a second battery (second one of embedded batteries (abstract, par 1)) disposed on the second electronic module and electronically coupled to the second electronic module (second one of memories, transistor logic devices, circuit elements, RF devices, sensors, processor, CPU, GPU, audio devices, LEDs (in par 28, 60, 62-65, 85 89-90, 100)), wherein the second battery is configured to provide power to the second electronic module.
(Claim 2) wherein the first electronic module comprises at least one of a first processor, a first memory, a first radio frequency circuit, or first a sensor circuit and the second electronic module comprises at least one of a second processor, a second memory, a second radio frequency circuit, or a second sensor circuit par (28, 60, 62-65, 85, 89-90, 100)
(Claims 3-4) a plurality of TSV connections (par 85) configured to:
electronically couple the first electronic module with the second electronic module; and transfer data between the first electronic module and the second electronic module, wherein the plurality of TSV connections surround the first battery;
electronically couple the first electronic module with the second electronic module; and transfer data between the first electronic module and the second electronic module, wherein the first battery comprises a plurality of through holes and the plurality of TSV connections pass through the through holes of the first battery.
Claims 9-10 and 12-20 in groups 2-3 are rejected for the same reason based on the Application grounds of traverse above. For interposer, see par 78, 83-85. For amplifier and transistor, see par 60, 62-65, 67-68, 85.
Allowable Subject Matter
Claims 7-8, 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Correspondence Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL DINH whose telephone number is 571-272-1890. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s Supervisor, Jack Chiang can be reached on 571-272-7483. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PAUL DINH/Primary Examiner, Art Unit 2851
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