Attorney’s Docket Number: P202204938US01
Filing Date: 12/12/2023
Claimed Foreign Priority Date: none
Applicants: Anderson et al.
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the Election filed on 07/20/2026.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election of Group Invention I (directed to a semiconductor structure), in the reply filed on 07/20/2026, is acknowledged. Applicant indicated that claims 1-18 read on the elected Group Invention. The examiner agrees. Accordingly, pending in this application are claims 1-20, with claims 19-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim.
Furthermore, because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 11, and 13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen et al. (US2025/0364358).
Regarding Claim 1, Chen (see, e.g., Fig. 3 and Par. [0033]-[0034]) shows all aspects of the instant invention, including a semiconductor structure, comprising:
- a first layer comprising:
a thermal dummy transfer via (e.g., one of conductive materials 320) comprising a conductive material configured for thermally conducting heat that is not electrically active
an active via (e.g., one of conductive materials 320E) that is connected at respective ends to active metal lines (e.g., to a pair of active metal patterns 323E).
Regarding Claim 3, Chen (see, e.g., Fig. 3 and Par. [0033]-[0034]) shows that the first layer further comprises a metal fill line (e.g., one of dummy metal patterns 323T), and wherein the thermal dummy transfer via is located on the metal fill line.
Regarding Claim 11, Chen (see, e.g., Fig. 3 and Par. [0033]-[0034]) shows that the thermal dummy transfer via is located in at least one of a middle-of-line (MOL) processing region, a backside end-of-line (BEOL) processing region, a through device region, or a backside layer of the semiconductor structure (e.g., 320 is formed above the gate electrode 312 layer, thus in a BEOL layer).
Regarding Claim 13, Chen (see, e.g., Fig. 3 and Par. [0033]-[0034]) shows that the thermal dummy transfer via is placed in an available location of a selected area of the semiconductor structure, the selected area comprises one of an area of relatively low metal, or an area of relatively high power density from heat producing components (e.g., to remove heat generated in the SOI transistor channel region 309S during device operation).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 4-8 and 10 are rejected under 35 U.S.C. 102(a)(2) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Chen et al. (US2025/0364358).
Regarding Claim 4, Chen (see, e.g., Fig. 3 and Par. [0033]-[0034]) shows that the thermal dummy transfer via (e.g., 320) is spaced apart from the active lines (e.g., 323E) by a distance (e.g., non-zero lateral distance).
Furthermore, with regards to the distance being a predefined distance to optimize yield and parasitic capacitance resulting from the dummy thermal transfer via, note that a limitation in a claim with respect to the manner in which a claimed device is intended to function does not differentiate the claimed device from a prior-art device if the prior-art device teaches all structural limitations in the claims and the functional limitations are found to be inherent in the prior-art device. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See Hewlett-Packard Co. v. Bausch & Lomb Inc. and the related case law cited therein which makes it clear that it is the final product per se which must be determined in a device claim, and not the patentability of its functions (909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990)). As stated in Best, “where the claimed and prior art products are identical or substantially identical in structure or composition, a prima facie case of either anticipation or obviousness has been established”. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
Note that the applicant has burden of proof once the examiner establishes a sound basis for believing that the products of the applicant and the prior art are the same. See In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990).
In the instant case, Chen shows all structural aspects of the semiconductor device according to the claimed invention and is capable of performing the claimed function.
Regarding Claim 5, Chen (see, e.g., Fig. 3 and Par. [0033]-[0034]) shows that the first layer further comprises a plurality of metal fill lines (e.g., dummy metal patterns 323T), and wherein the thermal dummy transfer via is located on one metal fill line spaced apart from other metal fill lines by a distance (e.g., non-zero vertical distance).
Furthermore, with regards to the distance being a predefined distance to optimize yield and parasitic capacitance resulting from the dummy thermal transfer via, see comments stated above in Par. 15-17 with regards to Claim 4, which are considered repeated here.
Regarding Claim 6, Chen (see, e.g., Fig. 3 and Par. [0033]-[0034]) shows that the thermal dummy transfer via (e.g., 320) has a size (e.g., at least a size to satisfactorily perform as part of a heat sink for removing heat from the transistor).
Furthermore, with regards to the size being a selected size based on a target thermal transfer in the semiconductor structure, see comments stated above in Par. 15-17 with regards to Claim 4, which are considered repeated here.
Regarding Claim 7, Chen (see, e.g., Fig. 3 and Par. [0033]-[0034]) shows a number of thermal dummy transfer vias (e.g., 320) (e.g., at least a number to satisfactorily perform as part of a heat sink for removing heat from the transistor).
Furthermore, with regards to the number being a selected number of thermal dummy transfer vias based on a target thermal transfer in the semiconductor structure, see comments stated above in Par. 15-17 with regards to Claim 4, which are considered repeated here.
Regarding Claim 8, Chen (see, e.g., Figs. 2-3 and Par. [0033]-[0034]) shows that the thermal dummy transfer via has a shape (e.g., at least a number to satisfactorily perform as part of a heat sink for removing heat from the transistor).
Furthermore, with regards to the shape being a selected shape based on a target thermal transfer in the semiconductor structure, see comments stated above in Par. 15-17 with regards to Claim 4, which are considered repeated here.
Regarding Claim 10, and regarding the language referring to the process by which the thermal dummy transfer via is formed, i.e., using one of damascene via formation, it has been held by the courts that the patentability of a product does not depend on its method of production. “If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
Note that the applicant has a burden of proof once the examiner establishes a sound basis for believing that the products of the applicant and the prior art are the same. See In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed, Cir. 1990).
In the instant case, while Chen is silent about the process of forming the thermal dummy transfer via, it would have been readily apparent to one of skill in the semiconductor manufacturing art that said via could have been manufactured by one of these two techniques, as masked etching of conductive layers to define conductive features (i.e., subtractive etching process) or trench fill with conductive material (i.e., damascene process) are techniques that would be commonly known by the skilled artisan for forming vias, and applying a known method step for their conventional use would have been a common sense choice by one skilled in the semiconductor art. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Allowable Subject Matter
Claims 14-18 are allowed.
Claims 2, 9, and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional references cited disclose semiconductor structures having thermal via arrangements, and having some features similar to the instant inventions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul at (571) 270-5514. The examiner can normally be reached on Monday-Friday 9am-6pm EST (Eastern Standard Time), or by e-mail via younes.boulghassoul@uspto.gov. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814
