Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Abstract
The abstract is objected to because of the following informalities:
Applicant is reminded of the proper language and format for an abstract of the disclosure. The Abstract filed on 12/12/2023 is too short to describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details. The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. See MPEP 608.01(b).
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 38, 55, 60-62, 64, 66, 69-70 and 77 are rejected under 35 U.S.C. 102 (a)(1) and (a)(2) as being anticipated by Guiot (US 20230374701).
Regarding claim 38. Guiot discloses A method, comprising:
providing a monocrystalline silicon carbide substrate layer 10/11([0074]/[0085]: single crystal SiC) on a substrate 20 (Fig 4);
separating a portion 10’ of the monocrystalline silicon carbide substrate layer such that at least a portion 11 of the monocrystalline silicon carbide substrate layer remains on the substrate (Fig 5); and
providing a wide bandgap epitaxial layer 30 [0095] is on the monocrystalline silicon carbide substrate layer (Fig 7).
Regarding claim 55. Fig 12 of Guiot discloses A semiconductor device [0107]/[0108], comprising:
a polycrystalline silicon carbide substrate 40 [0100];
a wide bandgap epitaxial layer 30/50/60 [0104]/[0106]/[0107] on the polycrystalline silicon carbide substrate; and
wherein at least a portion of the wide bandgap epitaxial layer comprises a structure forming a part of a transistor or a diode ([0107]/[0108]: HEMT).
Regarding claim 60. Guiot discloses The semiconductor device of claim 55, wherein the wide bandgap epitaxial layer comprises a silicon carbide epitaxial layer 30 [0104].
Regarding claim 61. Guiot discloses The semiconductor device of claim 55, wherein the wide bandgap epitaxial layer comprises a Group III-nitride epitaxial layer 50/60 [0106]/[0107].
Regarding claim 62. Guiot discloses The semiconductor device of claim 55, wherein the wide bandgap epitaxial layer is attached to the polycrystalline silicon carbide substrate 40 [0100].
Regarding claim 64. Guiot discloses The semiconductor device of claim 55, wherein the wide bandgap epitaxial layer is directly on the polycrystalline silicon carbide substrate such that there are no intervening structures between the wide bandgap epitaxial layer and the polycrystalline silicon carbide substrate (Fig 12, [0100]: 30 is directly on 40).
Regarding claim 66. Guiot discloses The semiconductor device of claim 55, wherein the wide bandgap epitaxial layer has a thickness in a range of about 0.2 μm to about 200 μm [0101]/[0106].
Regarding claim 69. Guiot discloses The semiconductor device of claim 55, further comprising a monocrystalline silicon carbide substrate layer between the polycrystalline silicon carbide substrate and the wide bandgap epitaxial layer (Fig 12: monocrystalline silicon carbide 30 is between 50 and 40).
Regarding claim 70. Guiot discloses The semiconductor device of claim 69, wherein the monocrystalline silicon carbide substrate layer is a 4H silicon carbide layer [0073].
Regarding claim 77. Guiot discloses The semiconductor device of claim 55, wherein the semiconductor device is an HEMT [0108].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 56-57, 63, 65 and 74-75 are rejected under 35 U.S.C. 103 as being unpatentable over Guiot (US 20230374701) in view of Maekawa (US 20220157943).
Regarding claim 56. Guiot discloses The semiconductor device of claim 55. But Guiot does not disclose wherein the semiconductor device is a vertical power semiconductor device having a first contact on the wide bandgap epitaxial layer and a second contact on the polycrystalline silicon carbide substrate.
However, Fig 27 of Maekawa discloses the semiconductor device is a vertical power semiconductor device [0290] having a first contact 342 on the wide bandgap epitaxial layer 312 [0245] and a second contact 332 on the polycrystalline silicon carbide substrate [0195].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Guiot’s device to have the Maekawa’s device structure for the purpose of providing enhanced production costs through the use of larger, cheaper, and more robust engineered substrates while maintaining high-voltage operation, low on-resistance, and excellent thermal management.
Regarding claim 57. Guiot in view of Maekawa discloses The semiconductor device of claim 56, Maekawa discloses further comprising a gate contact ([0273]: “G” in 341) on the wide bandgap epitaxial layer (Fig 27).
Regarding claim 63. Guiot discloses The semiconductor device of claim 55, wherein the wide bandgap epitaxial layer is plasma bonded to the polycrystalline silicon carbide substrate.
However, Maekawa discloses the wide bandgap epitaxial layer is plasma bonded to the polycrystalline silicon carbide substrate 310 (Fig 25, [0239]: “a plasma activated bonding”).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Guiot’s device to have the Maekawa’s device structure for the purpose of providing enhanced cost reduction, improved thermal management for high-power devices, and enhanced surface hydrophilicity for stronger, more reliable wafer-level packaging.
Regarding claim 65. Guiot discloses The semiconductor device of claim 55. But Guiot does not explicitly disclose wherein the polycrystalline silicon carbide substrate has a thickness in a range of about 1 μm to about 1000 μm.
However, Maekawa discloses the polycrystalline silicon carbide substrate 310 has a thickness in a range of about 1 μm to about 1000 μm ([0214]: 200 - 500 μm).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Guiot’s device to have the Maekawa’s device structure for the purpose of providing enhanced thermal management, high mechanical stability to prevent wafer bowing during further epi-layer growth, and improved high-frequency/high-power performance with thick polycrystalline Silicon Carbide (SiC) substrates.
Regarding claim 74. Guiot discloses The semiconductor device of claim 55. But Guiot does not explicitly disclose wherein the semiconductor device is a MOSFET.
However, Maekawa discloses the semiconductor device is a MOSFET (Fig 27, [0262]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Guiot’s device to have the Maekawa’s device structure for the purpose of providing enhanced performance over traditional Silicon (Si) devices by enabling higher efficiency, faster switching frequencies, and greater power density.
Regarding claim 75. Guiot discloses The semiconductor device of claim 55. But Guiot does not explicitly disclose wherein the semiconductor device is a Schottky diode.
However, Maekawa discloses the semiconductor device is a Schottky diode [0236].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Guiot’s device to have the Maekawa’s device structure for the purpose of providing enhanced efficiency, high-speed switching, and enhanced thermal performance compared to silicon alternatives.
Claims 58-59 and 76 are rejected under 35 U.S.C. 103 as being unpatentable over Guiot (US 20230374701) in view of Shimoida (US 20060118818).
Regarding claim 58. Guiot discloses The semiconductor device of claim 55. But Guiot does not disclose wherein the semiconductor device is a lateral power semiconductor device having a first contact and a second contact on the wide bandgap epitaxial layer.
However, Fig 5 of Shimoida discloses wherein the semiconductor device is a lateral power semiconductor device [0037] having a first contact 108 and a second contact 118 on the wide bandgap epitaxial layer 101.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Guiot’s device to have the Shimoida’s device structure for the purpose of providing enhanced efficiency, higher switching speeds, and better thermal management compared to Silicon (Si) alternatives.
Regarding claim 59. Guiot in view of Shimoida discloses The semiconductor device of claim 58. Shimoida discloses further comprising a gate contact (Fig 5: ‘G’ on 107) on the wide bandgap epitaxial layer.
Regarding claim 76. Guiot discloses The semiconductor device of claim 55. But Guiot does not explicitly disclose wherein the semiconductor device is a JFET.
However, Fig 4A of Shimoida discloses the semiconductor device is a JFET [0034].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Guiot’s device to have the Shimoida’s device structure for the purpose of providing enhanced efficiency and power density due to extremely low on-resistance, faster switching speeds, and robust high-temperature operation. They eliminate gate oxide reliability issues found in MOSFETs, providing better radiation tolerance and high reliability in harsh environments.
Claim 68 is rejected under 35 U.S.C. 103 as being unpatentable over Guiot (US 20230374701) in view of Khlebnikov (US 20210230769).
Regarding claim 68. Guiot discloses The semiconductor device of claim 55. But Guiot does not explicitly disclose wherein the polycrystalline silicon carbide substrate comprises an unintentionally doped polycrystalline silicon carbide substrate.
However, Khlebnikov discloses the polycrystalline silicon carbide substrate [0059] comprises an unintentionally doped polycrystalline silicon carbide substrate [0060]: “may comprise N-type doping including unintentional dopants”).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Guiot’s device to have the Khlebnikov’s device structure for the purpose of providing ultra-low resistivity, high-temperature, and cost-effective handle wafer for high-power devices.
Conclusion
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/Changhyun Yi/Primary Examiner, Art Unit 2812