Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Amendment filed on 5/15/26 has been entered.
Response to Arguments
Applicant’s arguments with regard to the amendments have been fully considered but they are moot because the arguments do not apply to any of the references being used in the current rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 38 is rejected under 35 U.S.C. 102 (a)(1)/(a)(2) as being anticipated by Guiot (US 20230374701).
Regarding claim 38. Fig 9 – Fig 11 of Guiot disclose A method, comprising:
providing a monocrystalline silicon carbide substrate layer 11/30 ([0077]/[0095]: 11 and 30 are single crystal SiC) directly on a substrate 40 (Fig 9);
separating a portion (Fig 10, [0104]: 11 is removed) of the monocrystalline silicon carbide substrate layer such that at least a portion (Fig 10, [0104]: 30 remains) of the monocrystalline silicon carbide substrate layer remains directly on the substrate (Fig 10: 30 directly on 40); and
providing a wide bandgap epitaxial layer 50 ([0106]: AlGaN) is on the at least the portion of the monocrystalline silicon carbide substrate layer (Fig 11).
Claim 55, 57, 60, 62, 64, 69 and 74 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Ishibashi (US 20130092956).
Regarding claim 55. Fig 7 of Ishibashi discloses A semiconductor device [0107]/[0108], comprising:
a polycrystalline silicon carbide substrate 10 ([0068]: a substrate made of polycrystalline silicon carbide);
a first contact 112 [0105] on a first surface (back surface) of the polycrystalline silicon carbide substrate;
a wide bandgap epitaxial layer 11/1/120 ([0054],[0114]-[0115]: all layers are made of SiC) on the polycrystalline silicon carbide substrate;
a second contact 111/127 [0109] on the wide bandgap epitaxial layer; and
wherein at least a portion of the wide bandgap epitaxial layer comprises a structure ([0105]: gate contact 110 and [0116]: gate insulating film 126 forming a part of a transistor [0105] or a diode.
Regarding claim 57. (Currently Amended) Ishibashi discloses The semiconductor device of claim 55, further comprising a gate contact 110 [0105] on the wide bandgap epitaxial layer (Fig 7).
Regarding claim 60. Ishibashi discloses The semiconductor device of claim 55, wherein the wide bandgap epitaxial layer comprises a silicon carbide epitaxial layer 120 [0114]-[0115].
Regarding claim 62. Ishibashi discloses The semiconductor device of claim 55, wherein the wide bandgap epitaxial layer is attached to the polycrystalline silicon carbide substrate (Fig 7: because the SiC layer directly on 10).
Regarding claim 64. Ishibashi discloses The semiconductor device of claim 55, wherein the wide bandgap epitaxial layer is directly on the polycrystalline silicon carbide substrate such that there are no intervening structures between the wide bandgap epitaxial layer and the polycrystalline silicon carbide substrate (Fig 7: the SiC layers 11/1/120 directly on 10).
Regarding claim 69. Ishibashi discloses The semiconductor device of claim 55, further comprising a monocrystalline silicon carbide substrate layer 1 ([0106]: single crystal substrate) between the polycrystalline silicon carbide substrate and the wide bandgap epitaxial layer (Fig 7).
Regarding claim 74. Ishibashi discloses The semiconductor device of claim 55, wherein the semiconductor device is a MOSFET [0105].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 61 and 65-66 are rejected under 35 U.S.C. 103 as being unpatentable over Ishibashi (US 20130092956) in view of Oka (US 20260143812).
Regarding claim 61. Ishibashi discloses The semiconductor device of claim 55. But Ishibashi does not expressly disclose wherein the wide bandgap epitaxial layer comprises a Group III-nitride epitaxial layer.
However, Fig 2 of Oka discloses the wide bandgap epitaxial layer 14 comprises a Group III-nitride epitaxial layer ([0031]: AlN).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Ishibashi’s device structure to have the Oka’s III-Nitride epitaxial layer to provide close lattice match to both SiC and subsequent GaN epilayers, drastically reducing threading dislocations, defects, and structural strain.
Regarding claim 65. Ishibashi discloses The semiconductor device of claim 55. But Ishibashi does not expressly disclose wherein the polycrystalline silicon carbide substrate has a thickness in a range of about 1 µm to about 1000 µm.
However, Fig 2 of Oka discloses the polycrystalline silicon carbide substrate 12 has a thickness in a range of about 1 µm to about 1000 µm ([0045]: equal to 500 µm).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Ishibashi’s device to have the Oka’s structure for the purpose of providing enhanced thermal management, high mechanical stability to prevent wafer bowing during further epi-layer growth, and improved high-frequency/high-power performance with thick polycrystalline Silicon Carbide (SiC) substrates.
Regarding claim 66. Ishibashi discloses The semiconductor device of claim 55. But Ishibashi does not expressly disclose wherein the wide bandgap epitaxial layer has a thickness in a range of about 0.2 µm to about 200 µm.
However, Fig 2 of Oka discloses the wide bandgap epitaxial layer 14 has a thickness in a range of about 0.2 µm to about 200 µm ([0030]: equal to 1 μm).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Ishibashi’s device to have the Oka’s structure for the purpose of providing remarkably close lattice match to both SiC and subsequent GaN epilayers, drastically reducing threading dislocations, defects, and structural strain.
Claims 63 and 75 are rejected under 35 U.S.C. 103 as being unpatentable over Ishibashi (US 20130092956) in view of Maekawa (US 20220157943).
Regarding claim 63. Ishibashi discloses The semiconductor device of claim 55. But Ishibashi does not expressly disclose wherein the wide bandgap epitaxial layer is plasma bonded to the polycrystalline silicon carbide substrate.
However, Maekawa discloses the wide bandgap epitaxial layer is plasma bonded to the polycrystalline silicon carbide substrate 310 (Fig 25, [0239]: “a plasma activated bonding”).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Ishibashi’s device to have the Maekawa’s device structure for the purpose of providing enhanced cost reduction, improved thermal management for high-power devices, and enhanced surface hydrophilicity for stronger, more reliable wafer-level packaging.
Regarding claim 75. Ishibashi discloses The semiconductor device of claim 55. But Ishibashi does not explicitly disclose wherein the semiconductor device is a Schottky diode.
However, Maekawa discloses the semiconductor device is a Schottky diode [0236].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Ishibashi’s device to have the Maekawa’s device structure for the purpose of providing enhanced efficiency, high-speed switching, and enhanced thermal performance compared to silicon alternatives.
Claim 68 is rejected under 35 U.S.C. 103 as being unpatentable over Ishibashi (US 20130092956) in view of Khlebnikov (US 20210230769).
Regarding claim 68. Ishibashi discloses The semiconductor device of claim 55. But Ishibashi does not explicitly disclose wherein the polycrystalline silicon carbide substrate comprises an unintentionally doped polycrystalline silicon carbide substrate.
However, Khlebnikov discloses the polycrystalline silicon carbide substrate [0059] comprises an unintentionally doped polycrystalline silicon carbide substrate [0060]: “may comprise N-type doping including unintentional dopants”).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Ishibashi’s device to have the Khlebnikov’s device structure for the purpose of providing ultra-low resistivity, high-temperature, and cost-effective handle wafer for high-power devices.
Claim 70 is rejected under 35 U.S.C. 103 as being unpatentable over Ishibashi (US 20130092956).
Regarding claim 70. Ishibashi discloses The semiconductor device of claim 55. But Ishibashi does not explicitly disclose The semiconductor device of claim 69, wherein the monocrystalline silicon carbide substrate layer is a 4H silicon carbide layer.
However, Ishibashi teaches a silicon carbide semiconductor device including a monocrystalline silicon carbide substrate and a silicon carbide epitaxial layer formed on the front surface of the monocrystalline substrate. See, e.g., Fig. 7 and the corresponding description of the semiconductor device and the epitaxial growth process.
More specifically, Ishibashi teaches that the monocrystalline silicon carbide substrate preferably has a hexagonal crystal structure and that the substrate surface is oriented off the {0001} plane to permit satisfactory epitaxial growth, or alternatively off the {03-38} plane to improve channel mobility. Ishibashi further teaches growing silicon carbide epitaxial layers directly on the front surface of the monocrystalline silicon carbide substrate to form the active semiconductor device.
Although Ishibashi does not expressly identify the hexagonal silicon carbide substrate as 4H-SiC, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ 4H-SiC as the monocrystalline silicon carbide substrate. At the time of the invention, 4H-SiC was the conventional and industry-standard hexagonal SiC polytype for power semiconductor devices, including vertical MOSFETs, because of its superior electron mobility, favorable channel characteristics, and mature epitaxial growth technology. A person of ordinary skilled in the art would therefore have understood Ishibashi's disclosed monocrystalline hexagonal silicon carbide substrate for a vertical SiC power device to be implemented using the conventional 4H-SiC polytype absent any teaching suggesting the use of another polytype.
Accordingly, it would have been obvious to modify or implement Ishibashi's monocrystalline silicon carbide substrate as a 4H silicon carbide substrate, thereby arriving at the subject matter of claim 70. Selecting the conventional 4H polytype for Ishibashi's disclosed monocrystalline silicon carbide substrate would have been no more than the use of a known material for its known advantages, yielding the predictable result of a conventional 4H-SiC power semiconductor device.
Claim 76 is rejected under 35 U.S.C. 103 as being unpatentable over Ishibashi (US 20130092956) in view of Shimoida (US 20060118818).
Regarding claim 76. Ishibashi discloses The semiconductor device of claim 55. But Ishibashi does not explicitly disclose wherein the semiconductor device is a JFET.
However, Fig 4A of Shimoida discloses the semiconductor device is a JFET [0034].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Ishibashi’s device to have the Shimoida’s device structure for the purpose of providing enhanced efficiency and power density due to extremely low on-resistance, faster switching speeds, and robust high-temperature operation. They eliminate gate oxide reliability issues found in MOSFETs, providing better radiation tolerance and high reliability in harsh environments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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