Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/537,435 filed on April 29, 2026.
Information Disclosure Statement
3. Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Specification
4. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Power Semiconductor Devices Comprising Wide Bandgap Epitaxial Layer in Flip Chip Configuration”.
Election/Restrictions
5. Applicant’s election without traverse of claims 1,5,8-17, 20 w.r.t. species II (Fig. 4) in the reply filed on 04/29/2026 is acknowledged.
6. Claims 2-4, 6-7, 18 are withdrawn and claim 50 is cancelled from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/29/2026.
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
10. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or non-obviousness.
11. Claims 1, 5, 8-10, 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Dhar et al. (US 2012/0223330 A1) in view of SUNDARAMOORTHY et al. (US 2024/0222462 A1).
Regarding independent claim 1, Dhar et al. teaches a semiconductor device (26, Fig. 2), comprising:
a wide bandgap layer or substrate (28 made of SiC, para [0030] and considering as the wide bandgap material), the wide bandgap layer or substrate (28) comprising silicon carbide (SiC), the wide bandgap layer (28) having a first surface (upper surface) and an opposing second surface (bottom surface);
a first contact (36 source contact, para [0030]) on the first surface (upper surface) of the wide bandgap layer (28); and
wherein the second surface (bottom surface) is not in direct or indirect contact with a silicon carbide substrate (no additional SiC substrate or layer added to the 28).
Dhar et al. is explicitly silent of disclosing wherein, the wide bandgap layer or substrate comprising an epitaxial layer.
SUNDARAMOORTHY et al. teaches wherein (Fig. 1), the wide bandgap semiconductor material (2, para [0045]) made of epitaxial layer or epilayer (para [0045], [0048]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by SUNDARAMOORTHY et al. while forming the wide bandgap material, such as silicon carbide of Dhar et al., by applying epitaxy process or CVD, in order to obtain uniform growth or doping profiles that enhance ohmic contacts, low resistance and minimize energy loses.
Regarding claim 5, Dhar et al. and SUNDARAMOORTHY et al. teach all of the limitations of claim 1 from which this claim depends.
Dhar et al. teaches wherein (Fig. 2), the semiconductor device (26) comprises a second contact (38 drain contact, para [0030]) on the first surface (upper surface) of the wide bandgap layer (28) such that the semiconductor device is a lateral power semiconductor device.
Regarding claim 8, Dhar et al. and SUNDARAMOORTHY et al. teach all of the limitations of claim 5 from which this claim depends.
Dhar et al. teaches wherein (Fig. 2), the wide bandgap layer (28) is not in contact with any semiconductor substrate (no additional substrate added to the SiC layer 28).
Regarding claim 9, Dhar et al. and SUNDARAMOORTHY et al. teach all of the limitations of claim 5 from which this claim depends.
Dhar et al. teaches wherein (Fig. 2), further comprising a gate contact (40 gate contact, para [0030]) on the first surface (upper surface) of the wide bandgap layer (28) between the first contact (36) and the second contact (38).
Regarding claim 10, Dhar et al. and SUNDARAMOORTHY et al. teach all of the limitations of claim 5 from which this claim depends.
Dhar et al. teaches wherein (Fig. 2), further comprising an underfill material (34 oxide) on at least a portion of the wide bandgap layer (28) between the first contact (36) and the second contact (38).
Regarding claim 13, Dhar et al. and SUNDARAMOORTHY et al. teach all of the limitations of claim 1 from which this claim depends.
Dhar et al. teaches wherein (Fig. 2), the wide bandgap layer (28) comprises one or more doped regions (30, 32).
Regarding claim 14, Dhar et al. and SUNDARAMOORTHY et al. teach all of the limitations of claim 1 from which this claim depends.
Dhar et al. teaches wherein (Fig. 2), a certain thickness (vertical height) of the wide bandgap epitaxial layer (28) is seen from the figure 2.
However, Dhar et al. is explicitly silent of disclosing wherein, the wide bandgap epitaxial layer (28) has a thickness in a range of about 0.2 µm to about 200 µm. It would have been obvious to select intended ‘thickness of the wide bandgap layer’ to be within the quoted range of is range of about 0.2 µm to about 200 µm, to obtain uniform growth layer for device performance. In addition, to an ordinary artisan practicing the invention, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F. 2d 454, 105 USPQ 233, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed thickness or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen thickness or upon another variable recited in a claim, the Applicant must show that the chosen thickness is critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 15, Dhar et al. and SUNDARAMOORTHY et al. teach all of the limitations of claim 1 from which this claim depends.
Dhar et al. teaches wherein (Fig. 2), the second surface provides at least a portion of a thermal path for dissipation of heat from the wide bandgap epitaxial layer (this is a functional limitation/an intended use), wherein the thermal path does not include a silicon carbide substrate (no additional SiC substrate or layer added to layer 28).
Regarding claim 16, Dhar et al. and SUNDARAMOORTHY et al. teach all of the limitations of claim 1 from which this claim depends.
Dhar et al. teaches wherein (Fig. 2), the semiconductor device (26) comprises a Schottky diode or MOSFET (para [0029]).
12. Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Dhar et al. (US 2012/0223330 A1) in view of SUNDARAMOORTHY et al. (US 2024/0222462 A1) as applied to claim 1 above, and further in view of Lee et al. (US 2024/0063109 A1).
Regarding claim 11, Dhar et al. and SUNDARAMOORTHY et al. teach all of the limitations of claim 1 from which this claim depends.
Dhar et al. and SUNDARAMOORTHY et al. are explicitly silent of disclosing wherein, the wide bandgap epitaxial layer is mounted in a flip chip configuration in a semiconductor device package.
Lee et al. teaches wherein (Fig. 1), the MOSFET (30, para [0032], [0035]) is mounted in a flip chip configuration in a semiconductor device package (PK1, para [0026]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Lee et al. and attach the structure of Dhar et al. and SUNDARAMOORTHY et al., to the wiring substrate WS-1 in a flip chip configuration, in order to reduce electrical paths, higher connection densities and produce compact package size.
Regarding claim 12, Dhar et al. and SUNDARAMOORTHY et al. and Lee et al. teach all of the limitations of claim 11 from which this claim depends.
Dhar et al. and SUNDARAMOORTHY et al. are explicitly silent of disclosing wherein, the wide bandgap epitaxial layer directly contacts an insulating material of the semiconductor device package.
Lee et al. teaches wherein (Fig. 1), the MOSFET (30) directly contacts an insulating material (36 molding layer, para [0038]) of the semiconductor device package (PK1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Lee et al. and apply the molding material to the structure of Dhar et al. and SUNDARAMOORTHY et al., in order to protect/housing the flip chip configuration of the semiconductor device.
13. Claims 17, 30 are rejected under 35 U.S.C. 103 as being unpatentable over Dhar et al. (US 2012/0223330 A1) in view of SUNDARAMOORTHY et al. (US 2024/0222462 A1), and further in view of Lee et al. (US 2024/0063109 A1).
Regarding independent claim 17, Dhar et al. teaches a semiconductor device (26, Fig. 2), comprising:
a wide bandgap layer (28 made of SiC, para [0030] and considering as the wide bandgap material), the wide bandgap layer (28) having a first surface (upper surface) and an opposing second surface (bottom surface);
a first contact (36 source contact, para [0030]) on the first surface of the wide bandgap layer (28), and
wherein the second surface of the wide bandgap layer (28) provides at least a portion of a thermal path configured to dissipate heat from the wide bandgap epitaxial layer (this is a functional limitation/an intended use), wherein the thermal path does not include a semiconductor substrate (no additional substrate or layer added to the 28, see Fig. 2).
Dhar et al. is explicitly silent of disclosing wherein, the wide bandgap layer or substrate comprising an epitaxial layer.
SUNDARAMOORTHY et al. teaches wherein (Fig. 1), the wide bandgap semiconductor material (2, para [0045]) made of epitaxial layer or epilayer (para [0045], [0048]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by SUNDARAMOORTHY et al. while forming the wide bandgap material, such as silicon carbide of Dhar et al., by applying epitaxy process or CVD, in order to obtain uniform growth or doping profiles that enhance ohmic contacts, low resistance and minimize energy loses.
Dhar et al. and SUNDARAMOORTHY et al. are explicitly silent of disclosing wherein, the first surface of the wide bandgap epitaxial layer is mounted in a flip chip configuration on a submount.
Lee et al. teaches wherein (Fig. 1), the MOSFET (30, para [0032], [0035]) is mounted in a flip chip configuration in a semiconductor device package (PK1, para [0026]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Lee et al. and attach the structure of Dhar et al. and SUNDARAMOORTHY et al., to the wiring substrate WS-1 in a flip chip configuration, in order to reduce electrical paths, higher connection densities and produce compact package size.
Regarding claim 30, Dhar et al. and SUNDARAMOORTHY et al. and Lee et al. teach all of the limitations of claim 17 from which this claim depends.
Dhar et al. and SUNDARAMOORTHY et al. are explicitly silent of disclosing wherein, an insulating material of a semiconductor package is directly on the second surface of the wide bandgap epitaxial layer.
Lee et al. teaches wherein (Fig. 1), an insulating material (36 molding layer, para [0038]) of a semiconductor package (PK1) is directly on the second surface of the wide bandgap layer.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Lee et al. and apply the molding material to the structure of Dhar et al. and SUNDARAMOORTHY et al., in order to protect/housing the flip chip configuration of the semiconductor device.
Examiner’s Note
14. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
15. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
16. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812
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