DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12/13/2023 and 04/09/2024 were filed before the first action on the merits. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4 and 6-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Letz et al. (2010/0248463).
Re claim 1, Letz teaches a method for manufacturing a semiconductor structure (Figs. 1a-o), comprising: providing a wafer structure (100) having a normal region (104) and a trimmed region adjacent (103) to the normal region (104), wherein a top surface of the trimmed region (103) is lower than a top surface of the normal region (Fig. 1b); forming a dielectric layer (141) and a conductive layer (121S) on the wafer structure (100) in the normal region (104) and the trimmed region (103); forming a protective layer (142) on a portion of the dielectric layer (141) in the trimmed region (103) and a portion of the conductive layer (121S) in the trimmed region (103); and forming another dielectric layer (151) on a portion of the dielectric layer (141) in the normal region (104) and a portion of the conductive layer in the normal region (110) and on the protective layer (130).
Re claim 4, Letz teaches the method according to claim 1, wherein the trimmed region surrounds the normal region (Fig. 1o).
Re claim 6, Letz teaches the method according to claim 1, wherein forming the protective layer comprises: forming the protective layer (142) on the wafer structure (100) in the normal region (104) and the trimmed region (103); and removing a portion of the protective layer in the normal region [42-43].
Re claim 7, Letz teaches the method according to claim 1, wherein the protective layer (141) is formed of oxide [42].
Re claim 8, Letz teaches the method according to claim 7, wherein the protective layer (141) is formed to have a thickness such that a top surface of the protective layer (141) remained in the trimmed region (103) is lower than a top surface of the portion of the dielectric layer in the normal region (104) and the portion of the conductive layer in the normal region by 20 µm or less [34].
Allowable Subject Matter
Claims 2-3 and 5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re claim 2, Letz teaches the method according to claim 1, yet remains explicitly silent to wherein providing the wafer structure comprises: forming a barrier oxide layer on a device wafer; forming a device layer on the barrier oxide layer; bonding the device wafer with the barrier oxide layer and the device layer to a handle wafer, wherein the device layer faces the handle wafer; and removing the device wafer.
Clam 3 is objected to for at least depending from objected claim 2.
Re claim 5, Letz teaches the method according to claim 1, yet remains explicitly silent to wherein forming the dielectric layer and the conductive layer comprises: forming the dielectric layer on the wafer structure; forming openings in the dielectric layer; forming the conductive layer on the dielectric layer and filling into the openings; and conducting a planarization process to the conductive layer such that the portion of the conductive layer in the normal region is flush with the portion of the dielectric layer in the normal region.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S BOWEN whose telephone number is (571)272-3984. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/ADAM S BOWEN/Examiner, Art Unit 2897