Prosecution Insights
Last updated: July 17, 2026
Application No. 18/538,036

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Non-Final OA §102
Filed
Dec 13, 2023
Examiner
HO, ANTHONY
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
1043 granted / 1147 resolved
+22.9% vs TC avg
Minimal +2% lift
Without
With
+2.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
22 currently pending
Career history
1166
Total Applications
across all art units

Statute-Specific Performance

§101
1.9%
-38.1% vs TC avg
§103
51.8%
+11.8% vs TC avg
§102
23.1%
-16.9% vs TC avg
§112
10.7%
-29.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1147 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group II, claims 17-36, in the reply filed on March 23, 2026 is acknowledged. Information Disclosure Statement The information disclosure statement (IDS) submitted on September 5, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 17, 28, 29, 34, and 35 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Young et al (US Pub 2021/0226066). In re claim 17, Young et al discloses a manufacturing method for a semiconductor device, comprising: forming a first active structure on a substrate (i.e. 100), wherein the first active structure comprises a plurality of first active channel sheets (i.e. 116) and a plurality of first metal gate structures (i.e. 154) vertically stacked to each other (i.e. see at least Figure 23); forming a plurality of first inner spacers (i.e. 232), wherein each of the first inner spacers is formed on a lateral surface of a corresponding first metal gate structure of the first metal gate structures (i.e. see at least Figure 23); forming a first helmet (i.e. 144) above the first inner spacers; and forming a conductive portion (i.e. 140) to be connected with a topmost first active channel sheet of the first active channel sheets, wherein the first helmet covers a lateral surface of the conductive portion (i.e. see at least Figure 23). In re claim 28, Young et al discloses a manufacturing method for a semiconductor device, comprising: forming a first active structure on a substrate (i.e. 100), wherein the first active structure comprises a plurality of first active channel sheets (i.e. 116) and a plurality of first metal gate structures (i.e. 154) vertically stacked to each other; forming a plurality of first inner spacers (i.e. 232), wherein each of the first inner spacers is formed on a lateral surface of a corresponding first metal gate structure of the first metal gate structures (i.e. see at least Figure 23); forming a first helmet (i.e. 144) above a topmost first inner spacer of the first inner spacers and a topmost first metal gate structure of the first metal gate structures (i.e. see at least Figure 23). In re claim 29, Young et al discloses further comprising: forming a conductive portion (i.e. 140) to be connected with a topmost first active channel sheet of the first active channel sheets, wherein the first helmet covers a lateral surface of the conductive portion (i.e. see at least Figure 23). In re claim 34, Young et al discloses a manufacturing method for a semiconductor device, comprising: forming a first active structure on a substrate (i.e. 100), wherein the first active structure comprises a plurality of first active channel sheets (i.e. 116) and a plurality of first metal gate structures (i.e. 154) vertically stacked to each other (i.e. see at least Figure 23); forming a plurality of first inner spacers (i.e. 232), wherein each of the first inner spacers is formed on a lateral surface of a corresponding first metal gate structure of the first metal gate structures (i.e. see at least Figure 23); forming a first helmet (i.e. 144) above a topmost first inner spacer of the first inner spacers and a topmost first metal gate structure of the first metal gate structures (i.e. see at least Figure 23), wherein the first inner spacers are formed of a material the same as that of the first helmet (i.e. in this case, both the inner spacers and the first helmet are made of dielectric material – see at least paragraphs 0038 and 0042). In re claim 35, Young et al discloses comprising: forming a conductive portion (i.e. 140) to be connected with a topmost first active channel sheet of the first active channel sheets, wherein the first helmet covers a lateral surface of the conductive portion (i.e. see at least Figure 23). Allowable Subject Matter Claims 18-27, 30-33, and 36 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. a. Wei et al (US Patent 12,148,751) b. Lan et al (US Pub 2025/0132217) Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY HO whose telephone number is (571)270-1432. The examiner can normally be reached 9AM - 5PM, Monday-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANTHONY HO/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Dec 13, 2023
Application Filed
May 29, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12681215
SILICON-CONTAINING COMPOUNDS FOR FORMING A PATTERNING COATING AND DEVICES INCORPORATING SAME
3y 2m to grant Granted Jul 14, 2026
Patent 12685005
FLEXIBLE SUBSTRATE, METHOD OF MANUFACTURING THEREOF, AND DISPLAY PANEL
2y 6m to grant Granted Jul 14, 2026
Patent 12685198
SEMICONDUCTOR CHIPLET DEVICE AND INTERPOSER
2y 3m to grant Granted Jul 14, 2026
Patent 12672416
DISPLAY DEVICE AND LIGHT EMITTING ELEMENT
2y 6m to grant Granted Jun 30, 2026
Patent 12666801
DEVICE
3y 3m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
93%
With Interview (+2.4%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1147 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month