DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This OA is in response to the amendment filled on 12/11/2025 that has been entered, wherein claims 1-20 are pending.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 10 and 19 recites the limitation "the distinct metal lines lack interconnection by any second metallization layer metal plate" in lines 11, 8 and 7, respectively. It is unclear if semiconductor device/system contains a second metallization layer metal plate? Is there a second metallization layer metal plate that is not connected to the distinct metal lines? Or are there no second metallization layer metal plate at all? For the purpose of examination, the limitation of "the distinct metal lines lack interconnection by any second metallization layer metal plate" will be interpreted as “the distinct metal lines lack interconnection by the second metallization layer”.
Claims 2-9, 11-18 and 20 depend on claims 1, 10 and 19 and inherit their deficiencies.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 3-11 and 13-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4, 6, 9, 17-20 of U.S. Patent No. 10,734,330 in view of Chang (US 2012/0043595 A1) as cited in the IDS of 12/13/2023.
Regarding claim 1, Claim 1 of US Patent No. 10,734,330 recites a semiconductor device comprising:
a substrate having an active region that includes opposite first and second edges;
a first metallization layer including a plurality of first metal lines that extend toward the second edge, a first metal plate that interconnects the first metal lines,
a plurality of second metal lines that extend toward the first edge, and
a second metal plate that interconnects the second metal lines, and
a second metallization layer including a plurality of distinct metal lines, at least one of which is substantially parallel to the first and second metal lines.
Claim 1 of US Patent No. 10,734,330 does not recite a centerline substantially parallel to the first and second edges; wherein at least one of the first and second metal lines extends through the centerline; a plurality of distinct metal lines, at least one of which is substantially parallel to the first and second metal lines, wherein the distinct metal lines lack interconnection by the second metallization layer.
Chang teaches a semiconductor device(Figs. 1-3) comprising:
a centerline(A-A’) substantially parallel to the first and second edges; wherein at least one of the first and first metal lines(150a, 150c, ¶0103) extends through the centerline(A-A’) ; and a plurality of distinct metal lines(G1, G2, ¶0101), at least one of which is substantially parallel to the first and first metal lines(150a, 150c, ¶0103), wherein the distinct metal lines(G1, G2, ¶0101) lack interconnection by the second metallization layer(126, ¶0130). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Claim 1 of US Patent No. 10, 734,330, to include a centerline substantially parallel to the first and second edges; wherein at least one of the first and second metal lines extends through the centerline; a plurality of distinct metal lines, at least one of which is substantially parallel to the first and second metal lines, wherein the distinct metal lines lack interconnection by the second metallization layer, as taught by Chang, in order a relatively large capacitance in the same area without having to use additional capacitors and without using a high-k dielectric material to form a gate insulation layer (in contrast to a general capacitor device), thereby increasing efficiency and integration and lowering costs(¶0124).
Regarding claim 3, Claim 2 of US Patent No. 10,734,330 recites the semiconductor device of claim 1, wherein the first metal lines and the first metal plate are integral with each other.
Regarding claim 4, Claim 1 of US Patent No. 10,734,330 recites the semiconductor device of claim 1, further comprising a third metallization layer between the first and second metallization layers and including
a plurality of metal lines, and
a metal plate that interconnects the metal lines and that has a different size than at least one of the first and second metal plates.
Regarding claim 5, Claim 4 of US Patent No. 10,734,330 recites the semiconductor device of claim 1, further comprising an electronic component in the active region.
Regarding claim 6, Claim 6 of US Patent No. 10,734,330 recites the semiconductor device of claim 1, further comprising a diode in the active region, wherein the diode has an anode coupled to a first metal line of the plurality of first metal lines and a cathode coupled to a second metal line of the plurality of second metal lines.
Regarding claim 7, Claim 3 of US Patent No. 10,734,330 recites the semiconductor device of claim 1, wherein at least one of the first and second metal plates is inside the active region.
Regarding claim 8, Claim 1 of US Patent No. 10,734,330 recites the semiconductor device of claim 1, wherein at least one of the first and second metal plates is outside the active region.
Regarding claim 9, Claim 1 of US Patent No. 10,734,330 recites the semiconductor device of claim 1, wherein at least one of the first and second metal plates is outside of the active region.
Claim 1 of US Patent No. 10,734,330 does not recite at least one of the first and second metal plates is inside of the active region.
Claim 3 of US Patent No. 10,734,330 recites at least one of the first and second metal plates is inside of the active region. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the combination of claims 1 and 3 of U.S. Patent No. 10,734,330 in view of Tsai recite claim 9 of the instant case.
Regarding claim 10, Claim 17 of US Patent No. 10,734,330 recites a system comprising:
a substrate having an active region that includes opposite first and second edges;
an electronic component in the active region;
a first metallization layer including a plurality of interconnected metal lines; and
a second metallization layer between the substrate and the first metallization layer and including a plurality of distinct metal lines, at least one of which extends through the centerline and is substantially parallel to the interconnected metal lines.
Claim 17 of US Patent No. 10,734,330 does not recite a centerline substantially parallel to the first and second edges; a plurality of distinct metal lines, at least one of which extends through the centerline and is substantially parallel to the interconnected metal lines, wherein the distinct metal lines lack interconnection by the second metallization layer.
Chang teaches a semiconductor device(Figs. 1-3) comprising:
a centerline(A-A’) substantially parallel to the first and second edges; wherein at least one of the first and first metal lines(150a, 150c, ¶0103) extends through the centerline(A-A’) ; and a plurality of distinct metal lines(G1, G2, ¶0101), at least one of which is substantially parallel to the interconnected metal lines(150a, 150c, ¶0103), wherein the distinct metal lines(G1, G2, ¶0101) lack interconnection by the second metallization layer(126, ¶0130). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Claim 17 of US Patent No. 10, 734,330, to include a centerline substantially parallel to the first and second edges; wherein at least one of the first and second metal lines extends through the centerline; a plurality of distinct metal lines, at least one of which is substantially parallel to the first and second metal lines, wherein the distinct metal lines lack interconnection by the second metallization layer, as taught by Chang, in order a relatively large capacitance in the same area without having to use additional capacitors and without using a high-k dielectric material to form a gate insulation layer (in contrast to a general capacitor device), thereby increasing efficiency and integration and lowering costs(¶0124).
Regarding claim 11, Claim 17 of US Patent No. 10,734,330 recites the system of claim 10, wherein the plurality of interconnected metal lines include:
first metal lines that extend toward the second edge;
a first metal plate that interconnects the first metal lines;
second metal lines that extend toward the first edge; and
a second metal plate that interconnects the second metal lines.
Regarding claim 13, Claim 19 of US Patent No. 10,734,330 recites the system of claim 11, wherein the first metal lines and the first metal plate are integral with each other.
Regarding claim 14, Claim 17 of US Patent No. 10,734,330 recites the system of claim 11, further comprising a third metallization layer between the first and second metallization layers and including:
third metal lines; and
a third metal plate that interconnects the third metal lines and that has a different size than at least one of the first and second metal plates.
Regarding claim 15, Claim 18 of US Patent No. 10,734,330 recites the system of claim 11, further comprising a diode in the active region, wherein the diode has an anode coupled to a first metal line of the plurality of first metal lines and a cathode coupled to a second metal line of the plurality of second metal lines.
Regarding claim 16, Claim 17 of US Patent No. 10,734,330 recites the system of claim 11, wherein at least one of the first and second metal plates is inside the active region.
Regarding claim 17, Claim 17 of US Patent No. 10,734,330 recites the system of claim 11, wherein at least one of the first and second metal plates is outside the active region.
Regarding claim 18, Claim 20 of US Patent No. 10,734,330 recites the system of claim 11, wherein at least one of the first and second metal plates is inside and outside of the active region.
Regarding claim 19, Claim 9 of US Patent No. 10,734,330 recites a semiconductor device comprising:
a substrate having an active region that includes opposite first and second edges;
a first metallization layer including a plurality of interconnected metal lines; and
a second metallization layer between the substrate and the first metallization layer and including a plurality of distinct metal lines, at least one of which extends through the centerline and is substantially parallel to the interconnected metal lines.
Claim 9 of US Patent No. 10,734,330 does not recite a centerline substantially parallel to the first and second edges and a plurality of distinct metal lines, at least one of which extends through the centerline and is substantially parallel to the interconnected metal lines, wherein the distinct metal lines lack interconnection by the second metallization layer.
Chang teaches a semiconductor device(Figs. 1-3) comprising:
a centerline(A-A’) substantially parallel to the first and second edges; wherein at least one of the first and first metal lines(150a, 150c, ¶0103) extends through the centerline(A-A’) ; and a plurality of distinct metal lines(G1, G2, ¶0101), at least one of which is substantially parallel to the interconnected metal lines(150a, 150c, ¶0103), wherein the distinct metal lines(G1, G2, ¶0101) lack interconnection by the second metallization layer(126, ¶0130). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Claim 9 of US Patent No. 10, 734,330, to include a centerline substantially parallel to the first and second edges; wherein at least one of the first and second metal lines extends through the centerline; a plurality of distinct metal lines, at least one of which is substantially parallel to the first and second metal lines, wherein the distinct metal lines lack interconnection by the second metallization layer, as taught by Chang, in order a relatively large capacitance in the same area without having to use additional capacitors and without using a high-k dielectric material to form a gate insulation layer (in contrast to a general capacitor device), thereby increasing efficiency and integration and lowering costs(¶0124).
Regarding claim 20, Claim 9 of US Patent No. 10,734,330 recites the semiconductor device of claim 19, wherein the plurality of interconnected metal lines include:
first metal lines that extend toward the second edge;
a first metal plate that interconnects the first metal lines;
second metal lines that extend toward the first edge; and
a second metal plate that interconnects the second metal lines.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,848,286 in view of Chang (US 2012/0043595 A1) as cited in the IDS of 12/13/2023.
Regarding claim 1, Claim 1 of US Patent No. 11,848,286 recites a semiconductor device comprising:
a substrate having an active region that includes opposite first and second edges and a centerline substantially parallel to the first and second edges;
a first metallization layer including a plurality of first metal lines that extend toward the second edge, a first metal plate that interconnects the first metal lines,
a plurality of second metal lines that extend toward the first edge, and
a second metal plate that interconnects the second metal lines, wherein at least one of the first and second metal lines extends through the centerline; and
a second metallization layer including a plurality of distinct metal lines.
Claim 1 of US Patent No. 11,848,286 does not recite a plurality of distinct metal lines, at least one of which is substantially parallel to the first and second metal lines, wherein the distinct metal lines lack interconnection by the second metallization layer.
Chang teaches a semiconductor device(Figs. 1-3) comprising:
a plurality of distinct metal lines(G1, G2, ¶0101), at least one of which is substantially parallel to the first and second metal lines(150a, 150c, ¶0103), wherein the distinct metal lines(G1, G2, ¶0101) lack interconnection by the second metallization layer(126, ¶0130). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Claim 1 of US Patent No. 11,848,286, to include a centerline substantially parallel to the first and second edges; wherein at least one of the first and second metal lines extends through the centerline; a plurality of distinct metal lines, at least one of which is substantially parallel to the first and second metal lines, wherein the distinct metal lines lack interconnection by the second metallization layer, as taught by Chang, in order a relatively large capacitance in the same area without having to use additional capacitors and without using a high-k dielectric material to form a gate insulation layer (in contrast to a general capacitor device), thereby increasing efficiency and integration and lowering costs(¶0124).
Regarding claim 2, Claim 2 of US Patent No. 11,848,286 recites the semiconductor device of claim 1, wherein the first metal lines and the first metal plate have substantially the same thickness.
Regarding claim 3, Claim 3 of US Patent No. 11,848,286 recites the semiconductor device of claim 1, wherein the first metal lines and the first metal plate are integral with each other.
Regarding claim 4, Claim 4 of US Patent No. 11,848,286 recites the semiconductor device of claim 1, further comprising a third metallization layer between the first and second metallization layers and including
a plurality of metal lines, and
a metal plate that interconnects the metal lines and that has a different size than at least one of the first and second metal plates.
Regarding claim 5, Claim 5 of US Patent No. 11,848,286 recites the semiconductor device of claim 1, further comprising an electronic component in the active region.
Regarding claim 6, Claim 6 of US Patent No. 11,848,286 recites the semiconductor device of claim 1, further comprising a diode in the active region, wherein the diode has an anode coupled to a first metal line of the plurality of first metal lines and a cathode coupled to a second metal line of the plurality of second metal lines.
Regarding claim 7, Claim 8 of US Patent No. 11,848,286 recites the semiconductor device of claim 1, wherein at least one of the first and second metal plates is inside the active region.
Regarding claim 8, Claim 7 of US Patent No. 11,848,286 recites the semiconductor device of claim 1, wherein at least one of the first and second metal plates is outside the active region.
Regarding claim 9, Claim 9 of US Patent No. 11,848,286 recites the semiconductor device of claim 1, wherein at least one of the first and second metal plates is inside and outside of the active region.
Regarding claim 10, Claim 10 of US Patent No. 11,848,286 recites a system comprising:
a substrate having an active region that includes opposite first and second edges and a centerline substantially parallel to the first and second edges;
an electronic component in the active region;
a first metallization layer including a plurality of metal lines; and
a second metallization layer between the substrate and the first metallization layer and including a plurality of distinct metal lines.
Claim 10 of US Patent No. 11,848,286 does not recite a first metallization layer including a plurality of interconnected metal lines, a plurality of distinct metal lines, at least one of which extends through the centerline and is substantially parallel to the interconnected metal lines.
Claim 11 of US Patent No. 11,848,286 recites a first metallization layer including a plurality of interconnected metal lines. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the combination of claims 10 and 11 of U.S. Patent No. 11,848,286 recite claim 10 of the instant case.
Claim 10 and 11 of US Patent No. 11,848,286 does not recite a plurality of distinct metal lines, at least one of which extends through the centerline and is substantially parallel to the interconnected metal lines, wherein the distinct metal lines lack interconnection by the second metallization layer.
Chang teaches a semiconductor device(Figs. 1-3) comprising:
a plurality of distinct metal lines(G1, G2, ¶0101), at least one of which is substantially parallel to the first and second metal lines(150a, 150c, ¶0103), wherein the distinct metal lines(G1, G2, ¶0101) lack interconnection by the second metallization layer(126, ¶0130). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Claims 10 and 11 of US Patent No. 11,848,286, to include a plurality of distinct metal lines, at least one of which extends through the centerline and is substantially parallel to the interconnected metal lines, wherein the distinct metal lines lack interconnection by the second metallization layer, as taught by Chang, in order a relatively large capacitance in the same area without having to use additional capacitors and without using a high-k dielectric material to form a gate insulation layer (in contrast to a general capacitor device), thereby increasing efficiency and integration and lowering costs(¶0124).
Regarding claim 11, Claim 11 of US Patent No. 11,848,286 recites the system of claim 10, wherein the plurality of interconnected metal lines include:
first metal lines that extend toward the second edge;
a first metal plate that interconnects the first metal lines;
second metal lines that extend toward the first edge; and
a second metal plate that interconnects the second metal lines.
Regarding claim 12, Claim 12 of US Patent No. 11,848,286 recites the system of claim 11, wherein the first metal lines and the first metal plate have substantially the same thickness.
Regarding claim 13, Claim 13 of US Patent No. 11,848,286 recites the system of claim 11, wherein the first metal lines and the first metal plate are integral with each other.
Regarding claim 14, Claim 14 of US Patent No. 11,848,286 recites the system of claim 11, further comprising a third metallization layer between the first and second metallization layers and including:
third metal lines; and
a third metal plate that interconnects the third metal lines and that has a different size than at least one of the first and second metal plates.
Regarding claim 15, Claim 15 of US Patent No. 11,848,286 recites the system of claim 11, further comprising a diode in the active region, wherein the diode has an anode coupled to a first metal line of the plurality of first metal lines and a cathode coupled to a second metal line of the plurality of second metal lines.
Regarding claim 16, Claim 17 of US Patent No. 11,848,286 recites the system of claim 11, wherein at least one of the first and second metal plates is inside the active region.
Regarding claim 17, Claim 16 of US Patent No. 11,848,286 recites the system of claim 11, wherein at least one of the first and second metal plates is outside the active region.
Regarding claim 18, Claim 18 of US Patent No. 11,848,286 recites the system of claim 11, wherein at least one of the first and second metal plates is inside and outside of the active region.
Regarding claim 19, Claim 19 of US Patent No. 11,848,286 recites a semiconductor device comprising:
a substrate having an active region that includes opposite first and second edges and a centerline substantially parallel to the first and second edges;
a first metallization layer including a plurality of interconnected metal lines; and
a second metallization layer between the substrate and the first metallization layer and including a plurality of distinct metal lines.
Claim 19 of US Patent No. 11,848,286 does not recite a plurality of distinct metal lines, at least one of which extends through the centerline and is substantially parallel to the interconnected metal lines, wherein the distinct metal lines lack interconnection by the second metallization layer.
Chang teaches a semiconductor device(Figs. 1-3) comprising:
a plurality of distinct metal lines(G1, G2, ¶0101), at least one of which is substantially parallel to the first and second metal lines(150a, 150c, ¶0103), wherein the distinct metal lines(G1, G2, ¶0101) lack interconnection by the second metallization layer(126, ¶0130). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Claim 19 of US Patent No. 11,848,286, to include a plurality of distinct metal lines, at least one of which extends through the centerline and is substantially parallel to the interconnected metal lines, wherein the distinct metal lines lack interconnection by the second metallization layer, as taught by Chang, in order a relatively large capacitance in the same area without having to use additional capacitors and without using a high-k dielectric material to form a gate insulation layer (in contrast to a general capacitor device), thereby increasing efficiency and integration and lowering costs(¶0124).
Regarding claim 20, Claim 20 of US Patent No. 11,848,286 recites the semiconductor device of claim 19, wherein the plurality of interconnected metal lines include:
first metal lines that extend toward the second edge;
a first metal plate that interconnects the first metal lines;
second metal lines that extend toward the first edge; and
a second metal plate that interconnects the second metal lines.
Claims 1-3, 7-8, 11, 15 and 19-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 6-11 and 13 of U.S. Patent No. 11,688,702 in view of Chang (US 2012/0043595 A1) as cited in the IDS of 12/13/2023.
Regarding claim 1, Claim 1 of US Patent No. 11,688,702 recites a semiconductor device comprising:
a substrate having an active region that includes opposite first and second edges;
a first metallization layer including a plurality of first metal lines that extend toward the second edge, a first metal plate that interconnects the first metal lines,
a plurality of second metal lines that extend toward the first edge, and
a second metal plate that interconnects the second metal lines; and
a second metallization layer including a plurality of distinct metal lines.
Claim 1 of US Patent No. 11,688,702 does not recite a centerline substantially parallel to the first and second edges; wherein at least one of the first and second metal lines extends through the centerline; a plurality of distinct metal lines, at least one of which is substantially parallel to the first and second metal lines, wherein the distinct metal lines lack interconnection by the second metallization layer.
Chang teaches a semiconductor device(Figs. 1-3) comprising:
a centerline(A-A’) substantially parallel to the first and second edges; wherein at least one of the first and first metal lines(150a, 150c, ¶0103) extends through the centerline(A-A’) ; and a plurality of distinct metal lines(G1, G2, ¶0101), at least one of which is substantially parallel to the interconnected metal lines(150a, 150c, ¶0103), wherein the distinct metal lines(G1, G2, ¶0101) lack interconnection by the second metallization layer(126, ¶0130). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Claim 1 of US Patent No. 11,688,702, to include a centerline substantially parallel to the first and second edges; wherein at least one of the first and second metal lines extends through the centerline; a plurality of distinct metal lines, at least one of which is substantially parallel to the first and second metal lines,, wherein the distinct metal lines lack interconnection by the second metallization layer as taught by Chang, in order a relatively large capacitance in the same area without having to use additional capacitors and without using a high-k dielectric material to form a gate insulation layer (in contrast to a general capacitor device), thereby increasing efficiency and integration and lowering costs(¶0124).
Regarding claim 2, Claim 6 of US Patent No. 11,688,702 recites the semiconductor device of claim 1, wherein the first metal lines and the first metal plate have substantially the same thickness.
Regarding claim 3, Claim 7 of US Patent No. 11,688,702 recites the semiconductor device of claim 1, wherein the first metal lines and the first metal plate are integral with each other.
Regarding claim 7, Claim 9 of US Patent No. 11,688,702 recites the semiconductor device of claim 1, wherein at least one of the first and second metal plates is inside the active region.
Regarding claim 8, Claim 8 of US Patent No. 11,688,702 recites the semiconductor device of claim 1, wherein at least one of the first and second metal plates is outside the active region.
Regarding claim 10, Claim 10 of US Patent No. 11,688,702 recites a system comprising:
a substrate having an active region that includes opposite first and second edges;
an electronic component in the active region;
a first metallization layer including a plurality of interconnected metal lines; and
a second metallization layer between the substrate and the first metallization layer and including a plurality of distinct metal lines.
Claim 10 of US Patent No. 111,688,702 does not recite a centerline substantially parallel to the first and second edges; a plurality of distinct metal lines, at least one of which extends through the centerline and is substantially parallel to the interconnected metal lines., wherein the distinct metal lines lack interconnection by the second metallization layer.
Chang teaches a semiconductor device(Figs. 1-3) comprising:
a centerline(A-A’) substantially parallel to the first and second edges; wherein at least one of the first and first metal lines(150a, 150c, ¶0103) extends through the centerline(A-A’) ; and a plurality of distinct metal lines(G1, G2, ¶0101), at least one of which is substantially parallel to the interconnected metal lines(150a, 150c, ¶0103), wherein the distinct metal lines(G1, G2, ¶0101) lack interconnection by the second metallization layer(126, ¶0130). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Claim 10 of US Patent No. 11,688,702, to include a centerline substantially parallel to the first and second edges; a plurality of distinct metal lines, at least one of which extends through the centerline and is substantially parallel to the interconnected metal lines, wherein the distinct metal lines lack interconnection by the second metallization layer, as taught by Chang, in order a relatively large capacitance in the same area without having to use additional capacitors and without using a high-k dielectric material to form a gate insulation layer (in contrast to a general capacitor device), thereby increasing efficiency and integration and lowering costs(¶0124).
Regarding claim 11, Claim 11 of US Patent No. 11,688,702 recites the system of claim 10, wherein the plurality of interconnected metal lines include:
first metal lines that extend toward the second edge;
a first metal plate that interconnects the first metal lines;
second metal lines that extend toward the first edge; and
a second metal plate that interconnects the second metal lines.
Regarding claim 15, Claim 13 of US Patent No. 11,688,702 recites the system of claim 11, further comprising a diode in the active region, wherein the diode has an anode coupled to a first metal line of the plurality of first metal lines and a cathode coupled to a second metal line of the plurality of second metal lines.
Regarding claim 19, Claim 1 of US Patent No. 11,688,702 recites a semiconductor device comprising:
a substrate having an active region that includes opposite first and second edges;
a first metallization layer including a plurality of interconnected metal lines; and
a second metallization layer between the substrate and the first metallization layer and including a plurality of distinct metal lines.
Claim 1 of US Patent No. 11,688,702 does not recite a centerline substantially parallel to the first and second edges and a plurality of distinct metal lines, at least one of which extends through the centerline and is substantially parallel to the interconnected metal lines, wherein the distinct metal lines lack interconnection by the second metallization layer.
Chang teaches a semiconductor device(Figs. 1-3) comprising:
a centerline(A-A’) substantially parallel to the first and second edges; wherein at least one of the first and first metal lines(150a, 150c, ¶0103) extends through the centerline(A-A’) ; and a plurality of distinct metal lines(G1, G2, ¶0101), at least one of which is substantially parallel to the interconnected metal lines(150a, 150c, ¶0103), wherein the distinct metal lines(G1, G2, ¶0101) lack interconnection by the second metallization layer(126, ¶0130). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Claim 1 of US Patent No. 111,688,702, to include a centerline substantially parallel to the first and second edges; a plurality of distinct metal lines, at least one of which extends through the centerline and is substantially parallel to the interconnected metal lines, wherein the distinct metal lines lack interconnection by the second metallization layer, as taught by Chang, in order a relatively large capacitance in the same area without having to use additional capacitors and without using a high-k dielectric material to form a gate insulation layer (in contrast to a general capacitor device), thereby increasing efficiency and integration and lowering costs(¶0124).
Regarding claim 20, Claim 1 of US Patent No. 11,688,702 recites the semiconductor device of claim 19, wherein the plurality of interconnected metal lines include:
first metal lines that extend toward the second edge;
a first metal plate that interconnects the first metal lines;
second metal lines that extend toward the first edge; and
a second metal plate that interconnects the second metal lines.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 8, 10-13, 17 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang (US 2012/0043595 A1) as cited in the IDS of 12/13/2023.
Regarding claim 1, Chang teaches a semiconductor device(Figs. 1-3) comprising:
a substrate(100) having an active region(ACT1, ACT3 ¶0100) that includes opposite first and second edges and a centerline(A-A’) substantially parallel to the first and second edges;
a first metallization layer(M1, M2, 150a, 150b, 150c, ¶0103) including a plurality of first metal lines(150b, 150c, ¶0103) that extend toward the second edge,
a first metal plate(M1, ¶0102) that interconnects the first metal lines(150b, 150c, ¶0103),
a plurality of first metal lines(150a, 150c, ¶0103) that extend toward the first edge, and
a second metal plate(M2, ¶0103) that interconnects the first metal lines(150a, 150c, ¶0103), wherein at least one of the first and first metal lines(150a, 150c, ¶0103) extends through the centerline(A-A’) ; and
a second metallization layer(126, ¶0130) including a plurality of distinct metal lines(G1, G2, ¶0101), at least one of which is substantially parallel to the first and first metal lines(150a, 150c, ¶0103), wherein the distinct metal lines(G1, G2, ¶0101) lack interconnection by the second metallization layer(126, ¶0130).
Regarding claim 2, Chang teaches the semiconductor device of claim 1, wherein the first metal lines(150b, 150c, ¶0103) and the first metal plate(M1, ¶0102) have substantially the same thickness(¶0135, Fig. 1).
Regarding claim 3, Chang teaches the semiconductor device of claim 1, wherein the first metal lines(150b, 150c, ¶0103) and the first metal plate(M1, ¶0102) are integral with each other(Fig. 1).
Regarding claim 5, Chang teaches the semiconductor device of claim 1, further comprising an electronic component(MOS Capacitor, ¶0100) in the active region(ACT1, ACT3 ¶0100) .
Regarding claim 8, Chang teaches the semiconductor device of claim 1, wherein at least one of the first and second metal plates(M1, M2, ¶0103) is outside the active region(ACT1, ACT3 ¶0100) .
Regarding claim 10, Chang teaches a system(Figs. 1-3) comprising:
a substrate(100) having an active region(ACT1, ACT3 ¶0100) that includes opposite first and second edges and a centerline(A-A’) substantially parallel to the first and second edges;
an electronic component(MOS Capacitor, ¶0100) in the active region(ACT1, ACT3 ¶0100) ;
a first metallization layer(M1, M2, 150a, 150b, 150c, ¶0103) including a plurality of interconnected metal lines(M1, M2, 150a, 150b, 150c, ¶0103); and
a second metallization layer(126, ¶0130) between the substrate(100) and the first metallization layer(M1, M2, 150a, 150b, 150c, ¶0103) and including a plurality of distinct metal lines(G1, G2, ¶0101), at least one of which extends through the centerline(A-A’) and is substantially parallel to the interconnected metal lines(M1, M2, 150a, 150b, 150c, ¶0103), wherein the distinct metal lines(G1, G2, ¶0101) lack interconnection by the second metallization layer(126, ¶0130).
Regarding claim 11, Chang teaches the system of claim 10, wherein the plurality of interconnected metal lines(M1, M2, 150a, 150b, 150c, ¶0103) include:
first metal lines(150b, 150c, ¶0103) that extend toward the second edge;
a first metal plate(M1, ¶0102) that interconnects the first metal lines(150b, 150c, ¶0103);
first metal lines(150a, 150c, ¶0103) that extend toward the first edge; and
a second metal plate(M2, ¶0103) that interconnects the first metal lines(150a, 150c, ¶0103).
Regarding claim 12, Chang teaches the system of claim 11, wherein the first metal lines(150b, 150c, ¶0103) and the first metal plate(M1, ¶0102) have substantially the same thickness(¶0135, Fig. 1).
Regarding claim 13, Chang teaches the system of claim 11, wherein the first metal lines(150b, 150c, ¶0103) and the first metal plate(M1, ¶0102) are integral with each other(Fig. 1).
Regarding claim 17, Chang teaches the system of claim 11, wherein at least one of the first and second metal plates(M1, M2, ¶0103) is outside the active region(ACT1, ACT3 ¶0100).
Regarding claim 19, Chang teaches a semiconductor device(Figs. 1-3) comprising:
a substrate(100) having an active region(ACT1, ACT3 ¶0100) that includes opposite first and second edges and a centerline(A-A’) substantially parallel to the first and second edges;
a first metallization layer(M1, M2, 150a, 150b, 150c, ¶0103) including a plurality of interconnected metal lines(M1, M2, 150a, 150b, 150c, ¶0103); and
a second metallization layer(126, ¶0130) between the substrate(100) and the first metallization layer(M1, M2, 150a, 150b, 150c, ¶0103) and including a plurality of distinct metal lines(G1, G2, ¶0101), at least one of which extends through the centerline(A-A’) and is substantially parallel to the interconnected metal lines(M1, M2, 150a, 150b, 150c, ¶0103), wherein the distinct metal lines(G1, G2, ¶0101) lack interconnection by the second metallization layer(126, ¶0130).
Regarding claim 20, Chang teaches the semiconductor device of claim 19, wherein the plurality of interconnected metal lines(M1, M2, 150a, 150b, 150c, ¶0103) include:
first metal lines(150b, 150c, ¶0103) that extend toward the second edge;
a first metal plate(M1, ¶0102) that interconnects the first metal lines(150b, 150c, ¶0103);
first metal lines(150a, 150c, ¶0103) that extend toward the first edge; and
a second metal plate(M2, ¶0103) that interconnects the first metal lines(150a, 150c, ¶0103).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2012/0043595 A1) as cited in the IDS of 12/13/2023 in view of Takada (US 2013/0062625 A1) as cited in the IDS of 12/13/2023.
Regarding claim 4, Chang teaches the semiconductor device of claim 1.
The embodiment of Figs. 1-3 of Chang is not relied on to teach a third metallization layer between the first and second metallization layers and including a plurality of metal lines, and a metal plate that interconnects the metal lines and that has a different size than at least one of the first and second metal plates(M1, M2, ¶0103).
The embodiment of Fig. 18 of Chang teaches a third metallization layer(550a, 550b ¶0215) between the first and second metallization layers(570a, 570b, 526, ¶0215, ¶0217) and including a plurality of metal lines(550a, 550b ¶0215), and a metal plate(M1, M2, ¶0103, ¶0214, ¶0222) that interconnects the metal line(550a, 550b ¶0215). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the embodiment of Figs. 1-3 of Chang, to include a third metallization layer between the first and second metallization layers and including a plurality of metal lines, and a metal plate that interconnects the metal lines and that has a different size than at least one of the first and second metal plates, as taught by the embodiment of Fig. 18 of Chang, in order to further obtaining MIM capacitances between the wirings included in the first and third metallization layers(¶0221).
The embodiments of Figs. 1-3 of Chang and the embodiment of Fig. 18 of Chang are not relied on to teach a metal plate that interconnects the metal lines and that has a different size than at least one of the first and second metal plates(M1, M2, ¶0103).
Tsai teaches a semiconductor device(Fig. 5) comprising a metal plate(backbone of 321, ¶0027-28) that interconnects the metal lines(fingers of 321, ¶0027-28) and that has a different size(Fig. 5, wherein the backbone of 321 is smaller than the backbone of 332) than at least one of the first and second metal plates(backbones of 332, 331, ¶0027-28). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang, so that a metal plate that interconnects the metal lines and that has a different size than at least one of the first and second metal plates as taught by Tsai, in order to reduce the stray capacitance between different patterns in the same electrically conductive layer and the equivalent capacitance of the layout structure of electrostatic discharge protection circuit(¶0029).
Regarding claim 14, Chang teaches the system of claim 11.
The embodiment of Figs. 1-3 of Chang is not relied on to teach a third metallization layer between the first and second metallization layers and including a plurality of metal lines, and a metal plate that interconnects the metal lines and that has a different size than at least one of the first and second metal plates(M1, M2, ¶0103).
The embodiment of Fig. 18 of Chang teaches a third metallization layer(550a, 550b ¶0215) between the first and second metallization layers(570a, 570b, 526, ¶0215, ¶0217) and including a plurality of metal lines(550a, 550b ¶0215), and a metal plate(M1, M2, ¶0103, ¶0214, ¶0222) that interconnects the metal line(550a, 550b ¶0215). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the embodiment of Figs. 1-3 of Chang, to include a third metallization layer between the first and second metallization layers and including a plurality of metal lines, and a metal plate that interconnects the metal lines and that has a different size than at least one of the first and second metal plates, as taught by the embodiment of Fig. 18 of Chang, in order to further obtaining MIM capacitances between the wirings included in the first and third metallization layers(¶0221).
The embodiments of Figs. 1-3 of Chang and the embodiment of Fig. 18 of Chang are not relied on to teach a metal plate that interconnects the metal lines and that has a different size than at least one of the first and second metal plates(M1, M2, ¶0103).
Tsai teaches a system(Fig. 5) comprising a metal plate(backbone of 321, ¶0027-28) that interconnects the metal lines(fingers of 321, ¶0027-28) and that has a different size(Fig. 5, wherein the backbone of 321 is smaller than the backbone of 332) than at least one of the first and second metal plates(backbones of 332, 331, ¶0027-28). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang, so that a metal plate that interconnects the metal lines and that has a different size than at least one of the first and second metal plates as taught by Tsai, in order to reduce the stray capacitance between different patterns in the same electrically conductive layer and the equivalent capacitance of the layout structure of electrostatic discharge protection circuit(¶0029).
Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2012/0043595 A1) as cited in the IDS of 12/13/2023 in view of Takada (US 2013/0062625 A1) as cited in the IDS of 12/13/2023 of record.
Regarding claim 6, Chang teaches the semiconductor device of claim 1, but is not relied on to teach a diode in the active region(ACT1, ACT3 ¶0100) , wherein the diode has an anode coupled to a first metal line of the plurality of first metal lines(150b, 150c, ¶0103) and a cathode coupled to a second metal line of the plurality of first metal lines(150a, 150c, ¶0103).
Takada teaches a semiconductor device(Fig. 1) comprising a diode e(10, ¶0026) in the active region, wherein the diode(10, ¶0026) has an anode(anode of diode 10, ¶0027) coupled to a first metal line(7, ¶0027) of the plurality of first metal lines(7, ¶0027) and a cathode(cathode of diode 10, ¶0027) coupled to a second metal line(8, ¶0027) of the plurality of second metal lines(8, ¶0027). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang, to include a diode in the active region, diode has an anode coupled to a first metal line of the plurality of first metal lines and a cathode coupled to a second metal line of the plurality of second metal lines, as taught by Takada, various rated current requirements or breakdown voltage requirements in the switching devices used in the field of power supplies of the power electronics can be met and a semiconductor device can be formed on a small chip without an unnecessary area(¶0021).
Regarding claim 15, Chang teaches the system of claim 11, but is not relied on to teach a diode in the active region(ACT1, ACT3 ¶0100) , wherein the diode has an anode coupled to a first metal line of the plurality of first metal lines(150b, 150c, ¶0103) and a cathode coupled to a second metal line of the plurality of first metal lines(150a, 150c, ¶0103).
Takada teaches a system(Fig. 1) comprising a diode(10, ¶0026) in the active region, wherein the diode(10, ¶0026) has an anode(anode of diode 10, ¶0027) coupled to a first metal line(7, ¶0027) of the plurality of first metal lines(7, ¶0027) and a cathode(cathode of diode 10, ¶0027) coupled to a second metal line(8, ¶0027) of the plurality of second metal lines(8, ¶0027). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang, to include a diode in the active region, diode has an anode coupled to a first metal line of the plurality of first metal lines and a cathode coupled to a second metal line of the plurality of second metal lines, as taught by Takada, various rated current requirements or breakdown voltage requirements in the switching devices used in the field of power supplies of the power electronics can be met and a semiconductor device can be formed on a small chip without an unnecessary area(¶0021).
Claims 7, 9, 16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2012/0043595 A1) as cited in the IDS of 12/13/2023 in view of Cheek et al. (US 5,970,311 A1) as cited in the IDS of 12/13/2023 of record
Regarding claim 7, Chang teaches the semiconductor device of claim 1, but is not relied on to teach at least one of the first and second metal plates(M1, M2, ¶0103) is inside the active region(ACT1, ACT3 ¶0100) .
Cheek teaches a semiconductor device(Fig. 3) wherein at least one of the first and second metal plates(323, col. 5, lines 40-55) is inside the active region(305, 307, col. 5, lines 40-55). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang, so that at least one of the first and second metal plates is inside the active region, as taught by Cheek, in order to maximize the amount of the active regions which are contacted is maximized to provide more accurate measurement of the electrical properties of the transistor(col. 5, lines 40-55).
Regarding claim 9, Chang teaches the semiconductor device of claim 1, but is not relied on to teach at least one of the first and second metal plates(M1, M2, ¶0103) is inside and outside of the active region(ACT1, ACT3 ¶0100) .
Cheek teaches a semiconductor device(Fig. 3) wherein at least one of the first and second metal plates(323, col. 5, lines 40-55) is inside and outside the active region(305, 307, col. 5, lines 40-55). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang, so that at least one of the first and second metal plates is inside and outside the active region, as taught by Cheek, in order to maximize the amount of the active regions which are contacted is maximized to provide more accurate measurement of the electrical properties of the transistor(col. 5, lines 40-55).
Regarding claim 16, Chang teaches the system of claim 11, but is not relied on to teach at least one of the first and second metal plates(M1, M2, ¶0103) is inside the active region(ACT1, ACT3 ¶0100) .
Cheek teaches a system(Fig. 3) wherein at least one of the first and second metal plates(323, col. 5, lines 40-55) is inside the active region(305, 307, col. 5, lines 40-55). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang, so that at least one of the first and second metal plates is inside the active region, as taught by Cheek, in order to maximize the amount of the active regions which are contacted is maximized to provide more accurate measurement of the electrical properties of the transistor(col. 5, lines 40-55).
Regarding claim 18, Chang teaches the system of claim 11, but is not relied on to teach at least one of the first and second metal plates(M1, M2, ¶0103) is inside and outside of the active region(ACT1, ACT3 ¶0100) .
Cheek teaches a system(Fig. 3) wherein at least one of the first and second metal plates(323, col. 5, lines 40-55) is inside and outside the active region(305, 307, col. 5, lines 40-55). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang, so that at least one of the first and second metal plates is inside and outside the active region, as taught by Cheek, in order to maximize the amount of the active regions which are contacted is maximized to provide more accurate measurement of the electrical properties of the transistor(col. 5, lines 40-55).
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/LAURA M DYKES/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892