DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
2. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
However, should applicant desire to perfect the priority claim, a certified English translation of
the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-
English application.
Response to Arguments
3. Applicant's arguments, see pages 6-10, filed June 22, 2026 have been fully considered but they are not persuasive.
4. Regarding applicant’s arguments with respect to the rejection of claims 1 and 11 under 35 USC § 102(a), applicant argues that “the heat-resistant adhesive sheet 2 in Hoshino is removed…. Heat-resistant adhesive sheet 2 is not equivalent to the offset suppression layer 21 of the present application.” However, Hoshino discloses the device and method of claims 1 and 11, respectively, of the present application. Claim 1 can read as an intermediate of the device of Hoshino. The device exists prior to further processing, and is therefore anticipated by Hoshino. Similarly, claim 11 can read as a portion of the method of Hoshino. Therefore, examiner’s rejection of claims 1 and 11 are maintained.
Furthermore, applicant’s arguments with respect to the rejection of the dependent claims anticipated by Hoshino (2, 5, 12, and 15) under 35 USC § 102(a), and dependent claims rejected in view of Igarashi (3 and 13), Scanlan (4 and 14), or Yu (6, 8-10, 16, and 18-20) under 35 USC § 103 are founded on the grounds that Hoshino fails to disclose the claimed inventions in the present application. Therefore, examiner’s rejection of the above dependent claims are maintained.
5. Regarding rejection of claims 4 and 14 under 35 USC § 112(b), applicant has amended the claim to read “are equal” from “are equal or close and belong to a same grade.” Examiner withdraws the rejection due to applicant’s amendments.
6. Regarding the specification objections, applicant has amended the title to be more descriptive and the informality to paragraphs [0003] and [0008]. Examiner withdraws the specification objections due to applicant’s amendments.
Claim Rejections - 35 USC § 102
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
8. Claims 1-2, 5, 11-12, and 15 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Hoshino et al. (US 2011/0151625 A1, hereafter Hoshino).
Regarding claim 1, Hoshino discloses an electronic package, comprising:
a carrier (Fig. 1B 3, [0012]);
an offset suppression layer (modified Fig. 1B 11, [0081]) having a first surface (modified Fig. 1B 11’) and a second surface (modified Fig. 1B 11”) opposing the first surface (modified Fig. 1B 11’), wherein the offset suppression layer (modified Fig. 1B 11) is formed on the carrier via the second surface (11”);
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[AltContent: textbox (For the record, the inserted figure (modified Fig. 1B of Hoshino) depicts the electronic package of Hoshino. The package consists of a carrier (3), an offset suppression layer (11) with a first (11’) and second (11”) surface , an adhesive layer (12), a first electronic element (1) and a second electronic element (1’), and an encapsulant (4).)]a first electronic element (modified Fig. 1B 1 of Hoshino, [0012]) and a second electronic element (modified Fig. 1B 1’, [0012]) disposed on the first surface (11’) of the offset suppression layer (11);
and an encapsulant (modified Fig. 1B 4, [0013]) formed on the first surface (11’) of the offset suppression layer (11) and covering the first electronic element (1) and the second electronic element (1’).
Regarding claim 2, Hoshino discloses the package of claim 1, wherein the electronic package further comprises an adhesive layer (modified Fig. 1B 12 of Hoshino), wherein the first electronic element (1) and the second electronic element (1’) are bonded to the first surface (11’) of the offset suppression layer (11).
Regarding claim 5, Hoshino discloses the package of claim 1, wherein the thickness of the offset suppression layer (11) is between 40 microns and 70 microns ([0087]).
Regarding claim 11, Hoshino discloses a method of manufacturing an electronic package, comprising:
forming an offset suppression layer (modified Fig. 1B 11, [0081]) having a first surface (modified Fig. 1B 11’) and a second surface (modified Fig. 1B 11”) opposing the first surface (11’) on a carrier (Fig. 1B 3, [0012]); via the second surface;
disposing a first electronic element (modified Fig. 1B 1 of Hoshino, [0012]) and a second electronic element (modified Fig. 1B 1’ of Hoshino, [0012]) on the first surface of the offset suppression layer (11); and
forming an encapsulant (modified Fig. 1B 4, [0013]) on the first surface (11’) of the offset suppression layer (11) to cover the first electronic element (1) and the second electronic element (1’).
Regarding claim 12, Hoshino discloses the method of manufacturing an electronic package of claim 11, wherein the first electronic element (1) and the second electronic element (1’) are bonded onto the first surface (11’) of the offset suppression layer (11) via an adhesive layer (modified Fig. 1B 12 of Hoshino).
Regarding claim 15, Hoshino discloses the method of manufacturing an electronic package of claim 11, wherein the thickness of the offset suppression layer (11) is between 40 microns and 70 microns ([0087]).
Claim Rejections - 35 USC § 103
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. Claims 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Hoshino as applied to claims 1 and 11 above, and further in view of Igarashi et al. (US 2020/0048501 A1, hereafter Igarashi).
Regarding claim 3, Hoshino discloses the package of claim 1.
Hoshino fails to disclose an offset suppression layer (11) made of polyimide.
Igarashi discloses that the offset suppression layer (11) can be made of polyimide ([0048]). Igarashi is analogous to Hoshino in the field of manufacturing electronic components and packaging.
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the material of the offset suppression layer of Hoshino with the polyimide to produce an offset suppression layer with sufficient mechanical strength and lowered cost.
Regarding claim 13, Hoshino discloses the method of manufacturing an electronic package of claim 11.
Hoshino fails to disclose an offset suppression layer (11) made of polyimide.
Igarashi discloses that the offset suppression layer (11) can be made of polyimide ([0048]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the material of the offset suppression layer of Hoshino with the polyimide to produce an offset suppression layer with sufficient mechanical strength and lowered cost.
11. Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Hoshino as applied to claims 1 and 11 above, and further in view of Scanlan (US 2011/0198762 A1).
Regarding claim 4, Hoshino discloses the package of claim 1, wherein Hoshino discloses a coefficient of thermal expansion of the offset layer (11, Hoshino [0081] discloses a coefficient of 0.8 to 5.6 x 10-5/K).
Hoshino fails to disclose a coefficient of thermal expansion of the encapsulant (4).
Scanlan discloses a coefficient of thermal expansion of the encapsulant (4, Scanlan [0020] discloses a coefficient of 11 to 18 ppm/°C (1.1 to 1.8 x 10-5/K)) that is equal to a coefficient of thermal expansion of the offset layer (11). Scanlan is analogous to Hoshino in the field of manufacturing electronic components and packaging.
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the encapsulant of Hoshino with the encapsulant of Scanlan to allow for similar thermal expansion of the offset layer and encapsulant during the molding process.
Regarding claim 14, Hoshino discloses the method of manufacturing an electronic package of claim 11, wherein Hoshino discloses a coefficient of thermal expansion of the offset layer (11, Hoshino [0081] discloses a coefficient of 0.8 to 5.6 x 10-5/K).
Hoshino fails to disclose a coefficient of thermal expansion of the encapsulant (4).
Scanlan discloses a coefficient of thermal expansion of the encapsulant (4, Scanlan [0020] discloses a coefficient of 11 to 18 ppm/°C (1.1 to 1.8 x 10-5/K)) that is equal to a coefficient of thermal expansion of the offset layer (11).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the encapsulant of Hoshino with the encapsulant of Scanlan to allow for similar thermal expansion of the offset layer and encapsulant during the molding process.
12. Claims 6, 8-10, 16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hoshino as applied to claim 1 and 11 above, and further in view of Yu et al. (US 2023/0411231 A1, hereafter Yu).
Regarding claim 6, Hoshino discloses the package of claim 1.
Hoshino fails to disclose a ratio of a thickness of the offset suppression layer (11) and a thickness of the encapsulant (4).
Yu discloses the ratio of the thickness of the offset suppression layer (modified Fig 7E of Yu 20) and the thickness of the encapsulant (modified Fig 7E of Yu 20) to be 1.75:1. Yu is analogous to Hoshino in the field of manufacturing electronic components and packaging.
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hoshino to have the ratio of the thickness of the offset suppression layer and the thickness of the encapsulant to prevent offset of the electronic elements.
Regarding claim 8, Hoshino discloses the package of claim 1, wherein the offset suppression layer (11) is bonded to the encapsulant (4) covering the first electronic element (1) and the second electronic element (1’).
Hoshino fails to disclose the first surface (11’) of the offset suppression layer (11) to be a rough surface.
Yu discloses a rough surface (modified Fig. 7E 20’ of Yu) on the offset suppression layer (11) that is bonded to the encapsulant (4).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the first surface of the offset suppression layer in the device of Hoshino with the rough surface of Yu to prevent offset of the electronic elements.
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[AltContent: textbox (For the record, the inserted figure (modified Fig. 7E of Yu) depicts the electronic package of Yu. The package consists of a carrier (10), an offset suppression layer (20) with a first surface (20’), electronic elements (3), and an encapsulant (4). The ratio between the offset suppression layer (20) and the encapsulant (4) is 1.75.)] Regarding claim 9, Hoshino discloses the package of claim 1, wherein the offset suppression layer (11) is bonded to the encapsulant (4) covering the first electronic element (1) and the second electronic element (1’).
Hoshino fails to disclose a first surface (11’) of the offset suppression layer (11) formed to have a plurality of convex portions and a plurality of recessed portions.
Yu discloses a first surface of the offset suppression layer (modified Fig. 7E 20 of Yu) formed to have a plurality of convex portions and a plurality of recessed portions (modified Fig. 7E 20’ of Yu) on the offset suppression layer (20) that is bonded to the encapsulant (4).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the first surface of the offset suppression layer in the device of Hoshino with the surface formed of a plurality of convex and recessed portions of Yu to prevent offset of the electronic elements.
Regarding claim 10, Hoshino discloses the package of claim 1.
Hoshino fails to disclose a first surface (11’) of the offset suppression layer (11) formed with a first and a second recessed portion and the first and second electronic elements (modified Fig. 1B 1 and 1’, respectively, of Hoshino) bonded to the first and second recessed portions, respectively.
Yu discloses a first surface of the offset suppression layer (modified Fig. 7E 20 of Yu) formed to have a first and second recessed portion (modified Fig. 7E 20’ of Yu) on the offset suppression layer (2000) bonded to a first and second electronic element (modified Fig. 7E 3 of Yu).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the first surface of the offset suppression layer in the device of Hoshino with the surface of Yu formed with a first and second recessed portion bonded to bonded to a first and second electronic element prevent offset of the electronic elements.
Regarding claim 16, Hoshino discloses the method of manufacturing an electronic package of claim 11.
Hoshino fails to disclose a ratio of a thickness of the offset suppression layer (11) and a thickness of the encapsulant (4).
Yu discloses the ratio of the thickness of the offset suppression layer (modified Fig 7E of Yu 20) and the thickness of the encapsulant (modified Fig 7E of Yu 20) to be 1.75:1.
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Hoshino to have the ratio of the thickness of the offset suppression layer and the thickness of the encapsulant to prevent offset of the electronic elements.
Regarding claim 18, Hoshino discloses the method of manufacturing an electronic package of claim 11, wherein the offset suppression layer (11) is bonded to the encapsulant (4) covering the first electronic element (1) and the second electronic element (1’).
Hoshino fails to disclose forming the first surface (11’) of the offset suppression layer (11) to be a rough surface.
Yu discloses forming a rough surface (modified Fig. 7E 20’ of Yu) on the offset suppression layer (11) that is bonded to the encapsulant (4).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the first surface of the offset suppression layer in the device of Hoshino with the rough surface of Yu to prevent offset of the electronic elements.
Regarding claim 19, Hoshino discloses the method of manufacturing an electronic package of claim 11, wherein the offset suppression layer (11) is bonded to the encapsulant (4) covering the first electronic element (1) and the second electronic element (1’).
Hoshino fails to disclose forming a first surface (11’) of the offset suppression layer (11) with a plurality of convex portions and a plurality of recessed portions.
Yu discloses forming a first surface of the offset suppression layer (modified Fig. 7E 20 of Yu) formed to have a plurality of convex portions and a plurality of recessed portions (modified Fig. 7E 20’ of Yu) on the offset suppression layer (20) that is bonded to the encapsulant (4).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the first surface of the offset suppression layer in the device of Hoshino with a plurality of convex and recessed portions of Yu to prevent offset of the electronic elements.
Regarding claim 20, Hoshino discloses the method of manufacturing an electronic package of claim 11.
Hoshino fails to disclose forming a first surface (11’) of the offset suppression layer (11) with a first and a second recessed portion and the first and second electronic elements (modified Fig. 1B 1 and 1’, respectively, of Hoshino) bonded to the first and second recessed portions, respectively.
Yu discloses forming a first surface of the offset suppression layer (modified Fig. 7E 20 of Yu) formed to have a first and second recessed portion (modified Fig. 7E 20’ of Yu) on the offset suppression layer (2000) bonded to a first and second electronic element (modified Fig. 7E 3 of Yu).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the first surface of the offset suppression layer in the device of Hoshino with a first and second recessed portion bonded to bonded to a first and second electronic element prevent offset of the electronic elements.
13. Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Hoshino as applied to claims 1 and 11 above, and further in view of Mahler et al (US 2017/0221857 A1, hereafter Mahler).
Regarding claim 7, Hoshino discloses the package of claim 1, wherein Hoshino discloses a first electronic element (1) and a second electronic element (1’).
Hoshino fails to disclose the thickness of the electronic elements (1, 1’).
Mahler discloses the thicknesses ([0018]) of the first and second electronic elements to be less than 60 microns. Mahler is analogous to Hoshino in the field of manufacturing electronic components and packaging.
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the electronic elements of Hoshino with the electronic elements of Mahler to provide control over the thickness of the overall electronic package.
Regarding claim 17, Hoshino discloses the method of manufacturing an electronic package of claim 11, wherein Hoshino discloses a first electronic element (1) and a second electronic element (1’).
Hoshino fails to disclose the thickness of the electronic elements (1, 1’).
Mahler discloses the thicknesses ([0018]) of the first and second electronic elements to be less than 60 microns.
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the electronic elements of Hoshino with the electronic elements of Mahler to provide control over the thickness of the overall electronic package.
Conclusion
14. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL B SUN whose telephone number is (571)699-0231. The examiner can normally be reached Mon-Fri 8:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL B SUN/
Examiner, Art Unit 2892
/LEX H MALSAWMA/Primary Examiner, Art Unit 2892
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