CTNF 18/538,704 CTNF 91297 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION Title 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. (see MPEP § 606.01). This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc. 06-11-01 AIA The following title is suggested: “Display device Including Oxide Semiconductor Transistors Having Different Gate Insulating Structures and method for manufacturing the same” Claim Objections 07-29-01 AIA Claim 2 is objected to because of the following informalities: the “includes” should be “include” because the subject is plural, but the verb is singular . Appropriate correction is required. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-3 and 10 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Kim (US 20210020717) . Regarding claim 1. Fig 2 (plan view of display device), Fig 7 (a first transistor view in Fig 2), Fig 8 (a lateral view of Fig 7), Fig 9 (a second transistor view in Fig 2) and Fig 23 (a lateral portion view of Fig 2) of Kim disclose A display device (Fig 2) comprising: a pixel [0132] comprising a first transistor (Fig 7, [0132]: TR1) located in a display area (Fig 2: DA); and a driving circuit 30 [0174] comprising a second transistor (Fig 9, [0174]: “driving circuit 30 may be formed to be substantially the same as the second transistor TR2”. Thus, TR2 is second transistor) located in a non-display area (Fig 2: NDA), wherein the first transistor (Fig 23: the left side transistor which is TR1) comprises: a first active layer 350 [0132] comprising a first channel region 350c [0137], and a first source region 350a and a first drain region 350b which are spaced apart from each other with the first channel region interposed therebetween (Fig 23); a first gate insulating layer 130 ([0131]: in TR1) disposed on the first active layer and covering the first channel region, the first source region and the first drain region (Fig 23: the 350c and the inner portions of each 350a and 350b are vertically overlapped with 130. Thus, they are being covered by 130; also refer to the Fig 8 for the detail view of the overlapping); and a first gate electrode 310 [0132] disposed on the first gate insulating layer and overlapping the first channel region (Fig 23), wherein the second transistor (Fig 23: the right side transistor which is TR2) comprises: a second active layer 450 [0132] comprising a second channel region 450c [0137], and a second source region 450a and a second drain region 450b which are spaced apart from each other with the second channel region interposed therebetween (Fig 23); a second gate insulating layer 130 ([0131]: in TR2) disposed on a part (Fig 23: the center part of 450c) of the second active layer comprising the second channel region and exposing the second source region and the second drain region (Fig 23: the 130 only covers the 450c because 450a and 450b are not vertically overlapped with the 130. Thus, exposing the second source region and the second drain region); and a second gate electrode 410 [0132] disposed on the second gate insulating layer and overlapping the second channel region (Fig 23). Regarding claim 2. Kim discloses The display device of claim 1, wherein the first active layer and the second active layer includes a same oxide semiconductor [0136]. Regarding claim 3. Kim discloses The display device of claim 2, wherein the first active layer and the second active layer are disposed in a same layer as each other (Fig 23: both are located on the 120). Regarding claim 10. Kim discloses The display device of claim 1, wherein the first transistor and the second transistor are N-type oxide transistors [0103], and an electron mobility of the second transistor is higher than an electron mobility of the first transistor [0145] . 07-15 AIA Claim 13 is rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Kang (US 20170200740) . Regarding claim 13. Fig 3E (a detail portion view of Fig 4), Fig 8 (plan view of display device) and Fig 9 (a lateral portion view of Fig 8) of Kang disclose A display device comprising: a pixel [0083] comprising a first transistor ([0083]: TFT2) located in a display area (Fig 8/Fig 9: DA); and a driving circuit [0083] comprising a second transistor ([0083]: TFT1) located in a non-display area (Fig 8/Fig 9, [0083]: NDA), wherein the first transistor (TFT2) comprises: a first active layer 202 [0086] comprising a first channel region 202c, and a first source region 202a and a first drain region 202b which are spaced apart from each other with the first channel region interposed therebetween (Fig 9, [0086]); a first gate insulating layer 203 (unlabeled but similar to 103, which gate insulating layer in TFT1 [0051]) disposed on the first active layer; and a first gate electrode 204 [0086] disposed on the first gate insulating layer and overlapping the first channel region (Fig 9), wherein the second transistor (TFT1) comprises: a second active layer 102 [0042] comprising a second channel region 102c, and a second source region 102a and a second drain region 102b which are spaced apart from each other with the second channel region interposed therebetween (Fig 9); a second gate insulating layer 103 disposed on the second active layer; and a second gate electrode 104 disposed on the second gate insulating layer and overlapping a part of the second source region, a part of the second drain region, and the second channel region (Fig 9), wherein the first gate electrode does not overlap the first source region and the first drain region (Fig 9: no-overlapping), or overlaps the first source region and the first drain region by a part having a first length in a longitudinal direction of the first channel region, the second gate electrode overlaps the second source region and the second drain region by a part having a second length in a longitudinal direction of the second channel region (Fig 9, also refer to Fig 3E: ΔL which shows the overlapping portion), and the second length is greater than the first length (Fig 9, the first gate electrode has no-overlapping, thus ‘zero’ length whereas the second electrode has the overlapping length of at least 2ΔL, which means ‘at least 2ΔL : 0’. Thus, the second length is inherently greater than the first length) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20210020717) in view of Kang (US 20170200740) . Regarding claim 4. Kim discloses The display device of claim 1. But Kim does not disclose wherein the second gate electrode overlaps a part of the second source region and a part of the second drain region. However, Fig 3E of Kang disclose the second gate electrode 104 overlaps a part of the second source region 102a and a part (ΔL shows the overlapping portion) of the second drain region 102b. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Kim’s device t have the Kang’s structure for the purpose of reducing parasitic series resistance, increasing ON-current, and reducing the subthreshold swing (SS). This configuration enhances manage carrier concentration, reducing the OFF-state leakage current while increasing the drain current through improved carrier injection. Regarding claim 5. Kim in view of Kang discloses The display device of claim 4, wherein the second gate insulating layer 103 exposes a remaining part of the second source region and a remaining part of the second drain region except for the part of the second source region overlapping the second gate electrode and the part of the second drain region overlapping the second gate electrode (Fig 3E). Regarding claim 6. Kim in view of Kang discloses The display device of claim 4, Kang discloses wherein the first gate electrode 204 does not overlap the first source region 202a and the first drain region 202b (Fig 9). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Kim’s device to have the Kang’s structure for the purpose of reducing parasitic capacitance and lowers leakage current. This configuration mitigates high-field, hot-carrier-induced degradation, enhances pixel charging precision in displays, and minimizes off-state parasitic current . 07-21-aia AIA Claim s 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20210020717) in view of Kang (US 20170200740), and further in view of Moon (US 20230073848) . Regarding claim 7. Kim in view of Kang discloses The display device of claim 4. But Kim in view of Kang does not disclose wherein the first gate electrode overlaps a part of the first source region and a part of the first drain region. However, Moon discloses the first gate electrode (TR1) overlaps a part (Fig 1: 132a/132b) of the first source region 132a/133a and a part of the first drain region 132b/133b. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Kim in view of Kang’s device to have the Moon’s structure for the purpose of reducing the maximum electric field at the drain junction, which minimizes hot-carrier effects and reduces leakage current. It also lowers parasitic source/drain series resistance, enhancing on-current. Regarding claim 8. Kim in view of Kang and Moon disclose The display device of claim 7, Fig 1 of Moon discloses wherein the first gate electrode 150 overlaps the first source region 132a/133a and the first drain region 132b/133b by a part (132a/132b) having a first length (L2) in a longitudinal direction (X) of the first channel region 131, the second gate electrode 250 overlaps the second source region 232a/233a and the second drain region 232b/233b by a part (232a/232b) having a second length (L5) in a longitudinal direction (X) of the second channel region 231, and the second length is greater than the first length ([0059]: “L2 .. may be less than the fifth length L5”). Regarding claim 9. Kim in view of Kang and Moon disclose The display device of claim 7, Moon discloses wherein the first gate electrode 150 overlaps the first source region 132a/133a and the first drain region 132b/133b by a part (132a/133b) corresponding to a first ratio among parts overlapping the first active layer (Fig 1), the second gate electrode 250 overlaps the second source region 232a/233a and the second drain region 232b/233b by a part corresponding to a second ratio among parts overlapping the second active layer (Fig 1), and the second ratio is greater than the first ratio ([0059]: because L5 is greater than L2) . 07-21-aia AIA Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kang (US 20170200740) in view of Kim (US 20210020717) . Regarding claim 14. Kang discloses The display device of claim 13. But kang does not disclose wherein the first gate insulating layer covers the first channel region, the first source region, and the first drain region. However, Fig 23 of Kim discloses the first gate insulating layer 130 covers the first channel region 350c, the first source region 350a, and the first drain region 350b (350c and the inner portions of each 350a and 350b are vertically overlapped with 130. Thus, they are being covered by 130; also refer to the Fig 8 for the detail view of the overlapping). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Kang’s device to have the Kim’s structure for the purpose of reducing parasitic capacitance and lowers leakage current. This configuration mitigates high-field, hot-carrier-induced degradation, enhances pixel charging precision in displays, and minimizes off-state parasitic current . 07-21-aia AIA Claim s 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kang (US 20170200740) in view of Moon (US 20230073848) . Regarding claim 16. Kang discloses The display device of claim 13. Kang does not explicitly disclose wherein the first gate electrode overlaps the first source region and the first drain region by a part corresponding to a first ratio among parts of the first source region and the first drain region overlapping the first active layer, the second gate electrode overlaps the second source region and the second drain region by a part corresponding to a second ratio among parts of the second source region and the second drain region overlapping the second active layer, and the second ratio is greater than the first ratio. However, Fig 1 of Moon discloses 150 overlaps the first source region 132a/133a and the first drain region 132b/133b by a part (132a.132b) having a first length (L2) in a longitudinal direction (X) of the first channel region 131 the first gate electrode 150 (in TR1) overlaps the first source region 132a/133a and the first drain region 132b/133b by a part (132a/132b) by a part corresponding to a first ratio among parts of the first source region and the first drain region overlapping the first active layer 131, the second gate electrode 250 (in TR2) overlaps the second source region 232a/233a and the second drain region 232b/233b by a part (232a/232b) corresponding to a second ratio among parts of the second source region and the second drain region overlapping the second active layer 231, and the second ratio is greater than the first ratio ([0059]: because L5 is greater than L2). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Kang’s device to have the Moon’s structure for the purpose of reducing the maximum electric field at the drain junction, which minimizes hot-carrier effects and reduces leakage current. It also lowers parasitic source/drain series resistance, enhancing on-current. Regarding claim 17. Kang discloses The display device of claim 13. But Kang does not explicitly disclose wherein the first active layer and the second active layer includes a same oxide semiconductor. However, Moon discloses the first active layer 130 and the second active layer 230 includes a same oxide semiconductor [0073]. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Kang’s device to have the Moon’s active layer structure for the purpose of providing ultra-low off-state leakage current, high mobility, and excellent large-area uniformity. Thereby, enable lower power consumption (crucial for variable refresh rates), higher resolution, and increased flexibility in manufacturing . Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim s 18-20 are allowed. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 18. Kim discloses A method for manufacturing a display device, the method comprising: preparing a base layer 110 in which a display area (left) and a non-display area (right) are defined (Fig 19), and forming a first semiconductor pattern 350 and a second semiconductor pattern 450 on the base layer in the display area and the non-display area, respectively (Fig 19, [0132]); forming a first insulating layer 130 on the base layer to cover the first semiconductor pattern and the second semiconductor pattern (Fig 19); forming a first gate electrode 310 overlapping a part of the first semiconductor pattern and a second gate electrode 410 overlapping a part of the second semiconductor pattern, on the first insulating layer (Fig 21, [0132]). However, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, in particular, the forming steps of specific order, “maintaining the first insulating layer in an unetched state on the first semiconductor pattern in the display area, and etching the first insulating layer to expose a remaining part of the second semiconductor pattern which does not overlap the second gate electrode in the non-display area; and forming a second insulating layer covering the first semiconductor pattern, the second semiconductor pattern, the first insulating layer, the first gate electrode, and the second gate electrode” . 12-151-08 AIA 07-43 12-51-08 Claim s 11-12 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 11. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the third transistor comprises: a third active layer comprising a third channel region, and a third source region and a third drain region which are spaced apart from each other with the third channel region interposed therebetween; a third gate insulating layer disposed on a part of the third active layer and exposing the third source region and the third drain region, wherein the part of the third active layer comprises the third channel region; and a third gate electrode disposed on the third gate insulating layer and overlapping the third channel region”. Regarding claim 12. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the fourth transistor comprises: a fourth active layer comprising a fourth channel region, and a fourth source region and a fourth drain region which are spaced apart from each other with the fourth channel region interposed therebetween; a fourth gate insulating layer disposed on the fourth active layer and covering the fourth channel region, the fourth source region and the fourth drain region; and a fourth gate electrode disposed on the fourth gate insulating layer and overlapping the fourth channel region”. Regarding claim 15. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the second gate insulating layer is disposed only on a part of the second active layer comprising the second channel region, and the second gate insulating layer exposes remaining parts of the second source region and the second drain region except for parts of the second source region and the second drain region overlapping the second gate electrode ” . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Changhyun Yi/Primary Examiner, Art Unit 2812 Application/Control Number: 18/538,704 Page 2 Art Unit: 2812