DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 10/07/2024 and 12/13/2023, is/are in compliance with the provisions 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description:
“PX” is shown in Fig 5 but is not mentioned in the Specification.
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. All obviousness rationales stated below are rationales that would have been obvious prior to the earliest effective filing date of the application.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 11199871) herein referred to as Park (Fig 1 and 5), in view of Jin et al. (US 10014490) herein referred to as Jin. (Fig. 1A).
As to claims 1, Park teaches a display device in (Figs. 1 and 5) comprising:
a substrate ([col 10 line 43] substrate SUB) comprising a main region comprising a display area ([col 13 line 55-56] display area DA) in which emission areas (sensing electrodes SC1 and SC2) are arranged and
a non-display area ([col 5 line 41] non-display area NDA) disposed around the display area ([col 5 line 40] display area DA), and
a sub-region ([col 8 line 26] second bending area BA2) protruding from one side of the main region;
a circuit layer ([col 12 line 7] first insulating film group ING1) disposed on the substrate (substrate SUB);
a light emitting element layer ([col 13 line36] the light emitting film EML, LDE1 and LDE2) disposed on the circuit layer ([col 12 line7] first insulating film group ING1);
an encapsulation layer ([col 14 line 19] encapsulation film ENC1) disposed on the light emitting element layer (light emitting film EML, LDE1 and LDE2); and
the non-display area (non-display area NDA) comprises: a dam area [col 16, line 6] The dam DAM, DAM1 and DAM2) spaced apart from the display area (display area DA) and in which at least one dam portion (DAM1 / DAM2) surrounding the display area (display area DA) is arranged; and
a junction area (area outside DAM area) surrounding the dam area (DAM1 / DAM2), wherein the circuit layer (first insulating film group ING1) comprises:
a semiconductor layer ([col 11 lines 8-9] The active film ACT may be formed of a semiconductor material.) disposed on the substrate (substrate SUB);
a first insulating layer (1st insulating layer GI1) disposed on the substrate, covering the semiconductor layer, and containing an inorganic insulating material ([col 11 lines 20-22] The first gate insulating film GI1 may cover the active film ACT. The first gate insulating film GI1 may be an inorganic insulating film formed of an inorganic material.);
a first conductive layer (1st conductive layer GE) disposed on the first insulating layer ([col 11 line 26-28] A gate electrode GE of the transistor and a lower electrode LE of the capacitor Cst may be positioned on the first gate insulating film GI1);
a second insulating layer (2nd insulating layer GI2) disposed on the first insulating layer, covering the first conductive layer, and containing the inorganic insulating material ([col 11 lines 39-42]) A second gate insulating film GI2 may cover the gate electrode GE and the lower electrode LE. The second gate insulating film GI2 may be an inorganic insulating film formed of an inorganic material.);
a second conductive layer (2nd conductive layer UE +LE) disposed on the second insulating layer ([col 11 lines 56-58] The lower electrode LE and the upper electrode UE may form the capacitor Cst with the second gate insulating film GI2 interposed therebetween);
a third insulating layer (3rd insulating layer ILD) disposed on the second conductive layer, covering the second conductive layer, and containing the inorganic insulating material ([col 11 lines 66-67 col 12 line 1]An interlayer insulating film ILD may cover the upper electrode UE. The interlayer insulating film ILD may be an inorganic insulating film formed of an inorganic material.);
a third conductive layer ( 3rd conductive layer ILD) disposed on the third insulating layer ([col 12 line 11-12]The first connection pattern CNP1 may be positioned on the interlayer insulating film ILD.);
a fourth insulating layer (4th insulating layer VIA1) disposed on the third insulating layer, covering the third conductive layer, and containing an organic insulating material ([col 12 lines 31-32] The first via film VIA1 may be an organic insulating film formed of an organic material.);
a fourth conductive layer (4th conductive layer CNP2) disposed on the fourth insulating layer ([col 12 lines 38-40] The second connection pattern CNP2 maybe connected to the first connection pattern CNP1 through an opening portion of the first via film VIA1;) and
a fifth insulating layer (5th insulating layer VIA2) disposed on the fourth insulating layer, covering the fourth conductive layer, and containing the organic insulating material ([col 12 lines 45-48 The second via film VIA2 may cover the first via film VIA1 and the second connection pattern CNP2. The second via film VIA2 may be an organic insulating film formed of an organic material.), wherein
in the junction area (area outside DAM area), the encapsulation layer (encapsulation film ENC1) is disposed directly on the third insulating layer ( 3rd conductive layer ILD),
a thickness of the third insulating layer ( 3rd conductive layer ILD), at a central point of the junction area is substantially the same as a thickness of the third insulating layer (3rd conductive layer ILD), in the display area (display area DA), and
the center point is measured with respect to a direction from the sub-region (second bending area BA2) to the main region.
Park does not appear to expressly disclose "a polarization layer disposed on the encapsulation layer and overlapping the light emitting element layer”. It is well known in the art of displays to improve contrast in the display region through the use of a polarized layer or polarizer, which acts as an optical filter allowing light waves oscillating in a specific direction to pass through, while blocking others.
However, Jin does teach in Fig. 1A (prior art) a structure schematic diagram of the display panel comprising a base plate 100 on the sealing thin film transistor layer 200, and a thin film transistor layer 200 on the organic light emitting layer 300. The organic light emitting layer 300 of the packaging layer 400, is arranged in the packaging, the polarization layer 500 is arranged on layer 400, and a polarizing covering is arranged on the window layer 500, wherein the thin film encapsulation layer 400 comprises a first encapsulating layer 420 and second encapsulating layer 440
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to provide a polarization layer on the encapsulation layer of the Park device as in the Jin device to improve contrast so as to use an industrially tested and accepted device.
As to claim 2, the Park/Jin combination device teaches the display device of claim 1, wherein
the polarization layer (component 500 of Fig. 1A Jin) extends to the non-display area and overlaps the junction area of the non-display area.
As to claim 3, the Park/Jin combination device teaches the display device of claim 2, wherein
the sub-region comprises a bending area which is bendable ([col 10 lines 44-46 substrate SUB may be formed of a material having flexibility so as to be bent or folded,),
a first sub-region (Annotated 1st sub region, Fig. 1 Park) disposed between a first side (Annotated 1st side) of the bending area and the main region, and
a second sub-region (Annotated 2nd sub region, Fig. 1 Park) connected to a second side (Annotated 2nd side) of the bending area opposite to the first side,
the light emitting element layer comprises light emitting elements, (Fig. 5 LDE1 and LDE2) corresponding to the emission areas, respectively,
the circuit layer further (first insulating film group ING1) comprises: pixel drivers (PDE 1 and 2 Fig. 5)corresponding to the emission areas and electrically connected to the light emitting elements of the light emitting element layer, respectively;
data lines ([col 27 line 32] data line Dj) for transmitting a data signal ([col 27 line 32] signal line Dj (D1,D2,D3) Fig 27) to the pixel drivers; and
data connection lines (Fig. 28 line T2 connects Dj to INTL) disposed in the non-display area electrically connected to the data lines (data line Dj), respectively, and extending to the first sub-region,
the fourth conductive layer (4th conductive layer CNP2) comprises the data lines,
the first conductive layer (1st conductive layer GE) comprises some of the data connection lines,
the second conductive layer (2nd conductive layer UE +LE) comprises remaining others of the data connection lines, and
the polarization layer (component 500 of Fig. 1A Jin) overlaps the data connection lines (Fig. 28 connecting lines of PXij are in the pixel area )in the non-display area.
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As to claim 4, the Park/Jin combination device teaches the display device of claim 3, wherein
each of the pixel drivers ([col 7 lines 23] driver of the pixel) comprises two or more transistors and at least one capacitor, ([col 10 lines 40-42] “In FIG. 5, for convenience of description, one transistor, one light emitting element, and one capacitor Cst are shown for one pixel PX as an example” and [col 26 lines 13-15] “FIG. 28, the pixel PXij includes transistors T1, T2, T3, T4, T5, T6, and T7, a storage capacitor Cst, and a light emitting diode LD.”)
the semiconductor layer comprises active layers (ACT [col 11 lines 8-9] “The active film ACT may be formed of a semiconductor material.”) of the transistors,
the first conductive layer (Fig. 5, 1st conductive layer GE) further comprises gate electrodes of the transistors ([col 26 lines 34-65 and col 27 lines 1-9] transistors comprise gate electrodes),
the second conductive layer (2nd conductive layer UE + LE) further comprises a first capacitor electrode of the capacitor ([col 26 lines 34-65 and col 27 lines 1-9] transistors comprise gate electrodes),
the third conductive layer ( 3rd conductive layer ILD) comprises source electrodes of the transistors and drain electrodes of the transistors, ([col 12 lines 11-12] “The first connection pattern CNP1 may be positioned on the interlayer insulating film ILD. The first connection pattern CNP1 may be in contact with each of a source electrode and a drain electrode of the active film ACT” ) and
the fourth conductive layer (4th conductive layer CNP2) further comprises anode connection electrodes corresponding to the emission areas, respectively ([col 12 lines 52-55] “A first light emitting element electrode LDE1 may be connected to the second connection pattern CNP2 through an opening portion of the second via film VIA2. Here, the first light emitting element electrode LDE1 may be an anode” ).
As to claim 5, the Park/Jin combination device teaches the display device of claim 3, wherein
the encapsulation layer ([col 14 line 19] encapsulation film TFE + Fig. 5 DAM ) comprises: a first encapsulation layer (Fig 5 ENC1) disposed in the main region, covering the light emitting element layer (light emitting film EML, LDE1 and LDE2) and the at least one dam portion (Fig 5, DAM1/DAM2), and containing the inorganic insulating material ([col 14 lines 24-26] “The first to third encapsulation films ENC1, ENC2 and ENC3 may be formed of an organic material and/or an inorganic material.);
a second encapsulation layer (Fig 5 ENC2) disposed on the first encapsulation layer (Fig 5 ENC1), overlapping the light emitting element layer, and containing the organic insulating material; and
a third encapsulation layer (Fig 5 ENC3) covering the second encapsulation layer (Fig 5 ENC2) and containing the inorganic insulating material, wherein the second encapsulation layer (Fig 5 ENC2) is disposed in an area surrounded by the at least one dam portion (Fig 5, DAM1/DAM2) in the main region,
the first encapsulation layer (Fig 5 ENC1) is in contact with the third insulating layer (Fig 5 ENC3) in the junction area, and the third encapsulation layer (Fig 5 ENC3) is in contact with the first encapsulation layer (Fig 5 ENC1) in the junction area.
As to claim 6, the Park/Jin combination device teaches the display device of claim 5, wherein
the light emitting element layer (light emitting film EML, LDE1 and LDE2) comprises: anode electrodes (col 12 line 55-56, LDE1 may be an anode of the light emitting element) disposed on the fifth insulating layer (5th insulating layer VIA2) of the circuit layer and corresponding to the emission areas, respectively; ([col 13 line 57-63] “The second light emitting element electrode LDE2 may be used as a cathode or an anode according to an embodiment. When the first light emitting element electrode LDE1 is an anode, the second light emitting element electrode LDE2 may be used as a cathode. When the first light emitting element electrode LDE1 is a cathode, the second light emitting element electrode LDE2 may be used as an anode.”)
a pixel defining layer (Fig. 5, [col 13 line 3] pixel definition layer PDL) disposed on the fifth insulating layer(5th insulating layer VIA2) of the circuit layer, corresponding to a non-emission area which is a separation area between the emission areas, and covering an edge of each of the anode electrodes (Fig. 5);
a spacer layer disposed on a part of the pixel defining layer ([col 16 line 23-24 “a spacer is formed on the pixel definition layer PDL”);
first common layers (col 13 lines 36-46 “The light emitting film EML may be provided as a single-layer, but may be provided as multiple layers including various functional layers”) disposed on the anode electrodes, respectively;
light emitting layers (light emitting film EML, LDE1 and LDE2) disposed on the first common layers, respectively;
a second common layer disposed on the pixel defining layer, the spacer layer, and the light emitting layers (light emitting film EML, LDE1 and LDE2); and
a cathode electrode disposed on the second common layer, wherein each of the light emitting elements comprises a structure in which a corresponding first common layer, a corresponding light emitting layer, and the second common layer are disposed between a corresponding anode electrode and the cathode electrode facing each other. (col 13 lines 36-46 “When the light emitting film EML is multiple layers, the light emitting film EML may have a structure in which a hole injection layer (“HIL”), a hole transport layer (“HTL”), an emission layer (“EML”), an electron transport layer (“ETL”), an electron injection layer (“EIL”), and the like are stacked in a single or composite structure.”)
Claim(s) 9-17, and 19 is/are rejected 35 U.S.C. 103 as being unpatentable over Park et al. (US 11199871) herein referred to as Park (Fig 1 and 5), in view of Jin et al. (US 10014490) herein referred to as Jin. (Fig. 1A) and further in view of Lee et al. (US 20210159288).
As to claim 9, the Park/Jin combination device teaches a method for manufacturing a display device, comprising: providing
a substrate ([col 10 line 43] substrate SUB) comprising a main region comprising a display area ([col 13 line 55-56] display area DA) in which emission areas are arranged and
a non-display area ([col 5 line 41] non-display area NDA) disposed around the display area ([col 5 line 40] display area DA), and
a sub-region ([col 8 line 26] second bending area BA2) protruding from one side of the main region; and disposing
a circuit layer ([col 12 line 7] first insulating film group ING1) comprising pixel drivers corresponding to the emission areas, respectively, on the substrate (substrate SUB), wherein the
disposing of the circuit layer ([col 12 line 7] first insulating film group ING1) comprises: disposing a semiconductor layer ([col 10 lines 57-61] substrate SUB has a multilayer structure, inorganic material(s) such as silicon nitride, silicon oxide, and/or silicon oxynitride may be interposed between a plurality of layers as a single-layer or as a plurality of layers) on the substrate ([col 10 line 43] substrate SUB); disposing
a first insulating layer (1st insulating layer GI1) covering the semiconductor layer on the substrate; disposing
a first conductive layer (1st conductive layer GE) on the first insulating layer; disposing
a second insulating layer (2nd insulating layer GI2) covering the first conductive layer on the first insulating layer; disposing
a second conductive layer (2nd conductive layer UE +LE) on the second insulating layer; disposing
a third insulating layer (3rd insulating layer ILD) covering the second conductive layer on the second insulating layer; disposing
a third conductive layer (3rd conductive layer CNP1) on the third insulating layer; disposing
a fourth insulating layer (4th insulating layer VIA1) covering the third conductive layer on the third insulating layer; disposing
a fourth conductive layer (4th conductive layer CNP2) on the fourth insulating layer; and disposing
a fifth insulating layer (5th insulating layer VIA2) covering the fourth conductive layer on the fourth insulating layer, wherein
the non-display area ([col 5 line 41] non-display area NDA) comprises a dam area [col 16, line 6] The dam DAM, DAM1 and DAM2) spaced apart from the display area (display area DA) and in which at least one dam portion (DAM1 / DAM2) surrounding the display area is arranged, and
a junction area (area outside DAM area) surrounding the dam area (area around DAM1 / DAM2), in the disposing of the fourth insulating layer (4th insulating layer VIA1) ,
The Park/Jin combination does not appear to expressly disclose “ the fourth insulating layer comprises a first planarization layer disposed in the display area” and “in the disposing of the fifth insulating layer, the fifth insulating layer comprises a second planarization layer covering the first planarization layer,”
Lee et al. discloses in [0025] “The plurality of insulating layers may include a first insulating layer disposed on the substrate, a second insulating layer disposed on the first insulating layer, a third insulating layer disposed on the second insulating layer, a fourth insulating layer disposed on the third insulating layer, and a fifth insulating layer disposed on the fourth insulating layer, and the plurality of planarization layer may include a first planarization layer disposed on the fifth insulating layer and a second planarization layer disposed on the first planarization layer.”
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to have the an insulating layer comprise a first planarization layer disposed in the display area and to have another insulating layer comprising a second planarization layer covering the first planarization layer in the Park device, such as is in the Lee device. Having a planarization layers on insulating layers in semiconducting devices is obvious so as to flatten uneven topography caused by previous etching/deposition steps. This critical process enables high-resolution photolithography, prevents electrical shorts, ensures consistent dielectric thickness, and improves overall manufacturing yield.
As to claim 10, the Park/Jin/Lee combination device does not appear to expressly disclose the method of claim 9, wherein
“the removing of the temporary protective layer is performed before the disposing of the fifth insulating layer”.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to remove the temporary protective layer before the disposing of the fifth insulating layer. Removing a mask (photoresist or hard mask) during semiconductor fabrication is a critical step, often known as "strip" or "clean," performed primarily to prevent device contamination, remove temporary, sacrificial layers that protect the layers during processing, and allow for subsequent, different processing steps. Removing of the temporary protective layer before the disposing of the fifth insulating layer prevents contamination of subsequent layers.
As to claim 11, the Park/Jin/Lee combination device does not appear to expressly disclose the method of claim 9, wherein
“the removing of the temporary protective layer is performed after the disposing of the fifth insulating layer”.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to remove the temporary protective layer after the disposing of the fifth insulating layer. Removing a mask (photoresist or hard mask) after semiconductor fabrication is a critical step, because it is a temporary, sacrificial structure used only to define specific patterns steps. Removing of the temporary protective layer after the disposing of the fifth insulating layer prevents contamination of subsequent layers, ensures proper electrical functionality, and prepares the wafer surface for subsequent manufacturing steps, such as depositing new layers or doping.
As to claim 12, , Park/Jin/Lee teaches the method of claim 9, wherein the sub-region comprises
a bending area which is bendable ([col 8 lines 41-42] …”first to third bending areas BA1, BA2, and BA3 do not overlap with each other.),
a first sub-region (Annotated 1st sub region) disposed between a first side (Annotated 1st side) of the bending area and the main region, and
a second sub-region (Annotated 1st sub region) connected to a second side (Annotated 2nd side) of the bending area opposite to the first side, and
forming a bending hole corresponding to the bending area and penetrating the first insulating layer (1st insulating layer GI1), the second insulating layer (2nd insulating layer GI2), and the third insulating layer (3rd insulating layer ILD).
Park does not appear to expressly disclose “the disposing of the circuit layer ([col 12 line 7] first insulating film group ING1) further comprises, before the disposing of the third conductive layer (3rd conductive layer CNP1),
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to dispose the circuit layer before the disposing of the third conductive layer so as to provide a substrate for the deposition of the third conductive layer. Subsequent layering in semiconductor fabrication is well known. In the instant case, it has not been shown that the order of deposition would result in unexpected results. Furthermore, the Applicant has not shown that disposing of the circuit layer, before the disposing of the third conductive layer is novel and would not have been found through routine experimentation.
Nonetheless, it would have been obvious to one having ordinary skill in the art at the time the invention was made to provide a substrate for the third conductive layer so as to be able to ensures proper electrical functionality, and prepare the surface for subsequent manufacturing steps, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233. )
As to claim 13, Park/Jin/Lee teaches the method of claim 12, further comprising:
disposing a light emitting element layer on the circuit layer; disposing an encapsulation layer on the light emitting element layer; disposing a touch sensor layer on the encapsulation layer ([col 7 lines 16-21] “The pads PDE1 and PDE3 may be connected to the sensing electrodes SC1 and SC2 positioned above the encapsulation film through the sensing wires IST1 and IST2. The pads PDE1 and PDE3 may be connected to an external touch integrated chip (“IC”).”); and
disposing of the light emitting element layer ([col 13 line36] the light emitting film EML, LDE1 and LDE2), the light emitting element layer comprises: anode electrodes disposed on the fifth insulating layer of the circuit layer and corresponding to the emission areas, respectively ([col 12 lines 52-55] “A first light emitting element electrode LDE1 may be connected to the second connection pattern CNP2 through an opening portion of the second via film VIA2. Here, the first light emitting element electrode LDE1 may be an anode” );
a pixel defining layer (Fig. 5, [col 13 line 3] pixel definition layer PDL) disposed on the fifth insulating layer of the circuit layer, corresponding to a non-emission area which is a separation area between the emission areas, and covering an edge of each of the anode electrodes;
first common layers disposed on the anode electrodes, respectively (col 13 lines 36-46 “The light emitting film EML may be provided as a single-layer, but may be provided as multiple layers including various functional layers”);
light emitting layers disposed on the first common layers, respectively;
a second common layer disposed on the pixel defining layer and the light emitting layers (col 13 lines 36-46 “When the light emitting film EML is multiple layers, the light emitting film EML may have a structure in which a hole injection layer (“HIL”), a hole transport layer (“HTL”), an emission layer (“EML”), an electron transport layer (“ETL”), an electron injection layer (“EIL”), and the like are stacked in a single or composite structure.” Fig. 5) ; and
a cathode electrode disposed on the second common layer, wherein each of the light emitting elements comprises a structure in which a corresponding first common layer, a corresponding light emitting layer, and the second common layer are disposed between a corresponding anode electrode and the cathode electrode facing each other (col 13 lines 36-46 “When the light emitting film EML is multiple layers, the light emitting film EML may have a structure in which a hole injection layer (“HIL”), a hole transport layer (“HTL”), an emission layer (“EML”), an electron transport layer (“ETL”), an electron injection layer (“EIL”), and the like are stacked in a single or composite structure.” Fig. 5) .
Park does not appear to expressly disclose "a polarization layer overlapping the light emitting element layer on the touch sensor layer”. However, it is well known in the art of displays, to improve contrast in the display region through the use of a polarized layer or polarizer, which acts as an optical filter allowing light waves oscillating in a specific direction to pass through, while blocking others.
Jin does teach in Fig. 1A (prior art) a structure schematic diagram of the display panel comprising a base plate 100 on the sealing thin film transistor layer 200, and a thin film transistor layer 200 on the organic light emitting layer 300. The organic light emitting layer 300 of the packaging layer 400, is arranged in the packaging, the polarization layer 500 is arranged on layer 400, and a polarizing covering is arranged on the window layer 500, wherein the polarization layer 500 when combined with the Park device such as in the Jin device would overlap the light emitting element layer on the touch sensor layer.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to provide a polarization layer overlapping the light emitting element layer on the touch sensor layer of the Park device improving contrast so as to use an industrially tested and accepted device.
As to claim 14, the Park/Jin/Lee combination teaches the method of claim 13, wherein the circuit layer comprises:
data lines for transmitting a data signal to the pixel drivers; and data connection lines disposed in the non-display area, electrically connected to the data lines, respectively, and extending to the first sub-region ([col 27 line 32] data line Dj) ([col 27 line 32] signal line Dj (D1,D2,D3) Fig 27),
each of the pixel drivers ([col 7 lines 23] driver of the pixel) of the circuit layer comprises two or more transistors and at least one capacitor,
in the disposing of the semiconductor layer, the semiconductor layer comprises active layers of the transistors ([col 10 lines 40-42] “In FIG. 5, for convenience of description, one transistor, one light emitting element, and one capacitor Cst are shown for one pixel PX as an example” and [col 26 lines 13-15] “FIG. 28, the pixel PXij includes transistors T1, T2, T3, T4, T5, T6, and T7, a storage capacitor Cst, and a light emitting diode LD.”)
in the disposing of the first conductive layer (Fig. 5, 1st conductive layer GE), the first conductive layer further comprises gate electrodes of the transistors ([col 26 lines 34-65 and col 27 lines 1-9] transistors comprise gate electrodes), and some of the data connection lines,
in the disposing of the second conductive layer (2nd conductive layer UE + LE), the second conductive layer further comprises a first capacitor electrode of the capacitor, and remaining others of the data connection lines ([col 26 lines 34-65 and col 27 lines 1-9] transistors comprise gate electrodes),,
in the disposing of the third conductive layer ( 3rd conductive layer ILD), the third conductive layer comprises source electrodes of the transistors and drain electrodes of the transistors , ([col 12 lines 11-12] “The first connection pattern CNP1 may be positioned on the interlayer insulating film ILD. The first connection pattern CNP1 may be in contact with each of a source electrode and a drain electrode of the active film ACT” ), and
in the disposing of the fourth conductive layer (4th conductive layer CNP2), the fourth conductive layer further comprises anode connection electrodes corresponding to the emission areas ([col 12 lines 52-55] “A first light emitting element electrode LDE1 may be connected to the second connection pattern CNP2 through an opening portion of the second via film VIA2. Here, the first light emitting element electrode LDE1 may be an anode” )., respectively.
As to claim 15, the Park/Jin/Lee combination teaches the method of claim 14, wherein
in the disposing of the fourth insulating layer, the temporary protective layer overlaps a part of the data connection lines.
Park does not appear to expressly disclose “the temporary protective layer overlaps a part of the data connection lines,”
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to have a temporary protective layer overlaps a part of the data connection lines. Having temporary “mask layers” is obvious so as to protect unetched areas. Temporary masking layers serve as master stencils during photolithography, allowing high-throughput, precise transfer of complex circuit patterns onto silicon wafers. As shown in Fig. 5, a temporary layer was obviously used to protect the data connection lines.
As to claim 16, the Park/Jin/Lee combination teaches the method of claim 15, wherein
in the disposing of the encapsulation layer ([col 14 line 19] encapsulation film TFE + Fig. 5 DAM ), the encapsulation layer comprises:
a first encapsulation layer (Fig 5 ENC1) disposed in the main region, covering the light emitting element layer and the at least one dam portion, and containing the inorganic insulating material;
a second encapsulation layer (Fig 5 ENC2) disposed on the first encapsulation layer, overlapping the light emitting element layer, and containing the organic insulating material; and
a third encapsulation layer (Fig 5 ENC3) covering the second encapsulation layer and containing the inorganic insulating material, wherein
the second encapsulation layer is disposed in an area surrounded by the at least one dam portion (Fig 5, DAM1/DAM2) in the main region,
the first encapsulation layer is in contact with the third insulating layer (3rd insulating layer ILD) in the junction area, and
the third encapsulation layer (Fig 5 ENC3) is in contact with the first encapsulation layer (Fig 5 ENC1) in the junction area.
As to claim 17, the Park/Jin/Lee combination teaches the method of claim 16, wherein
in the disposing of the polarization layer.
Park does not appear to expressly disclose " the polarization layer extends to the non-display area and further overlaps the data connection lines of the non-display area”. It is well known in the art of displays to improve contrast in the display region through the use of a polarized layer or polarizer, which acts as an optical filter allowing light waves oscillating in a specific direction to pass through, while blocking others.
However, Jin does teach in Fig. 1A (prior art) a structure schematic diagram of the display panel comprising a base plate 100 on the sealing thin film transistor layer 200, and a thin film transistor layer 200 on the organic light emitting layer 300. The organic light emitting layer 300 of the packaging layer 400, is arranged in the packaging, the polarization layer 500 is arranged on layer 400, and a polarizing covering is arranged on the window layer 500, wherein the polarization layer extends beyond the active display area into the non-display area (border or bezel region) to cover or overlap with the data connection lines, driving circuits, or fan-out wiring. The extended polarization layer also acts as a protective barrier.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to provide a polarization layer that extends to the non-display area and further overlaps the data connection lines of the non-display area of the Park device as in the Jin device to create a more compact design of the non-display as an improved design choice.
As to claim 19, the Park/Jin/Lee combination teaches the method of claim 14, wherein
each of the at least one dam portion (Fig. 5, DAM1 / DAM2) comprises a structure in which two or more dam layers are stacked, and
each of the two or more dam layers is a same layer as any one of the fourth insulating layer (Fig. 5, 4th insulating layer VIA1), the fifth insulating layer (5th insulating layer VIA2), the pixel defining layer (Fig. 5, [col 13 line 3] pixel definition layer PDL), and the spacer layer ([col 16 line 23-24 “a spacer is formed on the pixel definition layer PDL”).
Allowable Subject Matter
Claim(s) 7, 18, and 20 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art taken either singularly or in combination, fails to anticipate or fairly suggest the limitations of the claims listed above in such a manner that a rejection under 35 U.S.C. 102 or 103 would be proper. The prior art fails to teach a combination of all of the features in the claims. The closest prior art is Park et al. (US 11199871) herein referred to as Park (Fig 1, 5 and 11), in view of Jin et al. (US 10014490) herein referred to as Jin
The Park/Jin combination teaches:
As to claim 7, the display device of claim 6, further comprising:
data bending lines disposed in the bending area, electrically connected to the data connection lines (Fig. 28 line T2 connects Dj to INTL), respectively, and extending to the second sub-region (Annotated Fig. 1 Park);
a bending hole (col 17 line1 first trench TCH1 ) defined in the bending area and penetrating the first insulating layer (1st insulating layer GI1), the second insulating layer (2nd insulating layer GI2), and the third insulating layer (3rd insulating layer ILD); and
a bank covering the bending hole and extending to the first sub-region; wherein
the bank comprises: a first bank layer which is a part of the fourth insulating layer (4th insulating layer VIA1) and covers the bending hole;
The Park/Jin combination does not teach:
a second bank layer which is a part of the fifth insulating layer (5th insulating layer VIA2) and covers the first bank layer;
a third bank layer, which is a same layer as the pixel defining layer and disposed on the second bank layer; and
a fourth bank layer, which is a same layer as the spacer layer and disposed on the third bank layer; wherein
the fourth conductive layer (4th conductive layer CNP2) further comprises the data bending lines, the data bending lines are disposed on the first bank layer and covered with the second bank layer,
each of the at least one dam portion comprises a structure in which two or more dam layers are stacked,
each of the two or more dam layers is a same layer as any one of the fourth insulating layer (4th insulating layer VIA1), the fifth insulating layer (5th insulating layer VIA2), the pixel defining layer, and the spacer layer, and the polarization layer (component 500 of Fig. 1A Jin) extends to the first sub-region and overlaps a part of the bank.
The Park/Jin/Lee combination teaches:
As to claim 18, the Park/Jin combination teaches the method of claim 14, wherein
in the disposing of the fourth insulating layer, the fourth insulating layer further comprises a first bank layer covering the bending hole (col 17 line1 first trench TCH1 ) of the bending area, extending to the first sub-region, and spaced apart from the temporary protective layer,
in the disposing of the fourth conductive layer, the fourth conductive layer further comprises data bending lines disposed in the bending area, electrically connected to the data connection lines, respectively, and extending to the second sub-region,
See [col 14 line 67 and col15 lines 1-7]. “The first via film VIA1, the second via film VIA2 (5th insulating layer VIA2) and the pixel definition film PDL, which are formed of an organic material, do not extend continuously to the non-display area NDA, and may be covered by the first encapsulation film ENC1”. Therefore, the Park/Jin combination does not teach for example the rest of the claim 18 limitations:
in the disposing of the fifth insulating layer, the fifth insulating layer further comprises a second bank layer covering the first bank layer and the data bending lines,
in the disposing of the light emitting element layer,
a third bank layer which is a same layer as the pixel defining layer and disposed on the second bank layer, and
a fourth bank layer which is a same layer as the spacer layer and disposed on the third bank layer are provided.
The Park/Jin/Lee combination teaches:
As to claim 20, the Park/Jin/Lee combination teaches the method of claim 14, wherein
in the providing of the substrate ([col 10 line 43] substrate SUB),
The Park/Jin/Lee combination does not teach:
the substrate further comprises a hole area surrounded by the main region, and
a hole periphery area disposed between the main region and the hole area, and
the method further comprising, after the disposing of the polarization layer,
forming a through portion corresponding to the hole area, and penetrating the substrate, the circuit layer, the light emitting element layer, the encapsulation layer, and the polarization layer.
The remaining claims 8 and 21-23, are allowable at least because they depend from allowable claims 7 and 20 respectively.
Conclusion
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/SHAWN SHAW MUSLIM/Examiner, Art Unit 2897
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