DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 and 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (2021/0242158) in view of Yu et al. (2019/0333893).
Regarding claims 1 and 11, Lee (Fig. 24) discloses a semiconductor package, comprising: a re-distribution layer (RDL) interposer 100 having a first surface and a second surface opposite to the first surface ([0046]); a plurality of fanout pads (114/124) disposed on the second surface of the RDL interposer 100 ([0046]); a plurality of peripheral pads (114, 116) disposed on the second surface and arranged along a perimeter of the RDL interposer 100 (Figs. 19-22, [0044]); a first semiconductor die 200 disposed on the first surface of the RDL interposer 100 and electrically connected to the plurality of fanout pads 114 ([0042]); a molding compound 300 encapsulating the first semiconductor die 200 and the first surface of the RDL interposer ([0060]), wherein a top surface of the molding compound 300 is coplanar with a rear surface of the first semiconductor die 200 (Fig. 22); a plurality of through mold vias 420 disposed in the molding compound 300 around the first semiconductor die 200, wherein the plurality of through mold vias 420 exposes the plurality of peripheral pads (114, 116) (Figs. 18-19), respectively; a plurality of peripheral solder bumps 410 disposed within the plurality of through mold vias 420 and placed directly on the plurality of peripheral pads (114, 116) (Fig. 24, [0042]), respectively; a plurality of through via pads 516 disposed on the rear surface of the first semiconductor die 200 ([0027]); and a second semiconductor die 620 bonded to the plurality of through via pads of the first semiconductor die 200 and bonded to the plurality of peripheral solder bumps 410 within the plurality of through mold vias 420 (see Fig. 24, [0069]).
Lee all the claimed limitations of the invention except for a plurality of through silicon via (TSV) pads.
However, Yu (Fig. 9) discloses a plurality of through silicon via (TSV) pads 208 disposed on the rear surface of the first semiconductor die 102 in order to provide additional electrical connections between dies 102 and/or 104 ([0073]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the device of Lee as taught by Yu by forming a plurality of through silicon via (TSV) pads disposed on the rear surface of the first semiconductor die in order to provide additional electrical connections between dies (Fig. 9, [0073]).
Regarding claims 2 and 12, Lee (Fig. 24) discloses wherein the plurality of peripheral pads (114, 116) surrounds the plurality of fanout pads 114.
Regarding claims 3 and 13, as discussed, the combination above, Yu (Fig. 9) discloses wherein the second semiconductor die 104B is bonded to the plurality of TSV pads 208 of the first semiconductor die 102 through a plurality of first connecting elements 602 ([0077]).
Regarding claims 4 and 14, as discussed, the combination above, Yu (Fig. 9) discloses wherein the plurality of first connecting elements 602 comprises micro-bumps ([0077]).
Allowable Subject Matter
Claims 5-10 and 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record fails to disclose all the limitations recited in the claim 5. Specifically, the prior art of record fails to disclose wherein the second semiconductor die is bonded to the plurality of peripheral solder bumps within the plurality of through mold vias through a plurality of second connecting elements having a diameter greater than a diameter of each of the plurality of first connecting elements.
The dependent claims being further limiting and definite are also allowable.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THERESA T DOAN whose telephone number is (571)272-1704. The examiner can normally be reached on Monday, Tuesday, Wednesday and Thursday from 7:00AM - 3:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WAEL FAHMY can be reached on (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/THERESA T DOAN/ Primary Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814