DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendments necessitated the shift in grounds of rejection detailed below. The shift in grounds of rejection renders Applicant’s arguments moot.
Applicant argues the Chen reference does not qualify as prior art under 102b2c because the issued patent 11621265 was published after the effective filing date of the present application. Examiner respectfully disagrees. Patent 11621265 was not cited in the rejection. Publication US-20210351187-A1, published November 21, 2021 was cited in the rejection. Accordingly November 21, 2021 was published more than a year before the effective filing date.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 2 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 2 and 15 recites the limitation "metal layer". There is insufficient antecedent basis for this limitation in the claim. Examiner believes the applicant intends “metal plug” instead of “metal layer”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10,12,13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US-20210351187-A1; Chen) in view of Liu et al. (CN-114373764-A; Liu) and further in view of Su (US-20210335792-A1; Su).
Regarding claim 1, A semiconductor structure, comprising: a substrate (Fig. 25,101; ¶59), comprising a first active area (Fig. 19, 105; ¶60) and a second active area (Fig. 19, second 105; ¶60); a plurality of first dielectric structures (Fig. 20, 103; ¶60), disposed in the substrate, wherein the first active area is disposed between the plurality of first dielectric structures; a plurality of second dielectric structures (Fig. 20,103; ¶60 not shown associated with second 105 of Fig. 19), disposed in the substrate, wherein the second active area is disposed between the plurality of second dielectric structures; a capacitor contact (Fig. 25, 403; ¶77), disposed over and in contact with the first active area; a landing pad (Fig. 25, 810; ¶83), disposed over the capacitor contact, wherein the landing pad comprises a first silicide layer (Fig. 25, 808A; ¶84) disposed over the capacitor contact and a second silicide layer (Fig. 25, 808B; ¶84) surrounding the first silicide layer; a metal plug (Fig. 26, 816; ¶85), disposed over the landing pad…; wherein the first active area and the plurality of first dielectric structures are arranged along a first direction (x), the second active area and the plurality of second dielectric structures are arranged along the first direction, and the first active area is misaligned with the second active area along a second direction perpendicular (y) to the first direction.
Chen is silent on and a dielectric segment, disposed in the substrate, extended along the first direction, wherein the first active area and the second active are separated by the dielectric segment along the second direction; wherein a width of the metal plug is larger than a width of the first silicide layer;
Liu discloses a semiconductor structure comprising a first (Fig. 4a, 102; ¶133) and second (Fig. 4a, 102; ¶133) active layers arranged in a first direction (z) and separated by a dielectric segment (Fig. 4a, 103; ¶133) extending in a second direction (y)
Su discloses a semiconductor structure comprising a capacitor plug (Fig. 24, 149; 179) and a self-aligned landing pad (Fig. 24, 155; 179) wherein a metal plug (Fig. 24, 159; ||79/81) disposed over the landing pad is wider than a first silicide layer (Fig. 24, 153A; 179).
Su discloses a metal plug formed over the landing pad in paragraph 81, but mislabels it as 149 instead of 159.
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to widen the metal plug for providing a larger contact surface coupled to top surfaces of the first and second silicide layers and being aligned with sidewalls of lower plugs.
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to separate active regions by a dielectric segment for defining array (memory or diode) regions and preventing cross talk.
Regarding claim 2, Chen in view of Liu and Su discloses the semiconductor structure of claim 1, wherein the landing pad comprises: a contact plug (Fig. 25, 411A/412A; ¶83 Chen), disposed over and in contact with the capacitor contact (Fig. 25, 403; ¶77 Chen); and a barrier layer (Fig. 25, 412A; ¶83 Chen), attached to a sidewall of the contact plug; wherein the first silicide layer (Fig. 25, 808A; ¶83 Chen) is in contact with the contact plug; and wherein the second silicide layer (Fig. 25, 808B; ¶83 Chen) is in contact with a sidewall of the barrier layer, wherein the metal layer (metal plug) (Fig. 24, 159; ¶79/81 Su) is in contact with a top surface of the first silicide layer (Fig. 24, 153A; ¶79 Su) and a top surface of the second silicide layer (Fig. 24, 153B; ¶79 extending over a portion of first silicide layer 153A Su).
Su discloses a metal plug formed over the landing pad in paragraph 81, but
mislabels it as 149 instead of 159.
Before the effective filing date of the invention it would have been obvious to one
of ordinary skill in the art to widen the metal plug for providing a larger contact surface coupled to top surfaces of the first and second silicide layers and being aligned with sidewalls of lower plugs.
Regarding claim 3, Chen in view of Liu and Su discloses the semiconductor structure of claim 2, wherein a height of the second silicide layer (Fig. 25, 808B; ¶8,83 Chen) is greater than a height of the first silicide layer (Fig. 25, 808A; ¶8,83 Chen), and the first silicide layer and the second silicide layer are made of different materials.
Regarding claim 4, Chen in view of Liu and Su discloses the semiconductor structure of claim 2, further comprising: a first insulating film (Fig. 25, 801; ¶67 Chen), disposed over the substrate (Fig. 25,101; ¶59 Chen) and in contact with the first active area (Fig. 25, 105; ¶60 Chen), the second active area (Fig. 25, second 105; ¶60 Chen), the plurality of first dielectric structures (Fig. 20, 103; ¶60 Chen), and the plurality of second dielectric structures (Fig. 20,103; ¶60 not shown associated with second 105 of Fig. 19 Chen); a second insulating film (Fig. 25, 803; ¶70 Chen), disposed over the first insulating film; and a third insulating film (Fig. 25, 805; ¶74 Chen), disposed over the second insulating film.
Regarding claim 5, Chen in view of Liu and Su discloses the semiconductor structure of claim 4, wherein the capacitor contact (Fig. 25, 403; ¶77 Chen) comprises: a neck portion, (Fig. 25, 403-1; ¶78 Chen) in contact with the first active area (Fig. 25, 105; ¶60 Chen), the first insulating film (Fig. 25, 801; ¶67 Chen), and the second insulting film (Fig. 25, 803; ¶70 Chen); and a head portion (Fig. 25, 403-2; ¶78 Chen), over the neck portion and in contact with the third insulating film. (Fig. 25, 805; ¶74 Chen)
Regarding claim 6, Chen in view of Liu and Su discloses the semiconductor structure of claim 5, wherein a width of the head portion (Fig. 25, 403-2; ¶78 Chen) is greater than a width of the neck portion (Fig. 25, 403-1; ¶78 Chen), and the head portion has a curved sidewall.
Regarding claim 9, Chen in view of Liu discloses the semiconductor structure of claim 2, further comprising: a fourth insulating film (Fig. 25, 807; ¶74 Chen), disposed over the substrate (Fig. 25,101; ¶59 Chen) and in contact with the barrier layer (Fig. 25, 412A; ¶83 Chen), the second silicide layer, and the capacitor contact.
Regarding claim 10, Chen in view of Liu discloses the semiconductor structure of claim 9, wherein the contact plug (Fig. 25, 411A/412A; ¶83 Chen) and the barrier layer (Fig. 25, 412A; ¶83 Chen) protrude from a top surface of the fourth insulating film. (Fig. 25, 807; ¶80 Chen)
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US-20210351187-A1; Chen) in view of Liu et al. (CN-114373764-A; Liu) , Su (US-20210335792-A1; Su), and further in view of Yu et al. (CN-113488472-A; Yu).
Regarding claim 11, Chen in view of Liu and Su discloses the semiconductor structure of claim 1, but is silent on wherein the first active area protrudes towards a concave portion of an adjacent first dielectric structure of the plurality of first dielectric structures.
This claim is about the shape of the claimed first dielectric structure.
Yu discloses a semiconductor structure where an active area (Fig. 5, 202) protrudes towards a concave portion of an adjacent first dielectric structure (Fig. 5, 210)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to have a concave portion to in the first dielectric to extend the length of the active region.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US-20210351187-A1; Chen) in view of Su (US-20210335792-A1; Su).
Regarding claim 14, A method for manufacturing a semiconductor structure, comprising: forming a first active area (Fig. 19, 105; ¶60) and a second active area (Fig. 19, second 105; ¶60) in a substrate (Fig. 25,101; ¶59); forming a plurality of first dielectric structures (Fig. 20, 103; ¶60 not shown in Fig. 19), wherein the first active area is disposed between the plurality of first dielectric structures; forming a plurality of second dielectric structures (Fig. 20, not shown second 103; ¶60 not shown in Fig. 19), wherein the second active area is disposed between the plurality of second dielectric structures; forming a capacitor contact (Fig. 25, 403; ¶77) over the first active area; and forming a landing pad (Fig. 25, 810; ¶83) over the capacitor contact, wherein the landing pad comprises a contact plug (Fig. 25, 411A/412A; ¶83), a barrier layer (Fig. 25, 412A; ¶83), a first silicide layer, (Fig. 25, 808A; ¶83) and a second silicide layer, (Fig. 25, 808B; ¶83) wherein the contact plug is disposed over and in contact with the capacitor contact, the barrier layer is attached to a sidewall of the contact plug, the first silicide layer is disposed over and in contact with the contact plug, and the second silicide layer is disposed over the contact plug and the barrier layer, in contact with a sidewall of the barrier layer, wherein the first active area and the plurality of first dielectric structures are arranged along a first direction (x), the second active area and the plurality of second dielectric structures are arranged along the first direction,(x) and the first active area is misaligned with the second active area along a second direction (y) perpendicular to the first direction.
Chen is silent on wherein a top surface of the second silicide layer is a flat surface
Su discloses wherein a top surface of the second silicide layer (Fig. 24, 153B; ¶79 extending over a portion of first silicide layer 153A Su) is a flat surface;
Applicant disclose the flat surface is a result of planarizing another layer, and not for any particular purpose. The applicant has not presented persuasive evidence in Spec. that the claimed flat surface is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed dimensions). Also, the applicant has not shown that the claimed flat surface would produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art."
Therefore, before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to have a flat top surface of the second silicide layer for optimal alignment and because where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. MPEP 2144.04 IV A
Allowable Subject Matter
Claims 12-13 and 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 13 is objected to due to its dependence on claim 12.Claims 16-20 are objected to due to their dependence on claim 15.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
Regarding claim 12, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " wherein the patterned mask has a through opening; wherein the second silicide layer is extended through the through opening of the patterned mask at a position that the top surface of the second silicide layer is exposed from a top surface of the patterned mask; wherein the top surface of the pattern mask is coplanar with the top surface of the second silicide layer; wherein the top surface of the first silicide layer is below the top surface of the pattern mask.”, as recited in Claim 12, with the remaining features.
Regarding claim 15, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " wherein the first insulating film, the second insulating film, and the third insulating film are disposed between the substrate and the patterned mask; and forming a metal plug over the landing pad within the through hole of the patterned mask, wherein a width of the metal plug is larger than a width of the first silicide layer; … wherein the second silicide layer is extended through the through opening of the patterned mask at a position that the top surface of the second silicide layer is exposed from a top surface of the patterned mask”, as recited in Claim 15, with the remaining features.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAWRENCE C TYNES JR. whose telephone number is (571)270-7606. The examiner can normally be reached 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAWRENCE C TYNES JR./Examiner, Art Unit 2899
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