Prosecution Insights
Last updated: October 04, 2026
Application No. 18/540,531

Asymmetric MOSFET Devices

Non-Final OA §103
Filed
Dec 14, 2023
Examiner
MAZUMDER, DIDARUL A
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
pSemi Corporation
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
647 granted / 748 resolved
+18.5% vs TC avg
Moderate +8% lift
Without
With
+7.8%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
41 currently pending
Career history
768
Total Applications
across all art units

Statute-Specific Performance

§103
58.7%
+18.7% vs TC avg
§102
25.1%
-14.9% vs TC avg
§112
11.5%
-28.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 748 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION This action is responsive to application No. 18/540,531 filed on July 21, 2026. Information Disclosure Statement 3. Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS have been considered. Specification 4. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: “Asymmetric MOSFET Devices Comprising Halo Region and/or Lightly-Doped Drain Region Implanted with Tilted Angles”. Election/Restrictions 5. Applicant’s election of claims 1-5, 7-12, 14-19, 21, w.r.t. device species I (Fig.3A) in the reply filed on 07/21/2026 is acknowledged. Because the applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). 6. Claims 6, 13, 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected device species II (Fig. 3B, there being no allowable generic or linking claim. Claim Objections 7. Claims 3-4, 10-11, 17-18 are objected to because of the following informalities: the claims should be recited as follows to avoid indefiniteness, in addition, to avoid the phrase ‘about’ having no definite limit or boundary: 3. (Currently Amended) The MOSFET of claim 1, wherein a first non-90° twist angle is in a first range of 4. (Currently Amended) The MOSFET of claim 1, including the halo region implanted with the dopant at a first tilt angle, and/or the lightly-doped region implanted with a dopant at a second tilt angle different from the first tilt angle. 10. (Currently Amended) The MOSFET of claim 8, wherein a first non-90° twist angle is in a first range of 11. (Currently Amended) The MOSFET of claim 8, including the halo region implanted with the dopant in the body region only from the source region side of the gate structure at a first tilt angle, and/or the lightly-doped region implanted with a dopant in the body region only from the source region side of the gate structure at a second tilt angle different from the first tilt angle. 17. (Currently Amended) The method of claim 15, wherein implanting is at a first non-90° twist angle in a first range of 18. (Currently Amended) The method of claim 15, wherein implanting includes implanting and/or halo region with and/or dopant only from the source region side of the gate structure at a first tilt angle, and/or implanting and/or lightly-doped region with the dopant only from the source region side of the gate structure at a second tilt angle different from the first tilt angle. Appropriate corrections are needed. Claim Rejections - 35 USC § 103 8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 10. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 11. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: a. Determining the scope and contents of the prior art. b. Ascertaining the differences between the prior art and the claims at issue. c. Resolving the level of ordinary skill in the pertinent art. d. Considering objective evidence present in the application indicating obviousness or non-obviousness. 12. Claims 1-5, 7-12, 14-19, 21 are rejected under 35 U.S.C. 103 as being unpatentable over SON (US 2015/0206874 A1) in view of Mahalingam (US 2022/0399337 A1). Regarding independent claim 1, SON teaches an asymmetric metal-oxide-semiconductor field-effect transistor (Fig. 1) (MOSFET) (nFET, para [0063]) including at least one of a halo region (130, para [0050], [0064], [0065]) and/or lightly-doped drain region implanted with a dopant (p-type dopant/impurity, para [0067]) only from a source region (140, para [0050]) side of a gate structure (110, para [0050]) of the MOSFET. SON is explicitly silent of disclosing wherein, the dopant is implanted at two or more different non-90° twist angles. Mahalingam teaches wherein (Figs. 1C-1D), the dopant is implanted at two or more different non-90° twist angles (2-twist angle, para [0024]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Mahalingam, and while using the tilted ion implantation in the structure of SON, in order to lead to higher current drive and higher performance without higher variability, and lower magnitude of the VT with higher drive current and a further increase in performance (para [0024]). Regarding claim 2, SON and Mahalingam teach all of the limitations of claim 1 from which this claim depends. Mahalingam teaches wherein (Fig. 1C), a first non-90° twist angle (left side) is in a first quadrant (see in figure below) with respect to the gate structure (104b), and a second non-90° twist angle (right side) is in a second quadrant (see in figure below) with respect to the gate structure (104b). PNG media_image1.png 487 634 media_image1.png Greyscale Regarding claim 3, SON and Mahalingam teach all of the limitations of claim 1 from which this claim depends. Mahalingam teaches wherein (Fig. 1C), a first non-90° twist angle (left side) is in a first range of about 0° to about 89° (see figure in claim 2) (para [0030]) and a second twist angle (right side) is in a second range of from about 91° to about 180° (see figure in claim 2). Regarding claim 4, SON and Mahalingam teach all of the limitations of claim 1 from which this claim depends. The combination of SON and Mahalingam discloses, including a halo region (130) implanted with a dopant at a first tilt angle (para [0066], SON), and a lightly-doped region (108, Mahalingam) implanted with a dopant (N+) at a second tilt angle different (para [0055-0057]) from the first tilt angle. Regarding claim 5, SON and Mahalingam teach all of the limitations of claim 1 from which this claim depends. SON teaches wherein (Fig. 1), the gate structure (110) includes a central gate tab (see the annotated figure below) on the source side region (140) of the gate structure (110). PNG media_image2.png 462 498 media_image2.png Greyscale Regarding claim 7, SON and Mahalingam teach all of the limitations of claim 1 from which this claim depends. Mahalingam teaches wherein (Fig. 1C), the dopant (p-type) is also implanted at a 90° twist angle (para [0035]). Regarding independent claim 8, SON teaches an asymmetric metal-oxide-semiconductor field-effect transistor (Fig. 1) (MOSFET) (nFET, para [0063]) including: (a) a source region (140, para [0050]); (b) a drain region (150, para [0050]); (c) a body region (see the annotated figure below) between the source region (140) and the drain region (150); (d) a gate structure (110, para [0050]) overlying the body region, the gate structure (110) having a source region side (left side) and a drain region side (right side); (e) at least one of a halo region (130, para [0050]) or lightly-doped drain region (120) implanted with a dopant (p type, para [0067]) in the body region only from the source region side (140) of the gate structure (110). PNG media_image3.png 431 473 media_image3.png Greyscale SON is explicitly silent of disclosing wherein, the dopant is implanted at two or more different non-90° twist angles. Mahalingam teaches wherein (Figs. 1C-1D), the dopant is implanted at two or more different non-90° twist angles (2-twist angle, para [0024]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Mahalingam, and while using the tilted ion implantation in the structure of SON, in order to lead to higher current drive and higher performance without higher variability, and lower magnitude of the VT with higher drive current and a further increase in performance (para [0024]). Regarding claim 9, SON and Mahalingam teach all of the limitations of claim 8 from which this claim depends. Mahalingam teaches wherein (Fig. 1C), a first non-90° twist angle (left side) is in a first quadrant (see in figure below) with respect to the gate structure (104b), and a second non-90° twist angle (right side) is in a second quadrant (see in figure below) with respect to the gate structure (104b). PNG media_image1.png 487 634 media_image1.png Greyscale Regarding claim 10, SON and Mahalingam teach all of the limitations of claim 8 from which this claim depends. Mahalingam teaches wherein (Fig. 1C), a first non-90° twist angle (left side) is in a first range of about 0° to about 89° (see figure in claim 9) (para [0030]) and a second twist angle (right side) is in a second range of from about 91° to about 180° (see figure in claim 9). Regarding claim 11, SON and Mahalingam teach all of the limitations of claim 8 from which this claim depends. The combination of SON and Mahalingam discloses, wherein including a halo region (130) implanted with a dopant (p-type) in the body region (see figure in claim 8) only from the source region (140) side of the gate structure (110) at a first tilt angle (para [0066], SON), and a lightly-doped region (108, Mahalingam) implanted with a dopant (N+) in the body region only from the source region (140) side of the gate structure (110) at a second tilt angle different (para [0055-0057]) from the first tilt angle. Regarding claim 12, SON and Mahalingam teach all of the limitations of claim 8 from which this claim depends. SON teaches wherein (Fig. 1), the gate structure (110) includes a central gate tab (see the annotated figure below). PNG media_image2.png 462 498 media_image2.png Greyscale Regarding claim 14, SON and Mahalingam teach all of the limitations of claim 8 from which this claim depends. Mahalingam teaches wherein (Fig. 1C), the dopant (p-type) is also implanted at a 900 twist angle (para [0035]). Regarding independent claim 15, SON teaches a method for making an asymmetric metal-oxide-semiconductor field-effect transistor (MOSFET) (nFET, para [0063]) including (Fig. 1) implanting at least one of a halo region (130, para [0050], [0064], [0065]) or lightly-doped drain region (120) with a dopant ((p-type dopant/impurity, para [0067]) only from a source region side (140) of a gate structure (110) of the MOSFET. SON is explicitly silent of disclosing wherein, the dopant is implanted at two or more different non-90° twist angles. Mahalingam teaches wherein (Figs. 1C-1D), the dopant is implanted at two or more different non-90° twist angles (2-twist angle, para [0024]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Mahalingam, and while using the tilted ion implantation in the structure of SON, in order to lead to higher current drive and higher performance without higher variability, and lower magnitude of the VT with higher drive current and a further increase in performance (para [0024]). Regarding claim 16, SON and Mahalingam teach all of the limitations of claim 15 from which this claim depends. Mahalingam teaches wherein (Fig. 1C), implanting is at a first non-90° twist angle (left side) is in a first quadrant (see in figure below) with respect to the gate structure (104b), and a second non-90° twist angle (right side) is in a second quadrant (see in figure below) with respect to the gate structure (104b). PNG media_image1.png 487 634 media_image1.png Greyscale Regarding claim 17, SON and Mahalingam teach all of the limitations of claim 15 from which this claim depends. Mahalingam teaches wherein (Fig. 1C), implanting is at a first non-90° twist angle (left side) is in a first range of about 0° to about 89° (see figure in claim 16) (para [0030]) and a second twist angle (right side) is in a second range of from about 91° to about 180° (see figure in claim 16). Regarding claim 18, SON and Mahalingam teach all of the limitations of claim 15 from which this claim depends. The combination of SON and Mahalingam discloses, wherein implanting includes implanting a halo region (130) with a dopant (p-type) only from the source region (140) side of the gate structure (110) at a first tilt angle (para [0066], SON), and/or implanting a lightly-doped region (108, Mahalingam) implanted with a dopant (N+) only from the source region (140) side of the gate structure (110) at a second tilt angle different (para [0055-0057]) from the first tilt angle. Regarding claim 19, SON and Mahalingam teach all of the limitations of claim 15 from which this claim depends. SON teaches wherein (Fig. 1), the gate structure (110) includes a central gate tab (see the annotated figure below). PNG media_image2.png 462 498 media_image2.png Greyscale Regarding claim 21, SON and Mahalingam teach all of the limitations of claim 15 from which this claim depends. Mahalingam teaches wherein (Fig. 1C), further including implanting the dopant (p-type) at a 90° twist angle (para [0035]). Examiner’s Note 13. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182. Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. Conclusion 14. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. 15. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812
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Prosecution Timeline

Dec 14, 2023
Application Filed
Sep 09, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
94%
With Interview (+7.8%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 748 resolved cases by this examiner. Grant probability derived from career allowance rate.

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