Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18/540,989 filed on June 29, 2026.
Specification
3. The title of the invention has been amended as “Memory Device Comprising Plurality of Memory Cells Incorporating Capacitors and Transistors and Manufacturing Method Thereof”.
Claim Objections
4. The objection of claim 3 has been withdrawn, per the response dated 06/29/2026.
Claim Rejections - 35 USC § 102
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
7. Claims 1-3, 10-11 are rejected under 35 U.S.C. 102(a)(1)/ (a)(2) as¶ being anticipated by Song et al. (US 2018/0174971 A1).
Regarding independent claim 1, Song et al. teaches a manufacturing method of a memory device, comprising (Figs. 4B-11B/11C, para [0047]):
forming bit line structures (116/118/120, para [0058], see Fig. 6B) over a substrate (100, para [0058]);
forming a conductive structure (BC/134/136, see Fig. 9B) between and over the bit line structures (116/118/120), wherein the conductive structure (BC/134/136) exposes (see Fig. 9B) a portion (a portion of 136) of the bit line structures (116/118/120);
forming a spacer (SP1/SP2/ASP, para [0041], Fig. 11B) comprising an air gap (ASP, para [0041]) along sidewalls of the bit line structures (116/118/120); and
forming an isolation structure (137/138a/138b, see Fig. 11B) between the conductive structure (BC/134/136) and one of the bit line structures (116/118/120), wherein the isolation structure (137/138a/138b) comprises a first insulation material layer (138a) sealing the air gap (ASP) and a second insulation material layer (138b) over the first insulation material layer (138a), and the first insulation material layer (138a) and the second insulation material layer (138b) are in contact with the one of the bit line structures (116/118/120).
Regarding claim 2, Song et al. teaches wherein (Figs. 4B-11B/11C, para [0047]), forming the spacer (SP1/SP2/ASP) comprising the air gap (ASP) along the sidewalls of the bit line structures (116/118/120) comprising (Fig. 6B):
sequentially forming a first spacer layer (301, see Fig. 6B), a sacrificial spacer layer (303) and a second spacer layer (305) along the sidewalls of the bit line structures (116/118/120) before forming the conductive structure (BC/134/136, see Fig. 9B); and
removing (see Fig. 9B) the second spacer layer (305) after forming the conductive structure (BC/134/136).
Regarding claim 3, Song et al. teaches wherein (Figs. 4B-11B/11C, para [0047]), forming the conductive structure (BC/134/136) between and over the bit line structures (116/118/120) comprises:
forming a first trench (Fig. 4B) in portions of the substrate (100) that are exposed through the bit line structures;
forming a first conductive layer (BC, see Fig. 8B) in the first trench;
forming a second conductive layer (134, see Fig. 9B) over the first conductive layer (BC);
forming a barrier layer (136) over the second conductive layer (134);
forming a landing pad material layer (LP) overfilling the first trench; and
forming a second trench (Fig. 9B) by removing a portion of the barrier layer (136), a portion of the landing pad material layer (LP) and a portion of the bit line structures (120).
Regarding claim 10, Song et al./971 and Song et al./057 teach all of the limitations of claim 11 from which this claim depends.
Song et al./971 teaches wherein (Figs. 4B-11B/11C), a dielectric constant (3.9 well known for silicon oxide) of the second insulation material layer (138a, made of silicon oxide) of the isolation structure (137/138a/138b) is lower than a dielectric constant (7.5 well known for silicon nitride) of the first insulation material layer (137, made of silicon nitride, para [0034]) of the isolation structure (137/138a/138b).
Regarding independent claim 11, Song et al. teaches a memory device, comprising (Figs. 4B-11B/11C, para [0047]):
a substrate (100, para [0048]);
bit line structures (116/118/120, para [0029]) over the substrate (100),
spacers (SP1/SP2/ASP, para [0035], [0037]) along sidewalls of the bit line structures (116/118/120), wherein each of the spacers (SP1/SP2/ASP) comprises an air gap (ASP, para [0037]);
a conductive structure (BC/134/136) between the spacers (SP1/SP2/ASP); and
an isolation structure (137/138a/138b) between the conductive structure (BC/134/136) and one of the bit line structures (116/118/120), wherein the isolation structure (137/138a/138b, see Fig. 11B) comprises a first insulation material layer (137) sealing the air gap (ASP) and a second insulation material layer (138a) over the first insulation material layer (137), and the first insulation material layer (137) and the second insulation material layer (138a) are in contact with the one (120) of the bit line structures (116/118/120).
Claim Rejections - 35 USC § 103
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
11. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or non-obviousness.
12. Claims 12-20 are rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (US 2018/0174971 A1) as applied to claim 11 above, and further in view of Song et al. (US 2022/0052057 A1).
Regarding claim 12, Song et al./971 teaches all of the limitations of claim 11 from which this claim depends.
Song et al./971 is silent to explicitly disclose wherein, further comprising:
a capacitor structure over the conductive structure and the isolation structure, wherein the capacitor structure comprises:
a bottom electrode in contact with the conductive structure;
a dielectric layer lining the bottom electrode; and
a top electrode layer lining the dielectric layer.
Song et al./057 teaches wherein, further comprising (Fig. 24, A-A’):
a capacitor structure (200, para [0136]) over the conductive structure (170/190) and the isolation structure (195, para [0087]), wherein the capacitor structure (200) comprises:
a bottom electrode (210, para [0136]) in contact with the conductive structure (190);
a dielectric layer (220, para [0136]) lining the bottom electrode (210); and
a top electrode layer (230, para [0136]) lining the dielectric layer (220).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the capacitor structure as taught by Song et al./057 and modify the semiconductor memory device structure of Song et al./971, in order to store a binary bit as an electrical charge on a tiny capacitor, allowing for significantly higher integration density compared to static RAM (SRAM).
Regarding claim 13, Song et al./971 and Song et al./057 teach all of the limitations of claim 12 from which this claim depends.
The combination of Song et al./971 and Song et al./057 teaches wherein, the bottom electrode (210, Fig. 24, Song et al./057) of the capacitor structure (200) is further in contact with the second insulation material layer (138a, Fig. 11B, Song et al./971) of the isolation structure (137/138a/138b).
Regarding claim 14, Song et al./971 and Song et al./057 teach all of the limitations of claim 12 from which this claim depends.
The combination of Song et al./971 and Song et al./057 teaches wherein, the capacitor structure (200, Fig. 24, Song et al./057) and the first insulation material layer (137, Fig. 11B, Song et al./971) of the isolation structure (137/138a/138b) are separated by the second insulation material layer (138a) of the isolation structure.
Regarding claim 15, Song et al./971 and Song et al./057 teach all of the limitations of claim 11 from which this claim depends.
Song et al./971 teaches wherein (Figs. 4B-11B/11C), each of the spacers (SP1/SP2/ASP) comprises:
a first spacer layer (SP1) in contact with one of the bit line structures (116/118/120); and
a second spacer layer (SP2) in contact with the conductive structure (BC/134/136), wherein first spacer layer (SP1) is separated from the second spacer layer (SP2) by the air gap (ASP), and the second insulation material layer (138a, made of silicon oxide, para [0042]) of the isolation structure (137/138a/138b) is made of a different material (silicon oxide vs silicon nitride) from the first spacer layer (SP1, made of silicon nitride, para [0035]) and the second spacer layer (SP2, made of silicon nitride, para [0035]).
Regarding claim 16, Song et al./971 and Song et al./057 teach all of the limitations of claim 11 from which this claim depends.
Song et al./971 teaches wherein (Figs. 4B-11B/11C), a dielectric constant (3.9 well known for silicon oxide) of the second insulation material layer (138a, made of silicon oxide) of the isolation structure (137/138a/138b) is lower than a dielectric constant (7.5 well known for silicon nitride) of the first insulation material layer (137, made of silicon nitride, para [0034]) of the isolation structure (137/138a/138b).
Regarding claim 17, Song et al./971 and Song et al./057 teach all of the limitations of claim 11 from which this claim depends.
Song et al./971 teaches wherein (Figs. 4B-11B/11C), the first insulation material layer (137) of the isolation structure (137/138a/138b) has a concave surface and a convex surface (see Fig. 11C), and an intersection of the concave surface and the convex surface is in contact with one of the bit line structures (116/118/120).
Regarding claim 18, Song et al./971 and Song et al./057 teach all of the limitations of claim 11 from which this claim depends.
Song et al./971 teaches wherein (Figs. 4B-11B/11C), the first insulation material layer (137) of the isolation structure (137/138a/138b) has a concave surface and a convex surface, and an intersection of the concave surface and the convex surface is in contact with the conductive structure (BC/134/136).
Regarding claim 19, Song et al./971 and Song et al./057 teach all of the limitations of claim 11 from which this claim depends.
Song et al./971 teaches wherein (Figs. 4B-11B/11C), the second insulation material layer (138a) of the isolation structure (137/138a/138b) is in contact with the conductive structure (BC/134/136).
Regarding claim 20, Song et al./971 and Song et al./057 teach all of the limitations of claim 11 from which this claim depends.
Song et al./971 teaches wherein (Figs. 4B-11B/11C), the second insulation material layer (138a) of the isolation structure (137/138a/138b) and the spacers (SP1/SP2/ASP) are separated by the first insulation material layer (137) of the isolation structure (137/138a/138b).
Allowable Subject Matter
13. Claim 4 (claims 5-9 depend on claim 4), are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 4: the prior art of record alone or in combination neither teaches nor makes obvious a manufacturing method of a memory device, comprising:
Claim 4 recites ….forming the isolation structure between the conductive structure and one of the bit line structures comprises:
forming the first insulation material layer lining a top surface of the bit line structures, a top surface and a sidewall of the conductive structure;
removing a vertical portion of the first insulation material layer, such that a horizontal portion of the first insulation material layer remains on the top surface of the bit line structures, and a curved portion of the first insulation material layer remains between the conductive structure and one of the bit line structures;
forming the second insulation material layer overfilling between the conductive structure and one of the bit line structures; and
performing a planarization process to remove an excess portion of the second insulation material layer and the horizontal portion of the first insulation material layer until the top surface of the conductive structure is exposed.
14. The prior arts, Song et al. (US 2018/0174971 A1) and/or Song et al. (US 2022/0052057 A1) are silent to disclose or show forming or processing steps of the isolation structure between the conductive structure and one of the bit line structure. Therefore, by itself or in combination or with other prior arts does not disclose the quoted limitation as stated in section 13.
Response to Arguments
15. It has been acknowledged that the applicant has amended claims 3, per the response dated on 06/29/2026.
Applicant’s remarks in pages 12-14 have been fully considered, but they are not found persuasive, because the previously cited prior art, Song et al. discloses in Fig. 11B as annotated below discloses the contact area between the isolation structure 137/138a/138b and the bit line structure (116/118/120: contacts with 120).
In addition, the isolation structure (137/138a/138b) seals the air gap ASP, see figure below.
Therefore, it is suggested to amend the languages of claim(s) structurally and/or clarify the claim limitation(s) that would differentiate the instant invention from the cited prior arts.
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Conclusion
16. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
16. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
17. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812
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