Prosecution Insights
Last updated: May 29, 2026
Application No. 18/542,032

SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME

Non-Final OA §102§103
Filed
Dec 15, 2023
Priority
Dec 16, 2022 — provisional 63/433,027 +1 more
Examiner
WALL, VINCENT
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Etron Technology Inc.
OA Round
1 (Non-Final)
62%
Grant Probability
Moderate
1-2
OA Rounds
3m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 62% of resolved cases
62%
Career Allowance Rate
496 granted / 802 resolved
-6.2% vs TC avg
Strong +25% interview lift
Without
With
+25.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
38 currently pending
Career history
855
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
82.9%
+42.9% vs TC avg
§102
7.3%
-32.7% vs TC avg
§112
7.4%
-32.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 802 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group I, claims 1-13 in the reply filed on April 16, 2026 is acknowledged. Information Disclosure Statement The information disclosure statement (IDS) submitted on February 6, 2025; December 20, 2024; and December 15, 2023 were considered by the examiner. Drawing Objections The drawings are objected to because: Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. Per ¶ 0005, the information shown in figure 1 was known before the effective filing date of the current application as it shows the mainstream micro-LED process. See MPEP § 608.02(g). Figure 2 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. Per ¶¶ 0005-06, figure 2 shows mainstream, i.e. what was already known in the art, LAMT process settings. See MPEP § 608.02(g). Figures 3A-3C should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. Per ¶¶ 0006-10, figures 3A-3C show what is already known about the LAMT process and what is already known about the LED structure. See MPEP § 608.02(g) Figure 4 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. Per ¶ 0011, the key structures and materials shown in figure 4 were known in the art before the effective filing date of the current application. See MPEP § 608.02(g). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-2, 4, 6, and 8 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Gao et al. (US 2020/0075534 A1) (“Gao”). Regarding claim 1, Gao teaches at least in figures 1-2: a first die (top part of figure 1; hereinafter “A”) having a plurality (figure 2) of first metal pads (100) at a first bonding side (where 100 is; hereinafter “B”); a second die (bottom part of figure 1; hereinafter “C”) over the first die (A), having a plurality of second metal pads (100’) at a second bonding side facing the first bonding side (where 100’ is; hereinafter “D”), wherein each of the first metal pads (100) corresponds to each of the second metal pads (100’) with a pitch no greater than about 10 μm (¶ 0002, where the pitch can be as small a 1 μm); a first dielectric layer (top 108) surrounding and in contact with a sidewall of the first metal pads (100); and a second dielectric layer (bottom 108) surrounding and in contact with a sidewall of the second metal pads (100’). Regarding claim 2, Gao teaches at least in figures 1-2, and 8-9: wherein the second die is a micro-LED die, a processor die, or a chiplet (¶ 0066). Regarding claim 4, Gao teaches at least in figures 1-2, and 8-9: a soft metal (SM) section or a solder section (824/834) between each of the first metal pads (812) and the second metal pads (812), and a sidewall of the SM section or the solder section (824/834) is in contact with the one of the first dielectric layer (820) or the second dielectric layer (820), wherein a melting point of the SM section or the solder section (824/834) is no greater than about 250°C (table 1 where the melting/diffusion temperature is 150 C). Regarding claim 6, Gao teaches at least in figures 1-2, and 8-9: wherein a first segment of a sidewall of the second dielectric layer (bottom 108; 804/820) proximal to the second die (C) is in contact with a sidewall of the second metal pad (110’), and a second segment of the sidewall of the second dielectric layer (bottom 108; 804/820) proximal to the first die (A) is in contact with the sidewall of the SM section or the solder section (824/834). Regarding claim 8, Gao teaches at least in figures 1-2, and 8-9: wherein the material of the first dielectric layer and the second dielectric layer comprises silicon dioxide or polymer (¶¶ 0004, 35, and 43, where silicon oxide can be used). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 3, 7, and 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gao. Regarding claim 3, Gao does not explicitly teach: wherein a dimension of the second die is less than about 10 μm by 10 μm. However, making a die smaller or larger is considered a change in size or proportion. The Court has held in In Gardner v.TEC Syst., Inc., 725 F.2d 1338 (Fed. Cir. 1984) where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. Here the only difference between the prior art and the claimed device is the size of the second die. This does not render the claim patentably distinct from the prior art because if the prior art device was made to the same size it would not perform differently than the claimed device. Regarding claim 7, Gao does not explicitly teach: wherein a height ratio of the second segment and the first segment is in a range of from 25% to 85%. However, this is considered a change in size or proportion for the same reason give in claim 3, where the height ratio of the claimed feature is not patentably distinct from the prior art as the claimed device would not perform differently than the prior art with the claimed ratio. Regarding claim 9, Gao teaches at least in figures 1-2, and 8-9: a first die (bottom part of figure 1; hereinafter “C”) ; a second die (top part of figure 1; hereinafter “A”) disposed over the first die (C); and a bonding layer (detailed below) between the first die (C) and the second die (A), the bonding layer comprises: a plurality of first metal pads (lower 812; figure 2 shows the plurality. It would have obvious that while a single metal pad is shown in the figures there would be a plurality based upon the disclosure) each stacked with a first barrier layer (lower 814) and connected to the first die (C), and a first dielectric bonding material (lower 804/820) contacting a sidewall of each of the plurality of first metal pads (lower 812) and a sidewall of the first barrier layer (lower 814); a plurality of second metal pads (upper 812; figure 2 shows the plurality. It would have obvious that while a single metal pad is shown in the figures there would be a plurality based upon the disclosure) each stacked with a second barrier layer (upper 814) and connected to the second die (A), and a second dielectric bonding material (upper 804/820) contacting a sidewall of each of the plurality of second metal pads (upper 812) and a sidewall of the second barrier layer (upper 814); and a soft metal (SM) section or a solder section (824/834) between each of the first metal pads (lower 812) and each of the second metal pads (upper 812). Regarding claim 10, Gao teaches at least in figures 1-2, and 8-9: wherein a thickness of each SM section or the solder section is in a range of from about 1 μm to about 2 μm (¶ 0058, where the thickness can be 1.6 μm). Regarding claim 11, Claim 11 contains subject matter of claims 2-3, and rejected for the same reasons as those given above. Regarding claim 12, Claim 12 contains subject matter from claim 1 is and is rejected for the same reason given in claim 1. Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gao, in view of Lo et al. (US 2018/0060479 A1) (“Lo”). Regarding claim 5, Gao does not teach: wherein the sidewall of the SM section or the solder section is aligned with a sidewall of one of the first metal pads or the second metal pads. Lo teaches at least in figure 2B: wherein the sidewall of the SM section or the solder section (B1) is aligned with a sidewall of one of the first metal pads or the second metal pads (V1 or RDL1). It would have been obvious to one of ordinary skill in the art that the sidewall of the SM section or the solder section can be aligned with the first metal pads or the second metal pads. One reason that one would want the alignment of the elements is that it will reduce the total amount of horizontal area occupied by the elements which would allow more interconnects between the dies or allow for smaller dies. One reason that one would want the first or second metal pads to be larger than the SM section or the solder section is that it would allow for overlay error between the first die and the second die. Therefore, whether to have the elements aligned or not would be a routine matter of optimization for one of ordinary skill in the art based upon the above parameters when coupled with the resulting yield of the different processes stated above. Claim(s) 9, and 13 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Shao et al. (US 2020/0091039 A1) (“Shao”). Regarding claim 9, Shao teaches at least in figure 1H-1I’: a first die (10) ; a second die (20) disposed over the first die (10); and a bonding layer (detailed below) between the first die (10) and the second die (20), the bonding layer (detailed below) comprises: a plurality of first metal pads (150; figure 5 shows the plurality) each stacked with a first barrier layer (162) and connected to the first die (10), and a first dielectric bonding material (figure 5 shows that the bonding layer is surrounded by 154 a dielectric) contacting a sidewall of each of the plurality of first metal pads and a sidewall of the first barrier layer (as shown in figure 5, the entirety of the structure claimed is contacted by and surrounded by the dielectric material 154); a plurality of second metal pads (250; figure 5 shows the plurality) each stacked with a second barrier layer (262) and connected to the second die (20), and a second dielectric bonding material (figure 5 shows that the bonding layer is surrounded by 254 a dielectric) contacting a sidewall of each of the plurality of second metal pads and a sidewall of the second barrier layer (as shown in figure 5, the entirety of the structure claimed is contacted by and surrounded by the dielectric material 254); and a soft metal (SM) section or a solder section (170/270) between each of the first metal pads (150) and each of the second metal pads (250). Regarding claim 13, Shao teaches at least in figure 1H-1I’: wherein each of the first barrier layers (162) and the second barrier layers (262) comprises Ni, NiV, Ti, TiW, TiN, Ta, TaN, Cr, phased Cr/Cu, or their combinations (¶ 0020, where Ti can be used), and each of the first barrier layers (162) or the second barrier layers (262) is coated with a wetting layer (164/264) comprising Au, Ag, Pd, or a combination of metals comprising Cu, Ni, NiV, Au, or Ag (¶ 0023), while the SM section or the solder section (170/270) comprises a die attachment materials made up of Sn, Pb, Au, Ag, Cu, In, Bi, Zn, Al, thorium, or their combinations (¶ 0031), and the material of the first metal pads (150) and the second metal pads (250) include Cu, Au, Al, W, Mo, Rh, Co, Ru, Ir, Pt, Pd, Os or combinations thereof (¶ 0019). Claim(s) 21-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gao, in view of Shao. Regarding claim 21, Gao teaches at least in figures 1-2, and 8-9: The difference between claim 21 and claim 1 are the following limitations: A driver IC die or a display panel having a plurality of first metal pads at a first bonding side; a LED die coupled over the driver IC die or the display panel, wherein the first dielectric layer is self-aligned to and directly in contact with the second dielectric layer, and the first metal pads are correspondingly electrically connected to the second metal pads Gao does not teach the function of the first die and the second die. However, the function of the first die and second die does not render the claim patentably distinct. Shao teaches a similar structure to Gao and teaches that one can use die bonding to package different packages together to integrate different functions. Shao ¶ 0004. Thus, while Gao and Shao do not expressly teach the functions of different dies it would have been obvious to one of ordinary skill in the art to use routine creativity to couple a driver IC die and a LED die together. This is because the Court has recognized “[a] person of ordinary skill in the art is also a person of ordinary creativity, not an automaton.” KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398, 421 (2007). Thus, while the references do not explicitly teach the functions of the dies it would have been obvious to one of ordinary skill in the art that dies with these functions could be combined to produce and integrated display. Regarding claim 22, Claim 3 is narrower than claim 22 and therefore teaches this limitation. Regarding claim 23, Gao teaches at least in figures 1-2, and 8-9: wherein the first metal pads (lower 812) and the second metal pads (upper 812) are free from being directly in contact with each other (there are a plurality of elements between the 812s). Regarding claim 24, Gao teaches at least in figures 1-2, and 8-9: Claim 24 is rejected for the same reasons contained in claim 4 above. Regarding claims 25-26, Gao does not teach: The limitations of claim 25-26. Shao teaches at least in figure 1H-1I’: All of the limitations of claim 25-26 in claim 13 above. It would have been obvious to one of ordinary skill in the art to substitute the interconnect structure of Gao with the interconnect structure of Shao as the structure of Shao appears to be an alternative connection means to Gao. This is because both are directed to same technical field of die bonding, and both are directed to solving the same technical problem of greater integration leading to the continuation of Moores Law. Regarding claims 27, Shao teaches at least in figure 1H-1I’, and 3C: wherein the display panel is a glass display panel (¶ 0077, where the substrate of one of the dies 390 can be glass. Therefore, it can be considered a glass display panel). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT WALL whose telephone number is (571)272-9567. The examiner can normally be reached Monday to Thursday at 7:30am to 2:30pm PST. Interviews can be scheduled on Tuesday thru Thursday at 10am PST or 2pm PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VINCENT WALL/ Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Dec 15, 2023
Application Filed
May 11, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12641865
FIELD-EFFECT TRANSISTOR STRUCTURE INCLUDING PASSIVE DEVICE AND BACK SIDE POWER DISTRIBUTION NETWORK (BSPDN)
3y 4m to grant Granted May 26, 2026
Patent 12635171
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
2y 5m to grant Granted May 19, 2026
Patent 12628503
DISPLAY DEVICE, DISPLAY PANEL AND MANUFACTURING METHOD THEREOF
2y 11m to grant Granted May 12, 2026
Patent 12628382
INTERFACIAL DUAL PASSIVATION LAYER FOR A FERROELECTRIC DEVICE AND METHODS OF FORMING THE SAME
1y 10m to grant Granted May 12, 2026
Patent 12610573
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
4y 8m to grant Granted Apr 21, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
62%
Grant Probability
87%
With Interview (+25.1%)
2y 9m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 802 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month