DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of method embodiment 1 as shown in figs. 1-7 (claims 1-4, 7-13, 15-17 readable thereon, claims 5, 6, 14, 18-20 withdrawn) in the reply filed on 5/6/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7, and similarly in claim 15, recites that the “oxide layer is formed prior to formation of the doped p-type layer.” Claim 1, and similarly in claim 11, recites “forming an oxide layer over the doped p-type layer” at line 7 and 8, respectively. Claims 7 and 15 contradict the order of the steps recited in claims 1 and 11 and therefore are deemed indefinite.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 4, 8, 9, 11, 13, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Manda (US PGPub 2010/0314672) in view of Toros et al. (US 7,323,671; hereinafter “Toros”).
Re claim 1: Manda teaches (e.g. figs. 1, 2A-4G) a method, comprising: providing a main body (11) of a complementary metal oxide semiconductor image sensor (solid state image sensing device as titled); forming a plurality of trenches (trench formed as shown in fig. 2B; e.g. paragraph 69; hereinafter “T”; there would be plural trenches formed since each trench corresponds to pixels, and an array of pixels are necessary for image sensing) in the main body (11), each of the plurality of trenches (T) comprising a set of sidewalls (sidewalls of T; hereinafter “SW”) and a base (base of T; hereinafter “B”) extending between the set of sidewalls (SW); forming a doped p-type layer (P+ impurity region 17; e.g. paragraph 42) along each of the set of sidewalls (SW) using at least one of: a plasma doping process (ion implantation; e.g. paragraph 71), and an epitaxy process; forming an oxide layer (gate insulation film 12 formed by radical oxidation; e.g. paragraph 78) over the doped p-type layer (17); and forming a polysilicon fill (polycrystalline silicon gate electrode 14 which serves as a transfer gate; e.g. paragraphs 80 and 71) over the oxide layer (12).
Manda teaches that the polycrystalline silicon material is doped N-type but is silent as to the polysilicon fill being a p-type fill over the oxide layer.
Toros teaches a transfer gate being formed to from p-type polysilicon to reduce dark current near the transfer gate (e.g. column 5, lines 48-50).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the p-type polysilicon material for the transfer gate as taught by Toros in the method of Manda in order to have the predictable result of reducing dark current near the transfer gate (see column 5, lines 48-50 of Toros).
Re claim 3: Manda teaches the method of claim 1, further comprising: forming a sacrificial layer (sacrificial oxide film 22; e.g. paragraph 70) along the set of sidewalls (SW is formed in fig. 2C) after the plurality of trenches (T as shown in fig. 2B) are formed in the main body (11); removing the sacrificial layer (22 is removed in fig. 3E); and forming an n-type layer (n-impurity region 2 (which consists of N+ region 2A and N region 2B) is formed in fig. 2A, however, during further processing of the device, 2 will continually diffuse and create new regions of N-type regions associated with the initial region 2) along the set of sidewalls (SW) after the sacrificial layer (22) is removed (22 is removed in fig. 3E, the deposition processes of figs. 4F and 4G would add to the thermal budget of the method disclosed and would diffuse n-type impurities from region 2), wherein the doped p-type layer (17) is formed along each of the set of sidewalls (SW) after the n-type layer is formed (2).
Re claim 4: Manda teaches the method of claim 3, wherein forming the sacrificial layer (22) comprises forming an oxide (sacrificial oxide 22) along the set of sidewalls (SW) and along the base (B).
Re claim 8: Manda teaches the method of claim 1, wherein the oxide layer (12) is formed after formation (fig. 4F where oxide layer 12 is formed is after fig. 3D where the p-type layer 17 is formed) of the doped p-type layer (17).
Re claim 9: Manda teaches the method of claim 1, wherein the plurality of trenches (T) are formed in the main body (11) using a dry etch process (dry etching; e.g. paragraph 69).
Re claim 11: Manda teaches (e.g. figs. 1, 2A-4G) a method of forming a complementary metal oxide semiconductor image sensor, the method comprising: providing a photodiode body (11); forming a plurality of trenches (trench formed as shown in fig. 2B; e.g. paragraph 69; hereinafter “T”; there would be plural trenches formed since each trench corresponds to pixels, and an array of pixels are necessary for image sensing) in the photodiode body (11), each of the plurality of trenches (T) comprising a set of sidewalls (sidewalls of T; hereinafter “SW”) and a base (base of T; hereinafter “B”) extending between the set of sidewalls (SW); forming a doped p-type layer (P+ impurity region 17; e.g. paragraph 42) along each of the set of sidewalls (SW) and along the base (B) using at least one of: a plasma doping process (ion implantation; e.g. paragraph 71), and an epitaxy process; forming an oxide layer (gate insulation film 12 formed by radical oxidation; e.g. paragraph 78) over the doped p-type layer (17); and forming a polysilicon fill (polycrystalline silicon gate electrode 14 which serves as a transfer gate; e.g. paragraphs 80 and 71) over the oxide layer (12).
Manda teaches that the polycrystalline silicon material is doped N-type but is silent as to the polysilicon fill being a p-type fill over the oxide layer.
Toros teaches a transfer gate being formed to from p-type polysilicon to reduce dark current near the transfer gate (e.g. column 5, lines 48-50).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the p-type polysilicon material for the transfer gate as taught by Toros in the method of Manda in order to have the predictable result of reducing dark current near the transfer gate (see column 5, lines 48-50 of Toros).
Re claim 13: Manda teaches the method of claim 11, further comprising: forming a sacrificial layer (sacrificial oxide film 22; e.g. paragraph 70) along the set of sidewalls (SW is formed in fig. 2C) after the plurality of trenches (T as shown in fig. 2B) are formed in the main body (11); removing the sacrificial layer (22 is removed in fig. 3E); and forming an n-type layer (n-impurity region 2 (which consists of N+ region 2A and N region 2B) is formed in fig. 2A, however, during further processing of the device, 2 will continually diffuse and create new regions of N-type regions associated with the initial region 2) along the set of sidewalls (SW) after the sacrificial layer (22) is removed (22 is removed in fig. 3E, the deposition processes of figs. 4F and 4G would add to the thermal budget of the method disclosed and would diffuse n-type impurities from region 2), wherein the doped p-type layer (17) is formed along each of the set of sidewalls (SW) after the n-type layer is formed (2).
Re claim 16: Manda teaches the method of claim 11, wherein the oxide layer (12) is formed after formation (fig. 4F where oxide layer 12 is formed is after fig. 3D where the p-type layer 17 is formed) of the doped p-type layer (17).
Claim(s) 2 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Manda in view of Toros as applied to claims 1 and 11 above, respectively, and further in view of Van Asselt et al. (US PGPub 2008/0245967; hereinafter “Van Asselt”).
Re claim 2: Manda in view of Toros teaches substantially the entire method of claim 1 except explicitly teaching performing a wet etch to increase a width of the plurality of trenches, wherein the oxide layer is formed after the wet etch is performed.
Van Asselt teaches (e.g. fig. 6) performing a wet etch (wet isotropic etch to form wider trenches 40 having rounded edges; e.g. paragraph 45) to increase a width of the plurality of trenches (T of Manda), wherein the oxide layer (12 of Manda) is formed after the wet etch (wet etch of Van Asselt) is performed.
It would have been obvious to one of ordinary skill in the art at time of effective filing, absent unexpected results, to use the wet etch after trench formation as taught by Van Asselt in the method of Manda in view of Toros in order to have the predictable result of increasing light responsive area in an application which required larger light sensitive regions.
Re claim 12: Manda in view of Toros teaches substantially the entire method as recited in claim 11 except explicitly teaching performing a wet etch to increase a width of the plurality of trenches, wherein the oxide layer is formed after the wet etch is performed.
Van Asselt teaches (e.g. fig. 6) performing a wet etch (wet isotropic etch to form wider trenches 40 having rounded edges; e.g. paragraph 45) to increase a width of the plurality of trenches (T of Manda), wherein the oxide layer (12 of Manda) is formed after the wet etch (wet etch of Van Asselt) is performed.
It would have been obvious to one of ordinary skill in the art at time of effective filing, absent unexpected results, to use the wet etch after trench formation as taught by Van Asselt in the method of Manda in view of Toros in order to have the predictable result of increasing light responsive area in an application which required larger light sensitive regions.
Claim(s) 10 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Manda in view of Toros as applied to claims 1 and 11 above, respectively, and further in view of Adkisson et al. (US PGPub 2007/0187734; hereinafter “Adkisson”).
Re claim 10: Manda in view of Toros teaches substantially the entire method as recited in claim 1 except explicitly teaching performing a planarization process following formation of the p-type fill.
Adkisson teaches (e.g. figs. 2 and 4D) performing a planarization (planarize excess poly-Si material 315; e.g. paragraph 43) process following formation of the p-type fill (14 of Manda).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the planarization as taught by Adkisson in the method of Manda in view of Toros in order to have the predictable result of providing a planar surface for subsequent front end of line material layers so that they can be formed with high planarity and accuracy.
Re claim 17: Manda in view of Toros teaches substantially the entire method as recited in claim 11 except explicitly teaching performing a planarization process following formation of the p-type fill, wherein the p-type fill is removed selective to an upper surface of the photodiode body; and performing a plurality of front-end-of-line processes after the planarization process.
Adkisson teaches (e.g. figs. 2 and 4D) performing a planarization (planarize excess poly-Si material 315/115; e.g. paragraph 43) process following formation of the p-type fill (14 of Manda), wherein the p-type fill (14 of Manda/115 of Adkisson) is removed selective to an upper surface of the photodiode body (11 of Manda/105 of Adkisson); and performing a plurality of front-end-of-line processes (15, 16 of Manda) after the planarization process (planarization process of Adkisson).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the planarization as taught by Adkisson in the method of Manda in view of Toros in order to have the predictable result of providing a planar surface for subsequent front end of line material layers so that they can be formed with high planarity and accuracy.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
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