CTNF 18/542,870 CTNF 88433 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Election was made without traverse in the reply filed on 4/27/2026. Applicant has elected Group II, corresponding to claims 6-10. Invention Group I, corresponding to claims 1-5, is withdrawn from further consideration. The examiner acknowledges the applicant’s cancellation of claims 1-5. Specification The specification submitted 12/18/2023 has been accepted by the examiner. Drawings The drawings submitted on 12/18/2023 have been accepted by the examiner. Information Disclosure Statements The information disclosure statements (IDS) submitted recently have been considered by the examiner. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-36 AIA Claim s 6-8 and 10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 10, 13, and 14 of U.S. Patent No. 10,529,864 in view of US # 200838805 and further in view of Akimoto (US # 20080308805) . Regarding Claim 6-8 , claims 10 and 14 of US # 10529864 recites claim limitations that are not patentably distinct from most of the applicant’s limitations. Although claims 10 and 14 recite much of the claimed invention, they do not recite the device comprising a two-layer stack, including silicon nitride film and a first oxynitride layer; and a second insulating film including a second oxynitride film. Nonetheless the prior art at the time the application was filed, in the same field of endeavor, renders such feature differences obvious, as explained below. For example, Akimoto ‘805 teaches a similar device (see Figs. 4 and corresponding text) comprising a two-layer stack, including silicon nitride film (403a; [0102]) and a first oxynitride layer (403b; [0102]); and a second insulating film including a second oxynitride film (405; see [0110]) over an oxide semiconductor layer (404). A person having ordinary skill in the art would have readily recognized the desirability and advantages of modifying the insulative materials recited in claims 6-8, as suggested by material layers of Akimoto. Specifically, the modification suggested by Akimoto would be to employ a device comprising a two-layer stack, including silicon nitride film and a first oxynitride layer; and a second insulating film including a second oxynitride film. The rationale for this modification is that these materials are compatible with an oxide semiconductor system, including that the two-layer stack suppresses diffusion of impurities and the second oxynitride film protects the semiconductor from being damaged during subsequent processing steps, like the S/D formation ([0110]) . 08-36 AIA Claim 9 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 10 and 13 of U.S. Patent No. 10,529,864 in view of Akimoto (US # 20080308805) and further in view of NPL Baek (G. Baek, K. Abe, A. Kuo, H. Kumomi and J. Kanicki, "Electrical Properties and Stability of Dual-Gate Coplanar Homojunction DC Sputtered Amorphous Indium–Gallium–Zinc–Oxide Thin-Film Transistors and Its Application to AM-OLEDs," in IEEE Transactions on Electron Devices, vol. 58, no. 12, pp. 4344-4353, Dec. 2011) . Regarding Claim 9 , claims 10 and 13 of US # 10529864 recites claim limitations that are not patentably distinct from most of the applicant’s limitations. Although claims 10 and 13 recite much of the claimed invention, they do not recite the semiconductor device according to claim 7, wherein the conductive film is in contact with a top surface of the gate electrode. Nonetheless the prior art at the time the application was filed, in the same field of endeavor, renders such feature differences obvious, as explained below. For example, NPL Baek is in the same or analogous field, and it teaches that connecting the top gate and bottom gate electrodes of dual gate a-IGZO TFT to a common electrical potential and it quantifies the benefits. A person having ordinary skill in the art would have recognized that modifying the gate structure of claims 10 and 13 with the connected top-gate suggested by NPL Baek would be obvious. Specifically, the modification suggested by NPL Baek would be to employ a semiconductor device according to claim 7, wherein the conductive film is in contact with a top surface of the gate electrode. The rationale for this obvious modification is that a top gate at the same potential increases on-state current in the saturation region, makes a steeper subthreshold swing, and functions as a light shield. This would have been apparent to a person having ordinary skill in the art in reading both references because the existence and benefits of a top conductor TFT are well known in the art (see MPEP 2144.01) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US # 20130157422 Regarding Claim 6, Yamazaki ‘422 teaches a semiconductor device comprising: a substrate (400); a gate electrode (401) over the substrate; a silicon nitride film (402a; [0066]) over the gate electrode; a first silicon oxynitride film (402b; [0068]) over the silicon nitride film; an oxide semiconductor film (403; [0040, 71]) over the first silicon oxynitride film; a second silicon oxynitride film (417a) having a region in contact with the oxide semiconductor film; a first metal oxide film comprising In over the second silicon oxynitride film; a second metal oxide film comprising Al (417b) over the second oxynitride film; and a conductive film ([0180-181]) over the second metal oxide film. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A JOHNSON whose telephone number is (571)272-9475. The examiner can normally be reached normally working Monday to Friday between 9 am and 6 pm Eastern Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER A JOHNSON/Primary Examiner, Art Unit 2899 Application/Control Number: 18/542,870 Page 2 Art Unit: 2899 Application/Control Number: 18/542,870 Page 3 Art Unit: 2899 Application/Control Number: 18/542,870 Page 4 Art Unit: 2899 Application/Control Number: 18/542,870 Page 5 Art Unit: 2899 Application/Control Number: 18/542,870 Page 6 Art Unit: 2899 Application/Control Number: 18/542,870 Page 7 Art Unit: 2899
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