DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
1. Acknowledgement is made of the amendment received on 1/21/2026. Claims 1-7 are pending in this application.
Drawings
2. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “protruding portion” (claim 6) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
3. Claims 1-3 and 5-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Han et al. (US 2019/0035750).
Re claim 1, Han teaches, under BRI, Figs. 5B & 5H, [0041, 0047, 0049, 0052, 0061, 0068], a semiconductor device, comprising:
-a substrate (100, 2x bottom 110);
-an interlayer dielectric layer (uppermost 110, 131 or upper 110 with barrier layer, not shown) [0041] on the substrate (100, 110);
-a metal pad (chip pad 111) on the interlayer dielectric layer (e.g., on uppermost 110); and
-a passivation dielectric layer (133) formed on the interlayer dielectric layer (110, 131) and the metal pad (111);
-a bump (CPa, CLa or 141) electrically connected to the metal pad (111);
-a first side surface (side or lateral surface of middle layer 110 exposed in OP2) of the substrate (100, 2x bottom 110) disposed below the interlayer dielectric layer (110, 131), the first side surface comprising an etched profile (e.g., result from anisotropically etch) (Fig. 5B, [0052]); and
-a second side surface (side surface exposed in cutting region 21) of the substrate (100, 2x bottom 110) spacer apart from the first side surface, the second side surface comprising a mechanical dicing texture (e.g., result from a sawing process) distinct from the etched profile of the first side surface (Fig. 5H, [0068]).
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Re claim 2, Han teaches, Fig. 5B, [0044, 0057], wherein the interlayer dielectric layer comprises: a first interlayer dielectric layer (upper 110) on the substrate (100, 2x bottom 110); and a second interlayer dielectric layer (131) on the first interlayer dielectric layer, and wherein a metal wire (CPa, 120) is formed on the first interlayer dielectric layer.
Re claim 3, Han teaches the first interlayer dielectric layer is a lower-k dielectric layer [0039].
Re claim 5, Han teaches, [0039, 0050], the second interlayer dielectric layer (HDP oxide layer 131) has a higher dielectric constant value the firs interlayer dielectric layer (upper most 110) (or barrier layer vs 110, [0041]).
Re claim 6, Han teaches, Fig. 5H, the substrate (110, 2x bottom 110) comprises a protruding region (region extending from side surface of 110, result from etching and sawing) extending laterally between the first side surface and the second side surface.
Re claim 7, Han teaches, Fig. 5B, after the portions of the interlayer dielectric layer (110, 131) are etched, another portion (110, 131) exists on the substrate at a predetermined thickness.
4. Claims 1 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Han et al. (US 2020/0091100, “Han100”).
Re claim 1, Han100 teaches, under BRI, Figs. 5C5I, [0030, 0042, 0044, 0046, 0050, 0057, 0075], a semiconductor device, comprising:
-a substrate (100, 103, (2x) bottom 110);
-an interlayer dielectric layer (top 110, 131) on the substrate;
-a metal pad (123a) on the interlayer dielectric layer (on top 110); and
-a passivation dielectric layer (133) formed on the interlayer dielectric layer (110, 131) and the metal pad (123a);
-a bump (141a) electrically connected to the metal pad (123a);
-a first side surface (side middle layer 110 exposed in OP2) of the substrate (100, 103, (2x) bottom 110) disposed below the interlayer dielectric layer (110, 131), the first side surface comprising an etched profile (e.g., result from anisotropically etching) [0057]; and
-a second side surface (side surface exposed in cutting region 21) of the substrate (100, 103, (2x) bottom 110) spacer apart from the first side surface, the second side surface comprising a mechanical dicing texture (e.g., result from a sawing process) [0075] distinct from the etched profile of the first side surface.
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Re claim 6, Han100 teaches, Fig. 5I, the substrate (110, 103, (2x) bottom 110) comprises a protruding region (region extending from side surface of 110, result from etching and sawing) extending laterally between the first side surface and the second side surface.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Han.
The teachings of Han have been discussed above.
Re claim 4, Han (in first consideration) does not explicitly teach the first interlayer dielectric and the second interlayer dielectric layer are same dielectric layer.
Han does teach “lower dielectric layer 110…may include a plurality of stacked insulating layers” & “maybe formed of a low-k dielectric material” [0038, 0039].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ & modify the teaching as taught by Han to obtain the first interlayer dielectric and the second interlayer dielectric layer are same dielectric layer as claimed, because it aids in facilitating manufacturing process and achieving desired stacked of interlayer dielectric layer at cost effective.
Response to Arguments
6. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
The claims amended with newly added limitations, interpretation and rejection under Han are altered to meet the current claims.
In further consideration, similar to Figs. 5A-B of the application, Han teaches, Figs. 5B & 5H, [0052, 0068], an anisotropically etch to form openings OP1, OP2 & OP3, and a sawing process applied to cutting region 21. Hence, Han teaches a first side surface (at side of middle 110) of the substrate (100, 2x bottom 110) disposed below the interlayer dielectric layer (upper 110, 131), the first side surface comprising an etched profile (result from a anisotropically etch); and a second side surface (side surface of 100, 110) of the substrate spaced apart from the first side surface, the second side surface comprising a mechanical dicing texture (result from sawing process) distinct from the etched profile of the first side surface. Further, Han teaches, Fig. 5H, a protruding region (region extending from side surface of 110, result from etching and sawing).
As result, given a broadest reasonable interpretation, Han meets the claimed invention. Details included in the above rejection.
Conclusion
7. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 3/10/26