Prosecution Insights
Last updated: July 17, 2026
Application No. 18/543,289

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

Non-Final OA §102§103§112
Filed
Dec 18, 2023
Priority
Jun 12, 2023 — RE 10-2023-0075002
Examiner
CHEN, DAVID Z
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
MagnaChip Semiconductor Ltd.
OA Round
1 (Non-Final)
45%
Grant Probability
Moderate
1-2
OA Rounds
1y 0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 45% of resolved cases
45%
Career Allowance Rate
306 granted / 685 resolved
-23.3% vs TC avg
Strong +50% interview lift
Without
With
+49.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
49 currently pending
Career history
751
Total Applications
across all art units

Statute-Specific Performance

§103
78.9%
+38.9% vs TC avg
§102
16.6%
-23.4% vs TC avg
§112
3.9%
-36.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 685 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Response to Amendment/Restriction Applicant's election with traverse of Group II, Species I (FIG. 4D), and claims 11-23 in the reply filed on June 02, 2026 is acknowledged. The traversal is on the ground(s) that “Because the Examiner’s proposed alternative process does not produce the same product as claimed, the product and process are not patentably distinct.” This is not found persuasive because the different process still provides covering of the shield electrode by the shield insulating layer. The process is distinct by not forming a plurality of trenches to surround the shield electrode by the shield insulating layer. Further, the argument that “both species are merely process variants directed to the same inventive concept” is found persuasive such that claims 11-23 are under examination and claims 1-10 are withdrawn from further consideration. The requirement is still deemed proper and is therefore made FINAL. Specification The title of the invention is broad and not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. As to claim 19, the limitation “etching an upper surface of the epitaxial layer by performing a CMP…such that the inter-electrode insulating layer etched to the upper surface of the epitaxial layer is formed in a trench” fails to clearly define the processes shown in FIG. 5. It is unclear how the epitaxial layer is etched after forming the poly oxide as the poly oxide covers the epitaxial layer. This then followed by etching the inter-electrode insulating layer to the upper surface of the epitaxial layer etched before etching the inter-electrode insulating layer. It is also not clear what this particular “a trench” is relative to the recited plurality of trenches. Thus, the limitation renders the claim indefinite and clarification is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 11-12, 14, 16-18, and 20-23 are rejected under 35 U.S.C. 102(a)(1)(2) as being anticipated by U.S. Patent Application Publication No. 2013/0302958 A1 to Hossain et al. (“Hossain”). As to claim 11, Hossain discloses a method for manufacturing a semiconductor device, the method comprising: forming an epitaxial layer (14) of a first conductivity type on a substrate (12) of the first conductivity type; forming a plurality of trenches (22, 27) in the epitaxial layer (14); forming a shield insulating layer (261, 262) inside the plurality of trenches (22, 27); forming a shield electrode (21, 141, 1021, 1141) surrounded by the shield insulating layer (261, 262) at a lower portion of the plurality of trenches (22, 27); forming an inter-electrode insulating layer (26) over the shield insulating layer (261, 262) and the shield electrode (21, 141, 1021, 1141) inside the plurality of trenches (22, 27); forming a gate insulating layer (127) on the inter-electrode insulating layer (26) disposed inside the plurality of trenches (22, 27); forming a gate electrode (28, 281) on the gate insulating layer (127); forming a body region (31) of a second conductivity type on an upper portion of the epitaxial layer (14) between the plurality of trenches (22, 27); forming a source region (33) on the body region (31); forming an inter-layer insulating layer (471, 477, 41) on the gate electrode (28, 281) and the source region (33); and forming a body contact region (36) in the body region (31), wherein a location and a thickness of the gate electrode (28, 281) are determined by a location and a thickness of the inter-layer insulating layer (471, 477, 41) (See Fig. 1-Fig. 17, ¶ 0014-¶ 0016, ¶ 0018-¶ 0025, ¶ 0029-¶ 0032, ¶ 0034-¶ 0038, ¶ 0040) (Notes: gate electrode is recessed to accommodate the inter-layer insulating layer). As to claim 12, Hossain further discloses wherein the forming of the inter-electrode insulating layer (26) comprises: determining the location and the thickness of the inter-layer insulating layer (471, 477, 41) by a depth at which the shield electrode (21, 41, 1021, 1141) is recess etched (See Fig. 7, Fig. 8, ¶ 0024, ¶ 0025). As to claim 14, Hossain further discloses wherein the forming of the plurality of trenches (22, 27) further comprises: forming the epitaxial layer (14), forming a mask (47) on the epitaxial layer (14), and performing a trench etching on the epitaxial layer (14) to form a trench (22, 27), and forming an angle of inclination of a side of the trench between 85° and 90° relative to an upper inner surface of the trench (22, 27) (See Fig. 1, ¶ 0016, ¶ 0018). As to claim 16, Hossain further discloses wherein the forming of the shield insulating layer (261, 262) further comprises: forming the shield insulating layer (261, 262) by a primary thermal oxidation or by a secondary chemical vapor deposition (CVD) after the primary thermal oxidation is performed (See Fig. 2, ¶ 0019). As to claim 17, Hossain further discloses wherein the forming of the shield electrode (21, 41, 1021, 1141) further comprises: forming the shield electrode (21, 41, 1021, 1141) by depositing a shield poly (1021, 1141) inside the shield insulating layer (261, 262) on an upper surface of the shield insulating layer (261, 262); etching the shield poly (1021, 1141) deposited on the upper surface of the shield insulating layer (261, 262) to a height of an upper surface of a trench via chemical mechanical polishing (CMP) or to a height of an upper surface of the epitaxial layer (14) via blanket etching; and etching the shield poly (1021, 1141) etched to the height of the upper surface of the trench (22, 27) or to the height of the upper surface of the epitaxial layer (14) to a height at which the inter-electrode insulating layer (26) is formed (See Fig. 3-Fig. 8, ¶ 0021-¶ 0025). As to claim 18, Hossain further discloses wherein the forming of the shield electrode (21, 41, 1021, 1141) further comprises: etching a portion of a side surface of the shield insulating layer (261, 262) to increase a width of an opening in the shield insulating layer (261, 262) disposed on a side of the shield electrode (21, 41, 1021, 1141) (See Fig. 3-Fig. 8, ¶ 0021-¶ 0025). As to claim 20, Hossain further discloses wherein the forming of the gate electrode (28, 281) further comprises: depositing a gate poly (281) on the shield insulating layer (261, 262) and the gate insulating layer (127) formed on an upper surface of the epitaxial layer (14); performing a CMP on the gate poly (281) deposited on the upper surface of the epitaxial layer (14) to the upper surface of the epitaxial layer (14); and performing a recess etching to the gate poly (281) to which the CMP is performed so that a height of the gate poly (281) is less than a height of the upper surface of the epitaxial layer (14) (See Fig. 12, Fig. 14, Fig. 16, ¶ 0031, ¶ 0033, ¶ 0036). As to claim 21, Hossain further disclose wherein the performing of the recess etching comprises etching the gate poly (281) from the upper surface of the epitaxial layer (14) to an etch thickness of 500 Å to 5000 Å (See ¶ 0016, ¶ 0036). As to claim 22, Hossain further discloses wherein the forming of the body region (31) further comprises: forming the body region (31) to have a maximum thickness on an upper surface of the epitaxial layer (14) equal to a depth of the gate electrode (28, 128) formed on an upper surface of the inter-electrode insulating layer (26) (See Fig. 17). As to claim 23, Hossain further discloses further comprising: forming a metal layer (44) over the body region (31), the source region (33), and the inter-layer insulating layer (471, 477, 41) (See Fig. 17, ¶ 0040). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 13 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2013/0302958 A1 to Hossain et al. (“Hossain”) as applied to claim 11 above, and further in view of U.S. Patent Application Publication No. 2020/0312962 A1 to Nagata et al. (“Nagata”). The teaching of Hossain has been discussed above. As to claim 13, although Hossain discloses wherein the forming of the epitaxial layer (14) further comprises: forming a lower epitaxial layer on the substrate (12); and forming an upper epitaxial layer on the lower epitaxial layer (See ¶ 0015) (Notes: the lower epitaxial layer and the upper epitaxial layers are grown relative to each other), Hossain does not further disclose and wherein a dopant concentration of the lower epitaxial layer is higher than a dopant concentration of the upper epitaxial layer. However, Nagata does disclose and wherein a dopant concentration of the lower epitaxial layer (11) is higher than a dopant concentration of the upper epitaxial layer (12) (See Fig. 2, ¶ 0017, ¶ 0036, ¶ 0043, ¶ 0044). In view of the teaching of Nagata, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Hossain to have wherein a dopant concentration of the lower epitaxial layer is higher than a dopant concentration of the upper epitaxial layer because a reduction in breakdown voltage is suppressed while also reducing a resistance of an epitaxial layer (See ¶ 0017). Claim(s) 15 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2013/0302958 A1 to Hossain et al. (“Hossain”) as applied to claim 11 above, and further in view of U.S. Patent Application Publication No. 2017/0125532 A1 to Jang (“Jang”). The teaching of Hossain has been discussed above. As to claim 15, although Hossain does not further disclose wherein the forming of the plurality of trenches further comprises: forming a sacrificial oxide layer to recover damage on a sidewall or uneven region of the epitaxial layer that occurred during an etching to form the plurality of trenches, Jang does disclose wherein the forming of the plurality of trenches (16) further comprises: forming a sacrificial oxide layer to recover damage on a sidewall or uneven region of the epitaxial layer that occurred during an etching to form the plurality of trenches (16) (See Fig. 4B, ¶ 0063) such that etch damage may be recovered. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DAVID CHEN/Primary Examiner, Art Unit 2815
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Prosecution Timeline

Dec 18, 2023
Application Filed
Jul 01, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
45%
Grant Probability
94%
With Interview (+49.8%)
3y 7m (~1y 0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 685 resolved cases by this examiner. Grant probability derived from career allowance rate.

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