DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, 9-10, and 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over Yan (US Pub. No. 2021/0367081) in view of Nishikawa (US Pub. No. 2004/0206960).
Regarding claim 1, in FIGs. 5-6, Yan discloses a display device comprising: a first active layer (100, paragraph [0039]); and a first gate electrode (300, paragraph [0039]) overlapping a part of the first active layer, the first gate electrode having a hole (310, paragraph [0039]), wherein the hole of the first gate electrode does not overlap the first active layer (portions of hole 210 do not overlap the first active layer).
Yan appears not to explicitly disclose a substrate, wherein the first active layer is disposed on the substrate.
However, in FIG. 4, Nishikawa discloses a similar display device having an active layer (120, paragraph [0049]) formed on a transparent substrate (10, paragraph [0051]) used to support the various components of the display device (e.g. the transistors/active regions).
To support the various components of the display device it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form a substrate, wherein the first active layer is disposed on the substrate.
Regarding claim 3, in FIGs. 5-6, Yan discloses that an insulating layer (600, paragraph [0045]) is disposed in the hole of the first gate electrode.
Regarding claim 4, the combination of Yan and Nishikawa appears not to explicitly disclose a light blocking layer disposed between the substrate and the first active layer.
However, in FIG. 4, Nishikawa discloses a similar display device having a light blocking layer (160) disposed between the substrate (10) and the first active layer (120) to avoid leakage current (paragraphs [0023]-[0024] and [0051]-[0052]).
To avoid leakage current it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form a light blocking layer disposed between the substrate and the first active layer.
Regarding claim 5, the combination of Yan and Nishikawa discloses that the hole of the first gate electrode overlaps the light blocking layer.
Regarding claim 9, the combination of Yan and Nishikawa appears not to explicitly disclose a second active layer adjacent to the first active layer.
However, in FIG. 3, Nishikawa discloses a similar display device having multiple pixels comprising multiple transistors that include active layers (associated with Tr1, TR2, etc.) adjacent to one another to form an active matrix display device.
To form an active matrix display device it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form a second transistor including at least a second active layer adjacent to the first active layer.
Regarding claim 10, the combination of Yan and Nishikawa discloses (see Nishikawa FIGs. 3-4) a gate connection electrode (e.g. line connecting gate of Tr2 to source/drain of Tr1) electrically connecting the first gate electrode (e.g. gate of Tr2) to the second active layer (source/drain of Tr1) through contact holes of an insulating layer (e.g. layers 134/138 in FIG. 4 of Nishikawa).
Regarding claim 14, the combination of Yan and Nishikawa discloses a second gate electrode overlapping the second active layer (the second transistor must include an overlapping second gate electrode).
Regarding claim 15, the combination of Yan and Nishikawa discloses that the second gate electrode includes a hole (see Yan FIGs. 5-6).
Regarding claim 16, the combination of Yan and Nishikawa discloses that the hole of the second gate electrode overlaps the second active layer (see Yan FIGs. 5-6).
Regarding claim 17, the combination of Yan and Nishikawa discloses an insulating layer is disposed in the hole of the second gate electrode (see Yan FIGs. 5-6, element 600).
Regarding claim 18, the combination of Yan and Nishikawa appears not to explicitly disclose a gate line electrically connected to the second gate electrode.
However, the prior art well recognized that gate lines are connected to gate electrodes to provide electrical signals to the gate electrodes.
To provide electrical signals to the second gate electrode it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form a gate line electrically connected to the second gate electrode.
Regarding claim 19, the combination of Yan and Nishikawa appears not to explicitly disclose an insulating layer having a hole overlapping the gate line.
However, the prior art well recognized that insulating layers are provided and include a hole overlapping a gate line (e.g. multilayer ILD/interconnect structures) to connect the gate line to other parts of the display.
To connect the gate line to other parts of the display it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form an insulating layer having a hole overlapping the gate line.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Yan (US Pub. No. 2021/0367081) in view of Nishikawa (US Pub. No. 2004/0206960) as applied to claim 1, and further in view of Koyama (US Pub. No. 2011/0069047).
Regarding claim 22, the combination of Yan and Nishikawa appears not to explicitly disclose that first gate electrode contains titanium and aluminum.
The art however well recognized a stack including titanium and aluminum to be suitable for use as a gate electrode in a display device. See, for example, Koyama, paragraph [0116].
According to well-established patent law precedents (see, for example, M.P.E.P. § 2144.07), therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have formed the Yan disclosed first gate electrode from a stack including titanium and aluminum for its recognized suitability as a gate electrode in a display device.
Allowable Subject Matter
Claims 2, 6-8, 11-13, and 20-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, the prior art failed to disclose or reasonably suggest the claimed display device particularly characterized by an entirety of the hole of the first gate electrode does not overlap the first active layer.
Regarding claims 6-8, the prior art failed to disclose or reasonably suggest the claimed display device particularly characterized by a capacitor electrode having a hole overlapping the first gate electrode.
Regarding claim 11, the prior art failed to disclose or reasonably suggest the claimed display device particularly characterized by the hole of the first gate electrode overlapping the gate connection electrode.
Regarding claims 12-13, the prior art failed to disclose or reasonably suggest the claimed display device particularly characterized by the first active layer containing polycrystalline silicon, and the second active layer containing an oxide.
Regarding claims 20-21, the prior art failed to disclose or reasonably suggest the claimed display device particularly characterized by a part of the gate line is disposed in the hole of the insulating layer; and the hole of the insulating layer is adjacent to the second active layer, in combination with the features of claims 1, 9, 14, and 18-19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUCKER J WRIGHT whose telephone number is (571)270-3234. The examiner can normally be reached 8:30am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TUCKER J WRIGHT/ Primary Examiner, Art Unit 2891