DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. US 17/279,637 filed on 03/25/2021.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 03/18/2024 and 06/02/2025, are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Invention I, and Claims 2-5 in the reply filed on 10/22/2025 is acknowledged. Claims 6-7 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/22/2025.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives.
Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps.
Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length.
See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts.
Claim Objections
Claim 2 is objected to because of the following informalities:
Claim 2 recites “forming an EL layer comprising a region overlapping with the second conductive layer” in line 12; this should be written as “forming an electroluminescent (EL) layer comprising a region overlapping with the second conductive layer.” Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki (US20100007632A1; hereinafter Yamazaki) in view of Wilson et al. (US20090224352A1; hereinafter Wilson), further in view of Yamamoto (US20150187980A1; Yamamoto).
Regarding Claim 2, Yamazaki discloses a method for manufacturing a semiconductor device [0002], comprising:
forming a low-resistance region (photo sensor 429 including n-type semiconductor film 426 and a p-type semiconductor film 428) in a first substrate (400) to form a photoelectric conversion element (photo sensor 429), FIG. 6 reproduced below, [0131], [0140];
providing an opening portion in the first substrate (contact hole is formed in the insulating film 424 on the substrate 400), FIG. 6, [0139];
forming a first conductive layer (first connection electrode 425) in the opening portion (contact hole), FIG. 6, [0139];
forming a first transistor (TFT 409) and a second transistor (TFT 408) over [an] insulating layer (407), FIG. 6, [0132];
forming a second conductive layer (418R) electrically connected to the first conductive layer (425), FIG. 6, [0135], [0139]. Yamazaki [0135] discloses the electrode 418R (second conductive layer) is formed over the insulating film 416; and [0139] discloses a contact hole is formed in the insulating layer 424 and a connection electrode 425 (first conductive layer) is formed over 424, indicating 425 is electrically connected to underlying conductive layers, including 418R through the contact hole.
forming an EL layer (light-emitting layer 421R) comprising a region overlapping with the second conductive layer (418R), FIG. 6, [0136]; and
forming a third conductive layer (422) comprising a region overlapping with the second conductive layer (418R) and the EL layer (421R), FIG. 6, [0136].
wherein one of a source and a drain of the first transistor (source or drain of 409) is electrically connected to the low-resistance region (429), FIG. 6, [0140].
wherein one of a source and a drain of the second transistor (source or drain of 408) is electrically connected to the first conductive layer (425 through upper wirings), FIG. 6, [0134], [0139], and
wherein a light-emitting element comprising the EL layer (421R) is configured to emit visible light, [0136]. Yamazaki [0136] discloses forming a light emitting layer 421R as red, blue, and or green layers for full display, indicting the EL layer 421R is configured to emit visible light.
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Yamazaki: FIG. 6
Yamazaki does not disclose “forming an insulating layer comprising a region overlapping with the low-resistance region and a region overlapping with the first conductive layer; polishing the first substrate to expose the first conductive layer; wherein a light-emitting element comprising the EL layer is configured to emit infrared light;” In a similar art, Wilson discloses a method of manufacturing a photodiode array [0006].
Wilson discloses: forming a low-resistance region (anode/cathode region 28) in a first substrate (12) to form a photoelectric conversion element (photodiode), FIG. 1 reproduced below, [0018];
providing an opening portion (via 16) in the first substrate (12), FIGS. 1, 3, [0022];
forming a first conductive layer (conductive material 20) in the opening portion (16); FIG. 1, [0018].
polishing the first substrate (12) to expose the first conductive layer (20), FIG. 1, [0022]. Wilson [0022] discloses after forming the via 16, the first main surface 12a of the substrate may be planarized, polished and/or ground using a process such as chemical mechanical polishing (CMP), indicating that polishing the substrate 12 exposes the conductive material 20 (first conductive layer).
forming an insulating layer (dielectric material 18) comprising a region overlapping with the low-resistance region (anode/cathode region 28) and a region overlapping with the first conductive layer (20), FIG. 1, [0027];
forming a second conductive layer (30) electrically connected to the first conductive layer (20), FIG. 1, [0029].
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Wilson: FIG. 1
Wilson discloses that a method as taught improves electrical access and device performance [0005]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Yamazaki’s method in order to improve electrical access and device performance as disclosed by Wilson [0005].
Yamazaki discloses wherein a light-emitting element comprising the EL layer 421R is configured to emit visible light, [0136], but the combination of Yamazaki and Wilson does not disclose “wherein a light-emitting element comprising the EL layer is configured to emit visible light and infrared light.”
In a similar art, Yamamoto discloses a manufacturing process of an optical device [0013].
Yamamoto discloses: wherein a light-emitting element (OLED) comprising the EL layer (EL element in portion 10, FIG. 4) is configured to emit visible light [0104] and infrared light [0057].
Yamamoto [0057] discloses the light emitting portion 10 emits irradiation light IL that is in near-infrared light having a wavelength in the range of 750 nm to 3000 nm. Yamamoto [0104] discloses the light emitting portions may emit red, green, blue, and white light.
Yamamoto discloses that a method as taught provides an optical device with high quality image and high signal to noise ratio [0077]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Yamazaki and Wilson’s method in order to provide an optical device with high quality image and high signal to noise ratio as disclosed by Yamamoto [0077].
Regarding Claim 3, The combination of Yamazaki, Wilson, and Yamamoto disclose the method for manufacturing a semiconductor device according to claim 2.
Yamazaki discloses: further comprising:
attaching a second substrate (189) over the first transistor (151) and the second transistor (152), FIG. 2B, [0070].
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki in view of Wilson, further in view of Yamamoto, still further in view of Yoneda (US20130153890A1; hereinafter Yoneda).
Regarding Claim 4, The combination of Yamazaki, Wilson, and Yamamoto disclose the method for manufacturing a semiconductor device according to claim 2.
The combination of Yamazaki, Wilson, and Yamamoto does not disclose “wherein the first transistor and the second transistor each comprises a metal oxide in a channel formation region.”
In a similar art, Yoneda discloses a method of manufacturing the semiconductor device [0048].
Yoneda discloses: wherein the first transistor (150) and the second transistor (152) each comprises a metal oxide in a channel formation region (channel formation regions first semiconductor film 106 and the second semiconductor film 118 are formed of oxide semiconductor film), FIG. 1B, [0050], [0053], [0067].
Yoneda [0067] discloses the examples of oxide semiconductor used can be: In—Ga—Zn-based oxide (also referred to as IGZO), an In—Al—Zn-based oxide, an In—Sn—Zn-based oxide, which are metal oxides.
Yoneda discloses that a method as taught provides a semiconductor device with high field-effect mobility and high speed operation [0052]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Yamazaki, Wilson, and Yamamoto’s method in order to provide a semiconductor device with high field-effect mobility and high speed operation as disclosed by Yoneda [0052].
Regarding Claim 5, The combination of Yamazaki, Wilson, Yamamoto, and Yoneda disclose the method for manufacturing a semiconductor device according to claim 4.
The combination of Yamazaki, Wilson, and Yamamoto does not disclose “wherein the metal oxide comprises In, Zn, and M, wherein M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf.”
Yoneda discloses: wherein the metal oxide comprises In, Zn, and M,
wherein M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf, [0067].
Yoneda [0067] discloses the examples of oxide semiconductor used can be: In—Ga—Zn-based oxide (also referred to as IGZO), an In—Al—Zn-based oxide, an In—Sn—Zn-based oxide, which are metal oxides comprising In, Zn, and M, where M = Ga, Al, Sn.
Yoneda discloses that a method as taught reduces variation in electrical characteristics of a transistor [0066]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method in order to provide a semiconductor device with stable electrical characteristics as disclosed by Yoneda [0066].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Krishna Palaniswamy whose telephone number is (571)272-6239. The examiner can normally be reached Monday - Friday 8:30AM - 5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached on 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and tps://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Krishna J. Palaniswamy/
Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899