DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions Acknowledged
Applicant’s election without traverse of Invention 1 Species I-1 shown in Figs. 1A-1K in the response (Remarks) to Restriction has been acknowledged. Applicant stated that Claims 1-11, 15, and 16 are read on the chosen Species I-1. However, in accordance with Restriction Requirements, Species I-1 is directed to a structure with one transistor, and Species I-2 is directed to a structure with multiple transistors, while Claim 8 recites: “multiple transistors” and Claims 9-16 depend on Claim 8. Accordingly, Claims 8-16 belong to Species I-2.
Status of Claims
Claims 8-20 are withdrawn from further consideration as being drawn to nonelected inventions.
Claims 1-7 are examined on merits herein.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "115" and "113" in Fig. 1B have both been used to designate a gate electrode 115. Similar applies to reference characters “155” and “153” in Fig. G. In addition, reference characters “113o” and “114” are both has been used to designate a gate dielectric for transistor 110 in Fig. 1A and reference characters “153o and “154” have both been used to designate a gate dielectric for transistor 150 in Fig. 1A; similar objections apply for Figs. 1B and 1G. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Paragraphs 0018, 0021, 0048 of the published application US 20250203937 recite multiple times: “1121” and “1521” instead of “112i” and “152i”.
Paragraph 0021 and 0022 recite: “1130” and “1530” instead of: “113o” and “153o”.
Specification is not seemed to be enough clear with respect to an outer gate section: Abstract and paragraphs 0004, 0014 of the published application teach that an outer gate section has a horizontal portion above the center portion of the upper nanosheet, while paragraph 0021 teaches that the outer gate section also has portions extending from the substrate to this horizontal portion. Does paragraph 0021 mean that inner and outer gate sections are defined such that below the horizontal line - the outer gate section surrounds an inner gate section and inner gate section with its spacers exists only in a portion of the device in which nanosheet segments are created?
Specification is not quite clear with respect to outer spacers that are shown in Figs. 1B and 1G being cross-sections of Fig. 1A along lines B-B and G-G, accordingly: Does the claimed structure for each transistor has an outer gate spacer that surrounds a gate? If so, each transistor has only one outer spacer, not “outer spacers” as claims (starting from Claim 1) of the application claim.
Appropriate corrections/clarifications are required without introduction a new matter.
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: Claim 3 recites that the outer gate section is laterally adjacent to inner spacers, which is not supported by the specification of the application.
Claim Objections
Claim 6 is objected to because of the following informalities:
Claim 6 recites: “the transistor further includes additional outer spacers above the proximal portion and positioned laterally between and immediately adjacent to the outer spacers and the distal portion”. Since there is no figure of the application showing entirety of outer spacers “laterally between’ “the outer spacers and the distal portion”, Examiner suggests, based on transistor 150, to change the citation to the following: “the transistor further includes additional outer spacers above the proximal portion and having a lower part positioned laterally between and immediately adjacent to the outer spacers and the distal portion”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 3 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
In re Claim 3: Claim 3 recites: “the outer gate section is further positioned laterally adjacent to opposing sides of the semiconductor nanosheets and the inner spacers”. The recitation is unclear with respect to laterally adjacent outer gate section and the inner spacers, as explained in the objection to the specification.
Appropriate correction is required to clarify the claimed subject matter.
For this Office Action, the cited limitation was interpreted as: “the outer gate section is further positioned laterally adjacent to opposing sides of the semiconductor nanosheets”, e.g., the ending of the limitation was omitted from consideration.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, and 4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yao et al. (US 2021/0234017).
In re Claim 1, Yao teaches a structure comprising: a substrate 202 (Fig. 13A, paragraph 0013); and a transistor (paragraph 0011) on the substrate 202, wherein the transistor includes (Fig. 13; see also Figs. 2-12 for numbers of some elements):
semiconductor nanosheets 204a (Fig. 4, paragraph 0017) extending laterally between source/drain regions – in trenches 214 (Fig. 7, paragraph 0028 on source/drain recesses 206, and paragraph 0052 on epitaxial source/drain regions), wherein the semiconductor nanosheets 204a are stacked vertically, parallel, and physically separated and include at least a lowermost semiconductor nanosheet – a first from the bottom - and an uppermost semiconductor nanosheet – a first from the top - above the lowermost semiconductor nanosheet;
inner spacers – 216 that are adjacent to a structure with nanosheets (Figs. 6-7 on 216, paragraph 0028) - below end portions of all of the semiconductor nanosheets 204a; and
outer spacers 212 (paragraph 0013) above the end portions of the uppermost semiconductor nanosheet 204a and further extending onto the source/drain regions (those parts that are under 212 and adjacent to inner spacers), wherein
the outer spacers 212 are wider than the inner spacers 216.
In re Claim 2, Yao teaches the structure of Claim 1, wherein (Figs. 12-13)
the transistor further includes a gate with a gate electrode 260 and a gate dielectric 262 in openings 250 and 252 of Fig. 12 (paragraph 0046), wherein
the gate includes inner gate sections – in openings 252 of Fig. 12 - below center portions of the semiconductor nanosheets 204a - and an outer gate section – in opening 250 of Fig. 12 - at least above a center portion of the uppermost semiconductor nanosheet 204a, wherein
the inner spacers 216 are between the inner gate sections and the source/drain regions, and wherein
the outer spacers 212 are positioned laterally adjacent to the outer gate section.
In re Claim 4, Yao teaches the structure of Claim 2, wherein (Fig. 13A and Annotated Fig. 13A) wherein
the source/drain regions (within trenches 214) include proximal portions – PP in Annotated Fig. 13A - positioned laterally immediately adjacent to the semiconductor nanosheets 204a and isolated from the inner gate sections by the inner spacers 216, wherein the source/drain regions further have distal portions – DP in Annotated Fig. 13A, wherein
the proximal portions PP are between the semiconductor nanosheets 204a and the distal portions DP, and wherein
Annotated Fig. 13A
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heights of the distal portions Hdp are greater than heights of the proximal portions Hpp.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Yao in view of Yoon et al. (NPL).
In re Claim 5, Yao teaches the structure of Claim 4 as cited above, including the distal portion, but does not teach additional outer spacers above the distal portions and positioned laterally immediately adjacent to the outer spacers.
Yoon teaches (Fig. 1, pages 861-862) a nanosheet transistor (for example, a middle transistor) in which an outer gate spacer has a lower narrow portion with a width similar to a width of an inner spacer and a wide upper portion disposed on top of a S/D region.
Yao and Yoon teach analogous arts directed to gates all around nanosheet transistors comprised inner and outer spacers, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Yao structure in view of the Yoon device since they are from the same field of endeavor, and Yoon created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Yao device by creating a combined outer spacer with a wider upper part extending onto the S/D region, if the manufacture prefers having this shape of the upper spacer. In accordance with MPEP 2144.04. I.B, referencing In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966), the court held that changes in shape is not patentable since this is a matter of choice of a person of ordinary skill in the art in absent persuasive evidence that the particular configuration is significant.
However, in order to simplify the manufacturing process, it would have been obvious for one of ordinary skill in the art before the effective date of filing the application, not creating the outer spacer in an inverted L-shape, but to add an addition outer spacer laterally immediately adjacent to the outer spacer and disposed above the distal portion, as shown in Annotated Modified Fig. 13A, where the additional spacer is shows as AOS:
Annotated Modified Fig. 13A
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As far as Claim 3 is understood, Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20230387261) in view of Yoon et al. (NPL).
In re Claim 1, Huang teaches a structure comprising: a substrate 101 (Figs. 8A and 8B, paragraph 0011); and a transistor on the substrate 10, wherein the transistor includes (Figs. 8A and 8B):
semiconductor nanosheets 1021 (paragraphs 0013, 0015) extending laterally between source/drain regions 105 (paragraph 0018), wherein
the semiconductor nanosheets 1021 are stacked vertically, parallel, and physically separated and include at least a lowermost semiconductor nanosheet and an uppermost semiconductor nanosheet above the lowermost semiconductor nanosheet (as is clear from Figs. 8A-8B);
inner spacers 1023 (paragraph 0018) below end portions of all of the semiconductor nanosheets 1021; and
outer spacers 107 (paragraph 0020) above the end portions of the uppermost semiconductor nanosheet 1021.
Huang does not teach that the outer spacers are extending onto the source/drain regions and are wider than the inner spacers.
Yoon teaches (Fig. 1, pages 861-862) a nanosheet transistor (for example, a middle transistor) in which an outer gate spacer has a lower narrow portion with a width similar to a width of an inner spacer and a wide upper portion disposed on top of a S/D region.
Huang and Yoon teach analogous arts directed to gates all around nanosheet transistors comprised inner and outer spacers, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Huang structure in view of the Yoon device since they are from the same field of endeavor, and Yoon created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Huang device by creating outer spacers with a wider upper part extending onto the S/D region, creating by that the outer spacers wider than the inner spacers (while slightly moving isolation 1062 to provide a space for the modification) if the manufacture prefers having this shape of the upper spacer, In accordance with MPEP 2144.04. I.B, referencing In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966), the court held that changes in shape is not patentable since this is a matter of choice of a person of ordinary skill in the art in absent persuasive evidence that the particular configuration is significant.
In re Claim 2, Huang/Yoon teaches the structure of Claim 1 as cited above.
Huang/Yoon further teaches (Huang, Figs. 8A-8B and paragraphs below) that
the transistor further includes a gate 108, comprised a gate metal 1082 and a gate dielectric 1081 (paragraph 0029) wherein
the gate includes inner gate sections below center portions of the semiconductor nanosheets 1021 and an outer gate section 1081t and 1082t at least above a center portion of the uppermost semiconductor nanosheet 1021, wherein
the inner spacers 1023 are between the inner gate sections and the source/drain regions 105, and wherein
the outer spacers - modified 107, as explained for Claim 1 - are positioned laterally adjacent to the outer gate section.
In re Claim 3, Huang/Yoon teaches the structure of Claim 2 as cited above.
Huang further teaches (Fig. 8A) that the outer gate section 1081t, 1082t is further positioned laterally adjacent to opposing sides of the semiconductor nanosheets 1021 and the inner spacers (the limitation related to inner spacers is omitted from consideration due to interpretation of Claim 3).
Claims 1 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20190067441) in view of Yoon et al. (NPL).
In re Claim 1, Yang teaches a structure comprising: a substrate 10 (Fig. 1A, paragraph 0051); and a transistor on the substrate 10, wherein the transistor includes (Fig. 1A):
semiconductor nanosheets 25 (paragraphs 0051, 0075, 0080, 0003) extending laterally between source/drain regions 50 (paragraph 0054), wherein
the semiconductor nanosheets 25 are stacked vertically, parallel, and physically
separated and include at least a lowermost semiconductor nanosheet and an uppermost semiconductor nanosheet above the lowermost semiconductor nanosheet (as is clear from Fig. 1A);
inner spacers 33/37 (paragraph 0054) below end portions of all of the semiconductor nanosheets 25; and
outer spacers 40 (adjacent to dielectric 82, paragraph 0053) above the end portions of the uppermost semiconductor nanosheet 25.
Yang does not teach that the outer spacers are extending onto the source/drain regions and are wider than the inner spacers.
Yoon teaches (Fig. 1, pages 861-862) a nanosheet transistor (for example, a middle transistor) in which an outer gate spacer has a lower narrow portion with a width similar to a width of an inner spacer and a wide upper portion disposed on top of a S/D region.
Yang and Yoon teach analogous arts directed to gates all around nanosheet transistors comprised inner and outer spacers, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Yang structure in view of the Yoon device since they are from the same field of endeavor, and Yoon created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Yang device by creating outer spacers with a wider upper part extending onto the S/D region, creating by that the outer spacers wider than the inner spacers (while making slightly narrower the isolation 72 near the gate) if the manufacture prefers having this shape of the upper spacer, In accordance with MPEP 2144.04. I.B, referencing In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966), the court held that changes in shape is not patentable since this is a matter of choice of a person of ordinary skill in the art in absent persuasive evidence that the particular configuration is significant.
In re Claim 7, Yang/Yoon teaches the structure of Claim 1 as cited above, wherein, as is clear from Fig. 1A, end walls of the semiconductor nanosheets 25 and the inner spacers 33/37 bare vertically aligned below the outer spacers 40.
Allowable Subject Matter
Claim 6, in its suggested modification, contains allowable subject matter and it is objected by the current Office Action as being dependent on a rejected base claim.
Reason for Identification of Allowable Subject Matter
Re Claim 6: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 6 as: “the transistor further includes additional outer spacers above the proximal portion and having a lower part positioned laterally between and immediately adjacent to the outer spacers and the distal portion”, in combination with other limitations of Claim 6 and with all limitations of Claims 1, 2, and 4, on which Claim 6 depends.
The prior arts of record are at least the prior arts cited by the current Office Action.
Conclusion
Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible).
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/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 06/03/26
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