DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I, claims 1-16 and 32, in the reply filed on 5/6/26 is acknowledged. The traversal is on the ground(s) that the Species represent alternate material implementations of the same inventive concept and that no serious burden would be placed in the Examiner to examine the entire application. This is not found persuasive because although there is overlap in the claimed limitations, there is also limitations pertaining to separate embodiments. However, should allowable subject matter be found, Applicant can incorporate such matter into the non-elected claims if applicable and the claims can be rejoined.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 11-13, 16 and 32 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ni et al. (US 2019/0371598).
Regarding claim 1, Ni discloses a method of forming an ohmic contact structure on a semiconductor device (Abstract), the method comprising:
forming a structure, the forming comprising:
providing a Group III nitride semiconductor structure (fig. 1 and paragraph 0035);
providing a passivation layer on the Group III nitride semiconductor
structure (fig. 1 and paragraph 0035);
etching the passivation layer to form a trench, the trench exposing a
portion of the Group III nitride semiconductor structure (fig. 2 and paragraph 0036);
depositing, on the Group III nitride semiconductor structure in the trench,
a first layer comprising at least one of silicon (Si), gallium nitride (GaN), and
germanium (Ge) doped with an n-type dopant to a concentration above about
10¹⁸ cm⁻³ (N++, fig. 3 and paragraph 0037);
providing at least one metal layer on the first layer (fig. 6 and paragraph 0040); and
annealing the structure (paragraphs 0003, 0040).
Regarding claim 2, Ni further discloses wherein the Group III nitride semiconductor structure comprises at least one of gallium nitride (GaN) and aluminum gallium nitride (AIGaN) (fig. 1 and paragraph 0035).
Regarding claim 3, Ni further discloses wherein the passivation layer comprises silicon nitride (SiN) (fig. 1 and paragraph 0035).
Regarding claim 4, Ni further discloses wherein the group III nitride semiconductor structure comprises GaN and at least one layer of AIGaN on the GaN (fig. 1 and paragraph 0035).
Regarding claim 5, Ni further discloses wherein the etching comprises etching the passivation layer to form a trench, the trench exposing a portion of the AlGaN (fig. 2 and paragraph 0036).
Regarding claim 6, Ni further discloses wherein the etching comprises etching the passivation layer to form a trench, the trench exposing a portion of the GaN (fig. 2 and paragraph 0036).
Regarding claim 7, Ni further discloses wherein the trench comprises a first side wall and a second side wall that are vertical (fig. 2 and paragraph 0036).
Regarding claim 11, Ni further discloses wherein the first layer has a thickness of at least from about 50 Å to about 500 Å (paragraph 0037).
Regarding claim 12, Ni further discloses wherein the first layer has a thickness of from about 50 Å to about 5000 Å (paragraph 0037).
Regarding claim 13, Ni further discloses wherein the providing at least one metal layer on the first layer comprises depositing nickel silicide (NiSi) (paragraph 0040).
Regarding claim 16, Ni further discloses wherein the semiconductor device comprises a high electron mobility transistor (HEMT) (Abstract and paragraph 0035).
Regarding claim 32, Ni discloses a semiconductor device having an ohmic contact (Abstract), the semiconductor device comprising:
a Group III nitride semiconductor structure (Abstract, fig. 6);
a passivation layer on the Group III nitride semiconductor structure (Passivation, fig. 6);
a trench that extends through the passivation layer and through at least a
portion of the Group III nitride semiconductor structure (figs. 2, 6 and paragraph 0036);
a first layer on the Group III nitride semiconductor structure in the trench, the
first layer comprising at least one of silicon (Si), gallium nitride (GaN), and germanium
(Ge) doped with an n-type dopant to a concentration above about 10¹⁸ cm⁻³ (N++, fig. 3 and paragraph 0037); and
an ohmic contact on the first layer in the trench (fig. 6 and paragraph 0040).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-10 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Ni et al. (US 2019/0371598).
Regarding claim 8, Ni discloses the method of Claim 1, as mentioned above. Ni’s disclosure of the etching process to form the trenches (fig. 2 and paragraph 0036) depicts a figure with vertical sidewalls. Ni does not explicitly disclose wherein the trench comprises at least one of a first side wall and a second side wall that are sloped. However, it would have been obvious to one of ordinary skill in the art at the time of filing to have at least one of a first side wall and a second wall that are sloped given the known state of semiconductor etching at the time of filing.
Regarding claims 9-10, Ni discloses the method of claim 1, as mentioned above. Ni further dislcoses wherein the depositing comprises MOCVD as an example, on
the Group III nitride semiconductor structure in the trench, the at least one of silicon
(Si), gallium nitride (GaN), and germanium (Ge) doped with an n-type dopant to a
concentration above about 10¹⁸ cm⁻³ (paragraph 0037). Ni does not explicitly disclose sputtering or LPCVD, however, such deposition techniques were just as well known in the art as MOCVD and would therefore be deemed obvious to one of ordinary skill in the art at the time of filing.
Regarding claim 14, Ni discloses the method of claim 1, as mentioned above. Ni does not explicitly disclose wherein the at least one metal layer has a thickness of from about 1000 Å to about 2000 Å. However, such thickness range would be deemed as obvious to one of ordinary skill in the art at the time of filing.
Regarding claim 15, Ni discloses the method of claim 1, as mentioned above. Ni does not explicitly disclose wherein the annealing comprises annealing the structure for a time period from about 200 seconds to about 1,000 seconds at a temperature of from about 800° C to about 1000° C. Ni in fact gives no details about the annealing, however, the broad range of annealing the structure for a time period from about 200 seconds to about 1,000 seconds at a temperature of from about 800° C to about 1000° C would be considered convention in the art and therefore obvious to one of ordinary skill in the art at the time of filing.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent 10403718 discloses forming a low resistance ohmic contact structure on a Group III nitride semiconductor structure using a heavily doped first layer in a trench and coupled to an ohmic metal.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 8:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DOUGLAS M MENZ/Primary Examiner, Art Unit 2897 7/14/26
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