DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-16 and 58-61 in the reply filed on 05/15/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 61 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (“The morphologies and the chemical states of the multiple zincating deposits on Al pads of Si” Thin Solid Films 288 (1996) pages 36-40, See IDS filed 10/03/2025, hereinafter Lin)
With regards to claim 61, Lin discloses a method (FIG. 1) for electroless deposition of a metal layer on a semiconductor device on a semiconductor wafer, the method comprising:
depositing a first activation layer (first zincating process, see FIG. 1) on the semiconductor wafer; (Si wafter with Al)
providing the semiconductor wafer in an etchant bath for a first process period for the first activation layer; (first acidic cleansing 5s after first zincating process, see FIG. 1. See also FIG. 3, where the first zincation layer is a part of the acidic cleaning and some is left over after the cleaning)
performing a rinse process (second rinse, see FIG. 1) on the semiconductor wafer;
providing the semiconductor wafer in the etchant bath (second acidic etching, 5s, See FIG. 1.) for a second process period for the first activation layer; (See also FIG. 3, where the first zincation layer is etched by the etching and has zinc left over) and
depositing a second activation layer (third zincating process, see FIG. 1) on the semiconductor wafer. (see FIG. 1)
Allowable Subject Matter
Claims 1-16 and 58-60 are allowed.
The following is an examiner’s statement of reasons for allowance: None of the cited references teach or suggest, either alone or in combination, at least “providing a semiconductor wafer, the semiconductor wafer comprising one or more wide bandgap semiconductor devices; performing an activation layer deposition process on at least a portion of the semiconductor …providing the semiconductor wafer in the etchant bath for a second process period,” as recited in claim 1, and “wherein the multi-dip activation layer deposition process provides a nodule rejection yield for the semiconductor wafer of at least about 65%,” as recited in claim 58.
Response to Arguments
Applicant's arguments filed 09/16/2026 have been fully considered but they are not persuasive.
Examiner notes that Applicant has not argued against the first zincating process being the first activation layer. However, Applicant has not explained what is meant by the limitations “providing the semiconductor wafer in an etchant bath for a first process period for the first activation layer” and “providing the semiconductor wafer in the etchant bath for a second process period for the first activation layer.” Examiner has interpreted this language to suggest that the first activation layer (i.e. the zinc layer) is present during both the first etchant and the second baths. However, Lin shows in FIG. 3 that the zinc is present during the first and second etchant baths, and thus meets the limitations of the claims.
Therefore, claim 61 is properly rejected.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Sinha et al. (US 20040033687 A1, hereinafter Sinha) – electroless deposition processes
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812
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