Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of group I, claims 1-7 in the reply filed on 12/30/25 is acknowledged. Claims 8-10 are withdrawn from further consideration by the examiner, 37 C.F.R. 1.142(b) as being drawn to a non-elected invention.
Information Disclosure Statement
The information disclosure statements filed 9/8/23 have been considered.
Oath/Declaration
Oath/Declaration filed on 9/8/23 has been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 6 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Higashino et al. (U.S. Patent Publication No. 2010/0213594).
Referring to figures 6-54, Higashino et al. teaches a semiconductor chip manufacturing method, comprising:
preparing a stacked substrate (1W) including a first semiconductor substrate (1S), a device layer (see paragraphs# 76-79), a separation layer (4a), and a third semiconductor substrate (4) in this order (see figures 6-7, paragraph# 97);
dicing the first semiconductor substrate, the device layer, and the separation layer (see figures 9-10, paragraphs# 99-102);
attaching the diced stacked substrate to a tape (10a) from an opposite side to the third semiconductor substrate, and mounting the diced stacked substrate to a frame (10b) with the tape therebetween (see figures 14, paragraph# 109);
radiating, after mounting the stacked substrate to the frame, a laser beam penetrating the third semiconductor substrate to the separation layer to form a modification layer at an interface between the third semiconductor substrate and the separation layer, or at an inside of the separation layer (see paragraph# 111); and
separating the third semiconductor substrate and the separation layer starting from the modification layer formed at the interface between the third semiconductor substrate and the separation layer or at the inside of the separation layer (see paragraphs# 113-116, figures 6-21).
Regarding to claim 2, the stacked substrate includes a gettering layer formed on a surface of the first semiconductor substrate opposite to the device layer before the dicing, and the dicing includes dicing the gettering layer (see paragraph# 98, see figure 8).
Regarding to claim 6, the mounting of the stacked substrate (W) to the frame (10b) includes attaching a die attach film formed on a surface of the tape (10a) and the first semiconductor substrate to face each other (see figure 14).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Higashino et al. (U.S. Patent Publication No. 2010/0213594) as applied to claims 1-2, 6 in view of Yamazaki et al. (U.S. Patent Publication No. 2008/0280417).
Referring to figures 6-54, Higashino et al. teaches a semiconductor chip manufacturing method, comprising:
preparing a stacked substrate (1W) including a first semiconductor substrate (1S), a device layer (see paragraphs# 76-79), a separation layer (4a), and a third semiconductor substrate (4) in this order (see figures 6-7, paragraph# 97);
dicing the first semiconductor substrate, the device layer, and the separation layer (see figures 9-10, paragraphs# 99-102);
attaching the diced stacked substrate to a tape (10a) from an opposite side to the third semiconductor substrate, and mounting the diced stacked substrate to a frame (10b) with the tape therebetween (see figures 14, paragraph# 109);
radiating, after mounting the stacked substrate to the frame, a laser beam penetrating the third semiconductor substrate to the separation layer to form a modification layer at an interface between the third semiconductor substrate and the separation layer, or at an inside of the separation layer (see paragraph# 111); and
separating the third semiconductor substrate and the separation layer starting from the modification layer formed at the interface between the third semiconductor substrate and the separation layer or at the inside of the separation layer (see paragraphs# 113-116, figures 6-21).
However, the reference does not clearly teach the gettering layer is a thermal oxide layer formed by thermally oxidizing the surface of the first semiconductor substrate.
Yamazaki et al. teaches the gettering layer is a thermal oxide layer formed by thermally oxidizing the surface of the first semiconductor substrate (see paragraph# 106, figure 8a).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention a thermal oxide layer formed by thermally oxidizing the surface of the first semiconductor substrate in Higashino et al as taught by Yamazaki et al. because thermal oxide would provide excellent interface and high electrical layer.
Allowable Subject Matter
Claims 4-5, 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
None of the prior art teaches or suggests the stacked substrate includes a die attach film formed on a surface of the gettering layer opposite to the first semiconductor substrate before the dicing, and the dicing includes dicing the die attach film (in claim 4), the stacked substrate includes a die attach film formed on a surface of the first semiconductor substrate opposite to the device layer before the dicing, and the dicing includes dicing the die attach film (in claim 5) and; the device layer includes a first device layer formed on a surface of the first semiconductor substrate, and a second device layer bonded to the first device layer (in claim 7).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
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/THANH T NGUYEN/Primary Examiner, Art Unit 2893