DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-7, and 10-13 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Yasumoto (US 4, 612, 083).
Regarding claim 1, Yasumoto discloses a method for manufacturing a semiconductor device, comprising: providing a first integrated circuit element (10’) including a first semiconductor substrate (Fig,1, numeral 12’’) having a semiconductor element (14’) and a first wiring layer (20’) having a first insulating film (16’); (22’) and a first electrode (20’), the first wiring layer (20’) being provided on a surface of the first semiconductor substrate (12’); providing a second integrated circuit element (10) including a second semiconductor substrate (12) having a semiconductor element (14) and a second wiring layer (20) having a second insulating film (16); (22) and a second electrode (20), the second wiring layer (20) being provided on a surface of the second semiconductor substrate (12); bonding the first insulating film (16’); (22’) of the first integrated circuit element and the second insulating film (16); (22) of the second integrated circuit element to each other (Fig. 1F; column 6, lines 58-67)), and bonding the first electrode (20’) of the first integrated circuit element and the second electrode (20) of the second integrated circuit element to each other (Fig.1F; column 7, lines 20-35), wherein the first insulating film includes a first inorganic insulating layer (16’) containing an inorganic insulating material and a first organic insulating layer (22’) containing an organic insulating material, and the first organic insulating layer (22’) is located on a first bonding surface side of the first integrated circuit element (10’) opposite to the first semiconductor substrate (12’), wherein the second insulating film includes a second inorganic insulating layer (16) containing an inorganic insulating material and a second organic insulating layer (22) containing an organic insulating material, and the second organic insulating layer is located on a second bonding surface side of the second integrated circuit element opposite to the second semiconductor substrate (12), wherein a thickness of the first organic insulating layer (16’) is smaller than a thickness of the first inorganic insulating layer (22’)and a thickness of the second organic insulating layer (16) is smaller than a thickness of the second inorganic insulating layer (22) (Fig 1d; column 5, lines 60-65; note: thickness of (20) is 1.5 mm, from (14) and 0.5mm from (16), i.e. thickness of (16) is 1 mm and thickens of (22) is 0.5mm).
Regarding claim 2, Yasumoto discloses wherein the organic insulating material contained in at least one of the first organic insulating layer and the second organic insulating layer has a Young's modulus of 7.0 GPa or less (column 6, lines 1-10; note: polyimide resin).
Regarding claim 3, Yasumoto discloses wherein the organic insulating material contained in at least one of the first organic insulating layer and the second organic insulating layer has a Young's modulus of 3.0 GPa or less (column 6, lines 1-10; note: polyimide resin).
Regarding claim 4, Yasumoto discloses wherein the organic insulating material contained in at least one of the first organic insulating layer and the second organic insulating layer contains polyimide, (column 6, lines 1-10).
Regarding claim 5, Yasumoto discloses the first inorganic insulating layer is formed as a plurality of layers (Fig.2, numeral 28’, 44’), the first organic insulating layer is formed as a single layer (Fig.2, numeral 46’), the second inorganic insulating layer is formed as a plurality of layers (Fig.2, numerals 28, 44), and the second organic insulating layer is formed as a single layer (Fig.2, numeral 44).
Regarding claim 6, Yasumoto discloses wherein at least one of the first organic insulating layer and the second organic insulating layer has a thickness of 10 mm or less Fig 1d; column 5, lines 60-65; note: thickness of (20) is 1.5 mm, from (14) and 0.5mm from (16), i.e. thickness of (16) is 1 mm and thickens of (22) is 0.5mm).
Regarding claim 7, Yasumoto discloses polishing the first organic insulating layer and the first electrode of the first integrated circuit element; and polishing the second organic insulating layer and the second electrode of the second integrated circuit element (column 6, lines 1-25; Figs. 1d, 1e).
Regarding claim 10, Yasumoto discloses a semiconductor device, comprising: a first integrated circuit element including a first semiconductor substrate (Fig. 1f, numeral 12’) having a semiconductor element (14’) and a first wiring layer (20’) having a first insulating film (16’); (22’) and a first electrode (20’), the first wiring layer being provided on a surface of the first semiconductor substrate (12’); and a second integrated circuit element (10) including a second semiconductor substrate (12) having a semiconductor element (14) and a second wiring layer (20) having a second insulating film (16); (22) and a second electrode (20), the second wiring layer being provided on a surface of the second semiconductor substrate (10), the second integrated circuit element being bonded to the first integrated circuit element, wherein the first insulating film includes a first inorganic insulating layer containing an inorganic insulating material and a first organic insulating layer containing an organic insulating material (Fig.1F), and the first organic insulating layer (22’) is located on a first bonding surface side of the first integrated circuit element opposite to the first semiconductor substrate, wherein the second insulating film includes a second inorganic insulating layer (16) containing an inorganic insulating material (column 4, lines 55-60) and a second organic insulating layer (22) containing an organic insulating material (column , lines 1-5), and the second organic insulating layer is located on a second bonding surface side of the second integrated circuit element opposite to the second semiconductor substrate (12), wherein the first organic insulating layer and the second organic insulating layer are bonded to each other (Fig.1F), and the first electrode and the second electrode are bonded to each other, and wherein a thickness of the first organic insulating layer is smaller than a thickness of the first inorganic insulating layer, and a thickness of the second organic insulating layer is smaller than a thickness of the second inorganic insulating layer (Fig 1d; column 5, lines 60-65; note: thickness of (20) is 1.5 mm, from (14) and 0.5mm from (16), i.e. thickness of (16) is 1 mm and thickens of (22) is 0.5mm).
Regarding claim 11, Yasumoto discloses an integrated circuit element to be bonded to another integrated circuit element to manufacture a semiconductor device, comprising: a semiconductor substrate (Fig.1, numeral 12) having a first surface and a second surface, a semiconductor element (14) being formed at least on the first surface or inside the semiconductor substrate (12); and a wiring layer (20) provided on the second surface of the semiconductor substrate (12), wherein the wiring layer includes: an inorganic insulating layer (16) provided on the second surface of the semiconductor substrate (12); an organic insulating layer (22) provided on the inorganic insulating layer (16) and exposed to outside of the wiring layer (20); and an electrode (20) electrically connected to the semiconductor element (14) of the semiconductor substrate (12) and passing through the inorganic insulating layer (16) and the organic insulating layer (22) to be exposed to outside from the organic insulating layer (22), wherein a thickness of the organic insulating layer is smaller than a thickness of the inorganic insulating layer (Fig 1d; column 5, lines 60-65; note: thickness of (20) is 1.5 mm, from (14) and 0.5mm from (16), i.e. thickness of (16) is 1 mm and thickens of (22) is 0.5mm), and an organic insulating material contained in the organic insulating layer has a Young's modulus of 7.0 GPa or less (column 6, lines 1-10; note: polyimide resin).
Regarding claim 12, Yasumoto discloses providing a semiconductor substrate (Fig. 1F, numeral 12) having a first surface and a second surface, a semiconductor element (14) being formed at least on the first surface or inside the semiconductor substrate (12); and forming a wiring layer (20) on the second surface of the semiconductor substrate, wherein the forming of the wiring layer (20) includes: forming an inorganic insulating layer (16) on the second surface of the semiconductor substrate (12); forming an inner layer electrode (18) passing through the inorganic insulating layer (16) so as to be electrically connected to the semiconductor element (14); forming an organic insulating layer (22) on the inorganic insulating layer (16); and forming an outer layer electrode (20) passing through the organic insulating layer (22)so as to be electrically connected to the inner layer electrode (18), wherein a thickness of the organic insulating layer is smaller than a thickness of the inorganic insulating layer(Fig 1d; column 5, lines 60-65; note: thickness of (20) is 1.5 mm, from (14) and 0.5mm from (16), i.e. thickness of (16) is 1 mm and thickens of (22) is 0.5mm), and wherein an organic insulating material contained in the organic insulating layer has a Young's modulus of 7.0 GPa or less (column 6, lines 1-10; note: polyimide resin). .
Regarding claim 13, Yasumoto discloses wherein the organic insulating layer (22) is formed after forming the outer layer electrode (20) (Figs. 1a-1C).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yasumoto as applied to claim 7 above, and further in view of Kagawa (US 2013/0009321).
Regarding claim 8, Yasumoto discloses in the polishing of the first integrated circuit element, the first organic insulating layer and the first electrode a surface of the first organic insulating layer has the same height as a surface of the first electrode (Figs. 1d, 1e) and surface of the second organic insulating layer has the same height as a surface of the second electrode (Figs. 1d, 1e)
Yasumoto does not discloses polishing using a chemical mechanical polishing.
Kagawa however discloses polishing using a chemical mechanical polishing ([0108]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Yasumoto with Kagawa to perform polishing using a chemical mechanical polishing because this one of typical methods for forming flattening surfaces (Kagawa, [0108]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Yasumoto as applied to claim 7 above, and further in view of Kayaba (US 2021/0391292).
Regarding claim 9, Yasumoto does not disclose (in the polishing of the first integrated circuit element, polishing is performed so that a surface roughness of the surface of the first organic insulating layer is 2 nm or less, and wherein, in the polishing of the second integrated circuit element, polishing is performed so that a surface roughness of the surface of the second organic insulating layer is 2 nm or less.
Kayaba however discloses polishing is performed so that a surface roughness of the surface of the organic insulating layers (Fig.3B, numeral 34) is 2 nm or less ([0355]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Yasumoto with Kayaba to perform polishing so that a surface roughness of the surface of the organic insulating layers is 2 nm or less for the purpose of improving bonding process.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JULIA SLUTSKER whose telephone number is (571)270-3849. The examiner can normally be reached Monday-Friday, 9 am-6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JULIA SLUTSKER/ Primary Examiner, Art Unit 2891