DETAILED ACTION
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/17/25 is in compliance with the provisions of 37 CFR 1.97 and 1.98. Accordingly, the information disclosure statement has been considered by the examiner.
The information disclosure statement (IDS) submitted on 10/24/23 is in compliance with the provisions of 37 CFR 1.97 and 1.98. Accordingly, the information disclosure statement has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Recesses around electrodes at direct bonding surface
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 8-9 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant) regards as the invention.
Claim 8 recites the limitation “wherein the second insulating layer contains an inorganic insulating material”.
The metes and bounds of the claimed limitation can not be determined for the following reasons: the limitation “an inorganic insulating material” lacks proper antecedent basis, as it is already recited in claim 1 (“wherein the first insulating layer contains an inorganic insulating material”). It is unclear whether the instance in claim 8 requires the same inorganic insulating material as in claim 1, or if it could be a different material.
Claim 9 recites the limitation “wherein the inorganic insulating material contained in at least one insulating layer of the first insulating layer and the second insulating layer is silicon dioxide, silicon nitride, or silicon oxynitride”.
The metes and bounds of the claimed limitation can not be determined for the following reasons: the limitation “the inorganic insulating material” was already recited in claim 1, but claim 1 does not otherwise recite limitations about the material of the second insulating layer. It is unclear if the first insulating layer and the second insulating layer need to have the same inorganic insulating material, or if only one of them needs to have the inorganic insulating material; it is unclear if each of the first and second insulating layers need to comprise one of silicon dioxide, silicon nitride, or silicon oxynitride, or if only one of them needs to comprise silicon dioxide, silicon nitride, or silicon oxynitride.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102, some of which form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-14 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US 2014/0264948 A1 (“Chou”).
Chou teaches, for example:
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Chou teaches:
1. A method for manufacturing a semiconductor device (see Figs. 1-10 and accompanying text), comprising:
providing a first integrated circuit element (e.g. 100 as shown in Fig. 5 or Fig. 10) including a first semiconductor substrate (e.g. 102, see e.g. para 9) having a semiconductor element (e.g. 104, see e.g. para 9) and a first wiring layer (e.g. comprising 106s, 108s, 110, and 112s) having a first insulating layer (e.g. comprising one or more of the 108s and 110) and a first electrode (e.g. 112), the first wiring layer being provided on a surface of the first semiconductor substrate (see e.g. Figs. 1, 5, or 10);
providing a second integrated circuit element (e.g. 200 as shown in Fig. 9 or Fig. 10) including a second semiconductor substrate (e.g. 202, see e.g. para 17) having a semiconductor element (e.g. 204, see e.g. para 17) and a second wiring layer (e.g. comprising 206s, 208s, 210 and 212s) having a second insulating layer (e.g. comprising one or more of the 208s and 210) and a second electrode (e.g. 212), the second wiring layer being provided on a surface of the second semiconductor substrate (see e.g. Figs. 6 or 10);
bonding the first insulating layer of the first integrated circuit element and the second insulating layer of the second integrated circuit element to each other (see e.g. Fig. 10 and para 23); and
bonding the first electrode of the first integrated circuit element and the second electrode of the second integrated circuit element to each other (see e.g. Fig. 10 and para 23),
wherein the first insulating layer contains an inorganic insulating material (see e.g. para 2, 12), and
wherein a plurality of first openings (e.g. one or more 116s) recessed toward the first semiconductor substrate from a first bonding surface (e.g. top surface of 100) bonded to the second insulating layer are provided at positions in the first insulating layer different from an arrangement position of the first electrode (the openings are near the pads 112, but not at the same positions thereof), and the plurality of first openings discontinuously surround the first electrode (see e.g. para 25, where the openings may be at locations 116 and 216 that do not extend into regions 18 of Fig. 11).
2. The method for manufacturing a semiconductor device according to claim 1, wherein the plurality of first openings are provided such that the first electrode is not exposed to each side surface of the plurality of first openings (see e.g. Figs. 10-11; a single electrode 112, e.g. leftmost 112 in Fig. 10, is not exposed to each side surface of each 116, e.g. to 116s around the rightmost 112 in Fig. 10).
3. The method for manufacturing a semiconductor device according to claim 1, wherein the plurality of first openings are provided such that the first semiconductor substrate is not exposed to each bottom surface of the plurality of first openings (see e.g. Fig. 10).
4. The method for manufacturing a semiconductor device according to claim 1, wherein each of the plurality of first openings has an opening shape closed in a planar direction of the first insulating layer (see e.g. Figs. 10-11).
5. The method for manufacturing a semiconductor device according to claim 1, wherein a width in its short-length direction or a diameter of each of the plurality of first openings is smaller than a width in its short-length direction or a diameter of the first electrode (see e.g. Fig. 11).
7. The method for manufacturing a semiconductor device according to claim 1, wherein the plurality of first openings are formed by dry-etching the first insulating layer of the first integrated circuit element (see e.g. para 14).
8. The method for manufacturing a semiconductor device according to claim 1,
wherein the second insulating layer contains an inorganic insulating material (see e.g. para 17, 23), and wherein a plurality of second openings recessed toward the second semiconductor substrate from a second bonding surface bonded to the first insulating layer are provided at positions in the second insulating layer different from an arrangement position of the second electrode (the openings are near the pads 212, but not at the same positions thereof), and
the plurality of second openings discontinuously surround the second electrode (see e.g. para 25, where the openings may be at locations 116 and 216 that do not extend into regions 18 of Fig. 11; see also Fig. 10).
9. The method for manufacturing a semiconductor device according to claim 1, wherein the inorganic insulating material contained in at least one insulating layer of the first insulating layer and the second insulating layer is silicon dioxide, silicon nitride, or silicon oxynitride (see e.g. para 12, 27).
10. A semiconductor device (see e.g. Fig. 10), comprising:
a first integrated circuit element (e.g. 100 as shown in Fig. 5 or Fig. 10) including a first semiconductor substrate (e.g. 102, see e.g. para 9) having a semiconductor element (e.g. 104, see e.g. para 9) and a first wiring layer having a first insulating layer (e.g. comprising 106s, 108s, 110, and 112s) and a first electrode (e.g. 112), the first wiring layer being provided on a surface of the first semiconductor substrate (see e.g. Figs. 1, 5, or 10); and
a second integrated circuit element (e.g. 200 as shown in Fig. 9 or Fig. 10) including a second semiconductor substrate (e.g. 202, see e.g. para 17) having a semiconductor element (e.g. 204, see e.g. para 17) and a second wiring layer (e.g. comprising 206s, 208s, 210 and 212s) having a second insulating layer (e.g. comprising one or more of the 208s and 210) and a second electrode (e.g. 212), the second wiring layer being provided on a surface of the second semiconductor substrate (see e.g. Figs. 6 or 10),
wherein the first insulating layer of the first integrated circuit element and the second insulating layer of the second integrated circuit element are bonded to each other (see e.g. Fig. 10 and para 23),
wherein the first electrode of the first integrated circuit element and the second electrode of the second integrated circuit element are bonded to each other (see e.g. Fig. 10 and para 23),
wherein the first insulating layer contains an inorganic insulating material (see e.g. para 2, 12, 27), and
wherein a plurality of first openings (e.g. one or more 116s) recessed toward the first semiconductor substrate from a first bonding surface bonded to the second insulating layer are provided at positions in the first insulating layer different from an arrangement position of the first electrode (the openings are near the pads 112, but not at the same positions thereof), and the plurality of first openings discontinuously surround the first electrode (see e.g. para 25, where the openings may be at locations 116 and 216 that do not extend into regions 18 of Fig. 11).
11. An integrated circuit element (see e.g. Figs. 1 or 5) to be bonded to another integrated circuit element (see e.g. Fig. 10) to manufacture a semiconductor device, comprising:
a semiconductor substrate (e.g. 102, see e.g. para 9) having a first surface and a second surface,
a semiconductor element (e.g. 104, see e.g. para 9) being formed at least on the first surface or inside the semiconductor substrate; and
a wiring layer (e.g. comprising 106s, 108s, 110, and 112s) provided on the second surface of the semiconductor substrate,
wherein the wiring layer includes:
an inorganic insulating layer (e.g. comprising one or more of the 108s and 110) (see e.g. para 2, 12) provided on the second surface of the semiconductor substrate; and
an electrode (e.g. 112) that is electrically connected to the semiconductor element of the semiconductor substrate and passes through the inorganic insulating layer to be exposed to an outside from the inorganic insulating layer (see e.g. Fig. 5), and
wherein a plurality of openings (e.g. one or more 116s) recessed toward the semiconductor substrate are provided at positions in the inorganic insulating layer different from an arrangement position of the electrode (the openings are near the pads 112, but not at the same positions thereof), and
the plurality of openings discontinuously surround the electrode (see e.g. para 25, where the openings may be at locations 116 and 216 that do not extend into regions 18 of Fig. 11).
12. A method for manufacturing the integrated circuit element according to claim 11 to be bonded to another integrated circuit element to manufacture a semiconductor device, comprising:
providing a semiconductor substrate (e.g. 102, see e.g. para 9) having a first surface and a second surface, a semiconductor element (e.g. 104, see e.g. para 9) being formed at least on the first surface or inside the semiconductor substrate; and
forming a wiring layer (e.g. comprising 106s, 108s, 110, and 112s) on the second surface of the semiconductor substrate, wherein the forming of the wiring layer includes: forming an inorganic insulating layer (see e.g. para 2, 12, 27) on the second surface of the semiconductor substrate;
forming an electrode (e.g. 112) passing through the inorganic insulating layer so as to be electrically connected to the semiconductor element; and
forming a plurality of openings (e.g. one or more 116s) recessed toward the semiconductor substrate at positions in the inorganic insulating layer different from an arrangement position of the electrode, the plurality of openings discontinuously surrounding the electrode (see e.g. para 25, where the openings may be at locations 116 and 216 that do not extend into regions 18 of Fig. 11).
13. The method for manufacturing an integrated circuit element according to claim 12 wherein, in the forming of the openings, the openings are formed by dry-etching the inorganic insulating layer (see e.g. para 14).
14. The method for manufacturing an integrated circuit element according to claim 12 wherein the forming of the openings is performed (see e.g. Fig. 3) after the forming of the electrode (see e.g. Fig. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou.
Chou teaches claim 1, but not explicitly wherein a ratio of a total area of the plurality of first openings to a total area of the first insulating layer in the planar direction is 65% or less. However, this percentage is obvious, see e.g. Figs. 10-11. While drawings are not to scale, the percentage is obviously quite small as disclosed, and specific small values would have been found by one of ordinary skill in the art.
It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou in view of JP 2016-181531 (“Sony”) (see Applicant-provided copy with English translation, provided on 10/24/23).
Chou teaches claim 12, but does not explicitly teach wherein the forming of the electrode is performed after the forming of the openings.
Sony teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Chou wherein the forming of the electrode is performed after the forming of the openings (see e.g. Fig. 16, and associated text, wherein trenches PM’ are formed in SiO2 before the formation of metal layer M.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Sony to the invention of Chou The motivation to do so is that the combination produces the predictable results of forming the trenches and pads in either of the two possible orders (pad, then trench; or trench, then pad) as taught by Chou and Sony.
Since there are logically only two orders to form the features, and both are known in the art, then it is obvious to try either order as a predictable solution with a reasonable expectation of success (see e.g. MPEP 2141).
It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
Conclusion
Conclusion / Prior Art
The prior art made of record, because it is considered pertinent to applicant's disclosure, but which is not relied upon specifically in the rejections above, is listed on the Notice of References Cited.
Conclusion / Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kevin Parendo/Primary Examiner, Art Unit 2896
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