DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01. The omitted elements are: the fifth through eighth wiring. Claim 1 does not establish fifth through eighth wiring, while claim 4 jumps to ninth and tenth wiring. It appears that claim 4 should depend upon claim 3 to be definite and not omit essential elements from the claim progression.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Koyama et al US 2011/0316818.
Pertaining to claim 1, Koyama teaches a display device comprising:
a display portion;
a first wiring See Figure 2B marked up below;
a second wiring See Figure 2B marked up below;
a third wiring See Figure 2B marked up below; and
a fourth wiring See Figure 2B marked up below, wherein the display portion includes a first pixel, a second pixel, and a third pixel, See Figure 2B marked up below
wherein the second pixel is positioned between the first pixel and the third pixel in a plan view See Figure 2B marked up below,
wherein the first pixel, the second pixel, and the third pixel each include a first subpixel and a second subpixel Koyama teaches subpixels [0002][0003] and the subpixels are indicated by elements 151 through 153 as shown in Figure 2B,
wherein the first wiring is configured to apply a first potential [0084] to the second subpixel included in the first pixel,
wherein the second wiring is configured to apply the first potential [0084] to the first subpixel included in the second pixel,
wherein the third wiring is configured to apply the first potential [0084] to the second subpixel included in the second pixel,
wherein the fourth wiring is configured to apply the first potential [0084] to the first subpixel included in the third pixel,
wherein the first wiring and the second wiring are adjacent to each other See Figure 2B marked up below,
wherein the third wiring and the fourth wiring are adjacent to each other See Figure 2B marked up below, and
wherein a distance between the first wiring and the second wiring is shorter than a distance between the third wiring and the fourth wiring. See Figure 2B marked up below which includes repeated pixels and shown in Figure 2A. Note that “configured to apply” is broad and a statement of intended use. Koyama teaches a wiring structure capable of being configured to provide potentials, be them the same or different, and controlled by signal line circuit 12, which is taught in paragraph [0084].
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Pertaining to claim 2, Koyama teaches the display device according to claim 1,
wherein the first subpixel is configured to control light corresponding to a first color selected from red, green and blue [0002], and
wherein the first subpixel is configured to control light corresponding to a first color selected from red, green and blue [0002]
Claim(s) 13-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matsueda et al US 2004/0115989 and further in view of Kawasaki et al US 2007/0242178.
Pertaining to claim 13, Matsueda teaches a method for manufacturing a display device comprising a display portion over a first substrate, comprising the steps of:
forming n transistors See Figure 1 elements 10, n being an integer greater than or equal to 2, arranged in a matrix in a region to be the display portion over the first substrate see Figure 1; and
forming n light-emitting elements arranged in a matrix over the n transistors See Figure 1 elements 10 represent pixels and pixels contain transistors [0049]
wherein the n wirings Vdd are electrically connected to the n transistors one by one,
wherein the first wiring Vddl and the second wiring Vdd are adjacent to each other see Figure 5,
wherein among the n transistors, a first transistor is electrically connected to the first wiring, and a second transistor is electrically connected to the second wiring see Figure 7 elements Vsel and Vsel, and
wherein the first wiring Vdd and the second wiring Vdd are placed between a channel formation region of the first transistor and a channel formation region of the second transistor in a plan view The elements Vdd and Vddas illustrated in Figure 5 run between adjacent pixels and are next to each other, therefore because each pixel contains a transistor and a transistor contains a channel region, the first and second wirings are between the channel formation regions of the transistors in each of the adjacent pixels See Figure 5 marked up below.
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Matsueda broadly described the process for forming the metal wiring lines as “patterning” [0051] but doesn’t detail this further. However, what is described in the claims is a generic photolithography process involving masking, exposure and etching. Kawasaki teaches a generic photolithography process including a process to form wiring 11 [0024] in a display device. Including:
depositing a first conductive film over the n transistors [0007];
depositing a photo resist over the first conductive film [0017][0018];
transferring a desired pattern through light exposure treatment on the photo resist onto the region to be the display portion [0018];
forming the desired pattern on the photo resist through development treatment on the photo resist [0018];
forming n wirings by removing part of the first conductive film with the use of the desired pattern [0019][0020]
wherein the step of transferring includes a step of performing light exposure on a plurality of divided light exposure regions over the region to be the display portion (the pixel regions are all exposed to this process)
wherein among the n wirings, a first wiring is formed through light exposure in a first light exposure region, and a second wiring is formed through light exposure in a second light exposure region, See Paragraphs [0013]-[0024] wires 11 are formed using the above process as taught in [0024]. Note the steps used to form 11 are what is detailed in the above cited paragraphs.
It would have been within the scope of one of ordinary skill in the art at the time the invention was filed to combine the teachings of Matsueda and Kawasaki to enable the wiring formation step of Matsueda to be performed according to the teachings of Kawasaki because one of ordinary skill in the art at the time the invention was filed would have been motivated to look to alternative suitable methods of performing the disclosed wiring formation step of Matsueda and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
Pertaining to claim 14, Masueda in view of Kawasaki teaches the method for manufacturing a display device according to claim 13, wherein the n wirings Vdd are electrically connected to ones of sources and drains of the n transistors one by one [0049], and wherein the others of the sources and the drains of the n transistors are electrically connected to the n light-emitting elements (OLED) one by one and are overlapped with each other one by one [0049] see Figure 5 Masueda.
Pertaining to claim 15, Masueda in view of Kawasaki teaches the method for manufacturing a display device according to claim 13, wherein the n light-emitting elements each include an EL layer [0059] Masueda.
Allowable Subject Matter
Claims 3, 5-8 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The primary reason for the indication of allowance of the claims is the inclusion of the limitation:
Pertaining to claim 3, the prior art does not teach nor suggest wherein the fifth wiring is configured to supply a first signal to the second subpixel included in the first pixel, wherein the sixth wiring is configured to supply a second signal to the first subpixel included in the second pixel, wherein the seventh wiring is configured to supply a third signal to the second subpixel included in the second pixel, wherein the eighth wiring is configured to supply a fourth signal to the first subpixel included in the third pixel, wherein the first wiring and the second wiring are positioned between the fifth wiring and the sixth wiring in a plan view, and wherein the third wiring and the fourth wiring are positioned between the seventh wiring and the eighth wiring in a plan view
Pertaining to claim 5, the prior art does not teach nor suggest wherein the second subpixel included in the first pixel includes a first transistor, wherein the first subpixel included in the second pixel includes a second transistor, and the second subpixel included in the second pixel includes a third transistor, wherein the first subpixel included in the third pixel includes a fourth transistor, wherein one of a source and a drain of the first transistor is electrically connected to the first wiring, wherein one of a source and a drain of the second transistor is electrically connected to the second wiring, wherein one of a source and a drain of the third transistor is electrically connected to the third wiring, wherein one of a source and a drain of the fourth transistor is electrically connected to the fourth wiring, wherein the first wiring and the second wiring are placed between a channel formation region of the first transistor and a channel formation region of the second transistor in a plan view, and wherein the third wiring and the fourth wiring are placed between a channel formation region of the third transistor and a channel formation region of the fourth transistor in a plan view
Pertaining to claim 16, the prior art does not teach nor suggest wherein light exposure treatment is performed so that in a connection portion of adjacent light exposure regions in the plurality of light exposure regions, a light exposure region where parts of the adjacent light exposure regions are overlapped with each other is formed.
Claims 9-12 are allowed.
The following is an examiner’s statement of reasons for allowance: The primary reason for the allowance of the claims is the inclusion of the limitation:
Pertaining to claim 9, the prior art does not teach nor suggest wherein the first wiring is configured to apply a first potential to the second subpixel included in the first pixel and the first subpixel in the second pixel, wherein the second wiring is configured to apply the first potential to the second subpixel included in the second pixel, wherein the third wiring is configured to apply the first potential to the second subpixel included in the second pixel, wherein the fourth wiring is configured to apply the first potential to the first subpixel included in the third pixel,
wherein the second wiring and the third wiring are adjacent to each other wherein the first wiring has a larger width than each of the second wiring and the third wiring.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J TOBERGTE whose telephone number is (571)272-6458. The examiner can normally be reached M-F 7:30-4:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817