DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-7, 9-15, and 17-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The Examiner thank the Applicant for the detailed remarks and arguments filed on 08/26/2026. Based on the provisions and requests (see Remarks, page 13), this non-final office action is prepared with respect to the claims (primarily independent claims 1, 9, and 17) have been considered moot as mentioned above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4, 7, 9-12, and 15, is/are rejected under 35 U.S.C. 103 as being unpatentable over Jonathan C. Rode et al, (hereinafter RODE), US 20200176582 A1, in view of Akitake Tamura et al, (hereinafter TAMURA), US 20090194233 A1, and Jun Suzuki et al, (hereinafter SUZUKI), US 20080017954 A1, and Ho Cho et al, (hereinafter CHO), US 20040137678 A1.
Regarding Claim 1, RODE teaches an article (Fig. 2, 100, transistor structure), comprising:
a substrate (Fig. 2, 120, [0040]); and
an amorphous oxide film (Fig. 2, 110, gate dielectric) overlaying at least a portion of the substrate (Fig. 2, 120, [0040]), wherein the amorphous oxide film (Fig. 2, 110, gate dielectric) comprises a bulk metal oxide (Fig. 2, 116, high-k dielectric) and a dopant metal oxide (Fig. 2, 114, low-k dielectric) used to convert the bulk metal oxide from a crystalline phase to an amorphous phase ([0012]),
wherein the bulk metal oxide (Fig. 2, 116, high-k dielectric) comprises zirconium oxide (ZrO2), hafnium oxide (HfO2) or a combination thereof (Fig. 2, 116, high-k dielectric, [0044]),
wherein the dopant metal oxide (Fig. 2, 114, low-k dielectric) comprises silicon dioxide (SiO2), aluminum oxide (A1203), nitric oxide (NO) or combinations thereof (Fig. 2, 114, low-k dielectric, [0043]).
wherein the amorphous oxide film (Fig. 2, 110, gate dielectric) comprises has a dielectric constant (k) of about 8 to about 28 ([0044]).
RODE does not explicitly disclose an article, comprising: wherein the amorphous oxide film is conformal and comprises has a porosity of less than about 1%.
TAMURA teaches an article (Fig. 9, 101, matrix) comprising: wherein the amorphous oxide film (Fig. 9, protection film is made of an amorphous oxide, [0222-0228]) is conformal and comprises has a porosity of less than about 1% ([0223]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified RODE to incorporate the teachings of TAMURA, such that, an article, comprising: wherein the amorphous oxide film is conformal and comprises has a porosity of less than about 1%, so that the amorphous protection film is so compact that it has essentially no pores, and henceforth the component’s durability can be enhanced (TAMURA, [0223], [0092]).
Though RODE teaches an article, comprising: a high-k dielectric, 116 has a dielectric constant greater than 3.9, RODE does not explicitly disclose an article, comprising: wherein the amorphous oxide film comprises has a dielectric constant (k) of about 8 to about 28.
SUZUKI teaches disclose an article (Fig. 6, structure of a capacitor), comprising: wherein the amorphous oxide film (Fig. 6, 102/103/104, hafnium oxide films) comprises has a dielectric constant (k) of about 8 to about 28 ([0059-0060]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have RODE as modified by TAMURA to incorporate the teachings of SUZUKI, such that, an article, comprising: wherein the amorphous oxide film comprises has a dielectric constant (k) of about 8 to about 28, so that the cell capacity is in proportion to the dielectric constant of the capacitor insulating film (SUZUKI, [0005]).
RODE as modified by TAMURA and SUZUKI does not explicitly disclose an article, comprising: wherein the amorphous oxide film comprises a first ratio of the bulk metal oxide to the dopant metal oxide within a first thickness of the amorphous oxide film, a second ratio of the bulk metal oxide to the dopant metal oxide within a second thickness of the amorphous oxide film, and a third ratio of the bulk metal oxide to the dopant metal oxide within a third thickness of the amorphous oxide film.
CHO teaches an article (Fig. 4e, capacitor structure, [0034]), comprising: wherein the amorphous oxide film (Fig. 4e, 43, dielectric film) comprises a first ratio of the bulk metal oxide to the dopant metal oxide within a first thickness of the amorphous oxide film (Fig. 4e, 47, film containing mixture of HfO2 and Al2O3 rich in Al (“Al-rich HfO2—Al2O3 film”) have a thickness ranging from 5 to 30 Å, [0042-0045]), a second ratio of the bulk metal oxide to the dopant metal oxide within a second thickness of the amorphous oxide film (Fig. 4e, 49, film containing mixture of HfO2 and Al2O3 rich in Hf (“Hf-rich HfO2—Al2O3 film”) have a thickness ranging from 10 to 100 Å, [0042-0045]), and a third ratio of the bulk metal oxide to the dopant metal oxide within a third thickness of the amorphous oxide film (Fig. 4e, pure Al2O3 film may be used instead of Al-rich HfO2—Al2O3 film, [0042-0045]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have RODE as modified by TAMURA and SUZUKI to incorporate the teachings of CHO, such that, an article, comprising: wherein the amorphous oxide film comprises a first ratio of the bulk metal oxide to the dopant metal oxide within a first thickness of the amorphous oxide film, a second ratio of the bulk metal oxide to the dopant metal oxide within a second thickness of the amorphous oxide film, and a third ratio of the bulk metal oxide to the dopant metal oxide within a third thickness of the amorphous oxide film, so that thereby providing a capacitor having a high capacitance (CHO, [0002]).
The combination of RODE, TAMURA, SUZUKI and CHO does not appear to expressly state an article, wherein the amorphous oxide film comprises a first ratio of the bulk metal oxide to the dopant metal oxide within a first thickness of the amorphous oxide film, a second ratio of the bulk metal oxide to the dopant metal oxide within a second thickness of the amorphous oxide film, and a third ratio of the bulk metal oxide to the dopant metal oxide within a third thickness of the amorphous oxide film; however, where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges (for example ratio and thickness in the present case) involves only routine skill in the art. See MPEP §2144.05 II A; see also In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
In the case at hand, CHO teaches the general conditions of claim 1. Specifically, the field indicated by CHO regarding the dimensions such as the ratio of the bulk metal oxide (e.g. HfO2) to the dopant metal oxide (e.g. Al2O3) and the respective thickness of the dielectric film are the variables describe by the range is “result-effective,” i.e. the prior art discloses/teaches that the range/variable in question is one that, which changed, results in a demonstrable/desired effect. For instance, a ratio of high-k bulk metal oxide to the low-k dopant metal oxide with the respective thickness can be changed to the effect of having a desirable device characteristics such as reducing or increase the dielectric constant to control the electrical conductivity of a channel through which charge carriers (e.g. electrons or holes) flow between the source and drain. Therefore, one having ordinary skill at the time the application at hand would find it obvious to discover the optimum or workable ranges, for example, a first ratio, a second ratio, and a third ratio of bulk metal oxide to dopant metal oxide with respective thickness of a dielectric film stacked structure using only routine skill in the art.
Regarding Claim 2, RODE as modified by TAMURA, SUZUKI and CHO teaches the article of claim 1.
RODE further teaches the article (Fig. 2, 100, transistor structure), wherein the substrate (Fig. 2, 120, [0040]) comprises silicon (Si), germanium (Ge), one or more group III-V semiconductor, InP, InAs, bare glass (SiO2) or combinations thereof ([0038]).
Regarding Claim 3, RODE as modified by TAMURA, SUZUKI and CHO teaches the article of claim 1.
CHO further teaches an article (Fig. 4e, capacitor structure, [0034]), wherein a molar ratio of the bulk metal oxide to the dopant metal oxide is about 1:1 to about 100:1 (a ratio of HfO 2 to Al2O3 cycles in the formation process of the Al-rich HfO2—Al2O3 film 47 is (1 cycle:1 cycle)˜(9 cycle:1 cycle), and a ratio of HfO2 to Al2O3 in the formation process of the Hf-rich HfO2—Al2O3 film 49 is (9 cycle:1 cycle)˜(2 cycle:1 cycle), [0045]).
Regarding Claim 4, RODE as modified by TAMURA, SUZUKI and CHO teaches the article of claim 1.
RODE further teaches the article (Fig. 2, 100, transistor structure), wherein the bulk metal oxide comprises ZrO2 (Fig. 2, 116, high-k dielectric, [0044]) and the oxide comprises SiO2 (Fig. 2, 114, low-k dielectric, [0020]).
Regarding Claim 7, RODE as modified by TAMURA, SUZUKI and CHO teaches the article of claim 1.
CHO further teaches an article (Fig. 4e, capacitor structure, [0034]), wherein the amorphous oxide film (Fig. 4e, 43, dielectric film) has a thickness of at least about 200 Å to about 2,000 Å (Fig. 4e, 47/49, thickness ranging from 5 to 30 Å and 10 to 100 Å, [0043]).
Regarding Claim 9, RODE teaches a transistor structure (Fig. 2, 100, transistor structure), comprising:
a gate (Fig. 2, 118, gate electrode);
a source (Fig. 2, 124, S/D regions);
a drain (Fig. 2, 124, S/D regions); and
an amorphous oxide film (Fig. 2, 110, gate dielectric) overlaying at least a portion of the substrate (Fig. 2, 120, [0040]), wherein the amorphous oxide film (Fig. 2, 110, gate dielectric) comprises a bulk metal oxide (Fig. 2, 116, high-k dielectric) and a dopant metal oxide (Fig. 2, 114, low-k dielectric) used to convert the bulk metal oxide from a crystalline phase to an amorphous phase ([0012]),
wherein the bulk metal oxide (Fig. 2, 116, high-k dielectric) comprises zirconium oxide (ZrO2), hafnium oxide (HfO2) or a combination thereof (Fig. 2, 116, high-k dielectric, [0044]),
wherein the dopant metal oxide (Fig. 2, 114, low-k dielectric) comprises silicon dioxide (SiO2), aluminum oxide (A1203), nitric oxide (NO) or combinations thereof (Fig. 2, 114, low-k dielectric, [0043]).
wherein the amorphous oxide film (Fig. 2, 110, gate dielectric) comprises has a dielectric constant (k) of about 8 to about 28 ([0044]).
RODE does not explicitly disclose an article, comprising: wherein the amorphous oxide film is conformal and comprises has a porosity of less than about 1%.
TAMURA teaches an article (Fig. 9, 101, matrix) comprising: wherein the amorphous oxide film (Fig. 9, protection film is made of an amorphous oxide, [0222-0228]) is conformal and comprises has a porosity of less than about 1% ([0223]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified RODE to incorporate the teachings of TAMURA, such that, an article, comprising: wherein the amorphous oxide film is conformal and comprises has a porosity of less than about 1%, so that the amorphous protection film is so compact that it has essentially no pores, and henceforth the component’s durability can be enhanced (TAMURA, [0223], [0092]).
Though RODE teaches an article, comprising: a high-k dielectric, 116 has a dielectric constant greater than 3.9, RODE does not explicitly disclose an article, comprising: wherein the amorphous oxide film comprises has a dielectric constant (k) of about 8 to about 28.
SUZUKI teaches disclose an article (Fig. 6, structure of a capacitor), comprising: wherein the amorphous oxide film (Fig. 6, 102/103/104, hafnium oxide films) comprises has a dielectric constant (k) of about 8 to about 28 ([0059-0060]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have RODE as modified by TAMURA to incorporate the teachings of SUZUKI, such that, an article, comprising: wherein the amorphous oxide film comprises has a dielectric constant (k) of about 8 to about 28, so that the cell capacity is in proportion to the dielectric constant of the capacitor insulating film (SUZUKI, [0005]).
RODE as modified by TAMURA and SUZUKI does not explicitly disclose an article, comprising: wherein the amorphous oxide film comprises a first ratio of the bulk metal oxide to the dopant metal oxide within a first thickness of the amorphous oxide film, a second ratio of the bulk metal oxide to the dopant metal oxide within a second thickness of the amorphous oxide film, and a third ratio of the bulk metal oxide to the dopant metal oxide within a third thickness of the amorphous oxide film.
CHO teaches an article (Fig. 4e, capacitor structure, [0034]), comprising: wherein the amorphous oxide film (Fig. 4e, 43, dielectric film) comprises a first ratio of the bulk metal oxide to the dopant metal oxide within a first thickness of the amorphous oxide film (Fig. 4e, 47, film containing mixture of HfO2 and Al2O3 rich in Al (“Al-rich HfO2—Al2O3 film”) have a thickness ranging from 5 to 30 Å, [0042-0045]), a second ratio of the bulk metal oxide to the dopant metal oxide within a second thickness of the amorphous oxide film (Fig. 4e, 49, film containing mixture of HfO2 and Al2O3 rich in Hf (“Hf-rich HfO2—Al2O3 film”) have a thickness ranging from 10 to 100 Å, [0042-0045]), and a third ratio of the bulk metal oxide to the dopant metal oxide within a third thickness of the amorphous oxide film (Fig. 4e, pure Al2O3 film may be used instead of Al-rich HfO2—Al2O3 film, [0042-0045]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have RODE as modified by TAMURA and SUZUKI to incorporate the teachings of CHO, such that, an article, comprising: wherein the amorphous oxide film comprises a first ratio of the bulk metal oxide to the dopant metal oxide within a first thickness of the amorphous oxide film, a second ratio of the bulk metal oxide to the dopant metal oxide within a second thickness of the amorphous oxide film, and a third ratio of the bulk metal oxide to the dopant metal oxide within a third thickness of the amorphous oxide film, so that thereby providing a capacitor having a high capacitance (CHO, [0002]).
The combination of RODE, TAMURA, SUZUKI and CHO does not appear to expressly state an article, wherein the amorphous oxide film comprises a first ratio of the bulk metal oxide to the dopant metal oxide within a first thickness of the amorphous oxide film, a second ratio of the bulk metal oxide to the dopant metal oxide within a second thickness of the amorphous oxide film, and a third ratio of the bulk metal oxide to the dopant metal oxide within a third thickness of the amorphous oxide film; however, where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges (for example ratio and thickness in the present case) involves only routine skill in the art. See MPEP §2144.05 II A; see also In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
In the case at hand, CHO teaches the general conditions of claim 1. Specifically, the field indicated by CHO regarding the dimensions such as the ratio of the bulk metal oxide (e.g. HfO2) to the dopant metal oxide (e.g. Al2O3) and the respective thickness of the dielectric film are the variables describe by the range is “result-effective,” i.e. the prior art discloses/teaches that the range/variable in question is one that, which changed, results in a demonstrable/desired effect. For instance, a ratio of high-k bulk metal oxide to the low-k dopant metal oxide with the respective thickness can be changed to the effect of having a desirable device characteristics such as reducing or increase the dielectric constant to control the electrical conductivity of a channel through which charge carriers (e.g. electrons or holes) flow between the source and drain. Therefore, one having ordinary skill at the time the application at hand would find it obvious to discover the optimum or workable ranges, for example, a first ratio, a second ratio, and a third ratio of bulk metal oxide to dopant metal oxide with respective thickness of a dielectric film stacked structure using only routine skill in the art.
Regarding Claim 10, RODE as modified by TAMURA, SUZUKI and CHO teaches the transistor structure of claim 9.
RODE further teaches the transistor structure (Fig. 2, 100, transistor structure), further comprising a substrate (Fig. 2, 120, [0040]) that comprises silicon (Si), germanium (Ge), one or more group III-V semiconductor, InP, InAs, bare glass (SiO2) or combinations thereof ([0038]).
Regarding Claim 11, RODE as modified by TAMURA, SUZUKI and CHO teaches the transistor structure of claim 9.
RODE further teaches the transistor structure (Fig. 2, 100, transistor structure), wherein a molar ratio of the bulk metal oxide to the dopant metal oxide is about 1:1 to about 100:1 (a ratio of HfO 2 to Al2O3 cycles in the formation process of the Al-rich HfO2—Al2O3 film 47 is (1 cycle:1 cycle)˜(9 cycle:1 cycle), and a ratio of HfO2 to Al2O3 in the formation process of the Hf-rich HfO2—Al2O3 film 49 is (9 cycle:1 cycle)˜(2 cycle:1 cycle), [0045]).
Regarding Claim 12, RODE as modified by TAMURA, SUZUKI and CHO teaches the transistor structure of claim 9.
RODE further teaches the transistor structure (Fig. 2, 100, transistor structure), wherein the bulk metal oxide comprises ZrO2 (Fig. 2, 116, high-k dielectric, [0044]) and the oxide comprises SiO2 (Fig. 2, 114, low-k dielectric, [0020]).
Regarding Claim 15, RODE as modified by TAMURA, SUZUKI and CHO teaches the transistor structure of claim 9.
RODE further teaches the transistor structure (Fig. 2, 100, transistor structure), wherein the amorphous oxide film (Fig. 4e, 43, dielectric film) has a thickness of at least about 200 Å to about 2,000 Å (Fig. 4e, 47/49, thickness ranging from 5 to 30 Å and 10 to 100 Å, [0043]).
Claim(s) 5-6, and 13-14, is/are rejected under 35 U.S.C. 103 as being unpatentable over RODE, in view of TAMURA, SUZUKI, and CHO, as applied to Claim(s) 1-4, 7, 9-12, and 15, above, and further and in view of Matthew N. Rocklein et al, (hereinafter ROCKLEIN), US 20120292584 A1.
Regarding Claim 5, RODE as modified by TAMURA, SUZUKI and CHO teaches the article of claim 1.
RODE as modified by TAMURA, SUZUKI and CHO does not explicitly disclose the transistor structure, wherein the amorphous oxide film comprises the dopant metal oxide in an amount of at least about 1 mol% to less than about 50 mol%.
ROCKLEIN teaches the transistor structure (Fig. 1, 100, memory cell array coupled to a select device, e.g. access device such as field effect transistor (FET) or bipolar junction transistor, BJT, [0015]), wherein the amorphous oxide film (Fig. 2, 236/238, dielectric region/barrier dielectric region can be (maybe) formed to be amorphous, [0034], [0036]) comprises the dopant metal oxide (SiO2/Al2O3, AlxOy, [0034], [0036]) in an amount of at least about 1 mol% to less than about 50 mol% (Fig. 2, 236, dielectric region, example of metal oxides (MOx) that can be included in the dielectric region, 236 include a near-stoichiometric, stoichiometric, and sub- stoichiometric metal oxide material; a sub- stoichiometric oxide can be an oxide that has an oxygen percentage below a stoichiometric ratio for the oxide, the dielectric region, 236 can include other metal oxides such as a zirconium silicon oxide (ZrxSiyOz), and/or a hafnium silicon oxide (HfxSiyOz), (AlxHfyOz) [0033-0034], [0045]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have RODE as modified by TAMURA, SUZUKI and CHO to incorporate the teachings of ROCKLEIN, such that, the transistor structure, wherein the amorphous oxide film comprises the dopant metal oxide in an amount of at least about 1 mol% to less than about 50 mol%, so that the discrete barrier dielectric materials within the bulk dielectric materials can result in discrete regions of stoichiometric oxides and sub-oxides being created under programming to establish a two-state resistive memory cell that can have a low resistance state and a high resistance state (ROCKLEIN, [0022], [0006]).
Regarding Claim 6, RODE as modified by TAMURA, SUZUKI and CHO teaches the article of claim 1.
RODE as modified by TAMURA, SUZUKI and CHO does not explicitly disclose the transistor structure, wherein the bulk metal oxide comprises ZrO2, wherein the dopant metal oxide comprises SiO2, and wherein the SiO2 is present in an amount of at least about 9 mol% to less than about 50 mol%.
ROCKLEIN teaches the transistor structure (Fig. 1, 100, memory cell array coupled to a select device, e.g. access device such as field effect transistor (FET) or bipolar junction transistor, BJT, [0015]), wherein the bulk metal oxide comprises ZrO2 ([0034]), wherein the dopant metal oxide comprises SiO2 ([0034], [0036]), and wherein the SiO2 is present in an amount of at least about 9 mol% to less than about 50 mol% (Fig. 2, 236, dielectric region, example of metal oxides (MOx) that can be included in the dielectric region, 236 include a near-stoichiometric, stoichiometric, and sub- stoichiometric metal oxide material; a sub- stoichiometric oxide can be an oxide that has an oxygen percentage below a stoichiometric ratio for the oxide, the dielectric region, 236 can include other metal oxides such as a zirconium silicon oxide (ZrxSiyOz), [0033-0036]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have RODE as modified by TAMURA, SUZUKI and CHO to incorporate the teachings of ROCKLEIN, such that, the transistor structure, wherein the bulk metal oxide comprises ZrO2, wherein the dopant metal oxide comprises SiO2, and wherein the SiO2 is present in an amount of at least about 9 mol% to less than about 50 mol%, so that the discrete barrier dielectric materials within the bulk dielectric materials can result in discrete regions of stoichiometric oxides and sub-oxides being created under programming to establish a two-state resistive memory cell that can have a low resistance state and a high resistance state (ROCKLEIN, [0022], [0006]).
Regarding Claim 13, RODE as modified by TAMURA, SUZUKI and CHO teaches the transistor structure of claim 9.
RODE as modified by TAMURA, SUZUKI and CHO does not explicitly disclose the transistor structure, wherein the amorphous oxide film comprises the dopant metal oxide in an amount of at least about 1 mol% to less than about 50 mol%.
ROCKLEIN teaches the transistor structure (Fig. 1, 100, memory cell array coupled to a select device, e.g. access device such as field effect transistor (FET) or bipolar junction transistor, BJT, [0015]), wherein the amorphous oxide film (Fig. 2, 236/238, dielectric region/barrier dielectric region can be (maybe) formed to be amorphous, [0034], [0036]) comprises the dopant metal oxide (SiO2/Al2O3, AlxOy, [0034], [0036]) in an amount of at least about 1 mol% to less than about 50 mol% (Fig. 2, 236, dielectric region, example of metal oxides (MOx) that can be included in the dielectric region, 236 include a near-stoichiometric, stoichiometric, and sub- stoichiometric metal oxide material; a sub- stoichiometric oxide can be an oxide that has an oxygen percentage below a stoichiometric ratio for the oxide, the dielectric region, 236 can include other metal oxides such as a zirconium silicon oxide (ZrxSiyOz), and/or a hafnium silicon oxide (HfxSiyOz), (AlxHfyOz) [0033-0034], [0045]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have RODE as modified by TAMURA, SUZUKI and CHO to incorporate the teachings of ROCKLEIN, such that, the transistor structure, wherein the amorphous oxide film comprises the dopant metal oxide in an amount of at least about 1 mol% to less than about 50 mol%, so that the discrete barrier dielectric materials within the bulk dielectric materials can result in discrete regions of stoichiometric oxides and sub-oxides being created under programming to establish a two-state resistive memory cell that can have a low resistance state and a high resistance state (ROCKLEIN, [0022], [0006]).
Regarding Claim 14, RODE as modified by TAMURA, SUZUKI and CHO teaches the transistor structure of claim 9.
RODE as modified by TAMURA, SUZUKI and CHO does not explicitly disclose the transistor structure, wherein the bulk metal oxide comprises ZrO2, wherein the dopant metal oxide comprises SiO2, and wherein the SiO2 is present in an amount of at least about 9 mol% to less than about 50 mol%.
ROCKLEIN teaches the transistor structure (Fig. 1, 100, memory cell array coupled to a select device, e.g. access device such as field effect transistor (FET) or bipolar junction transistor, BJT, [0015]), wherein the bulk metal oxide comprises ZrO2 ([0034]), wherein the dopant metal oxide comprises SiO2 ([0034], [0036]), and wherein the SiO2 is present in an amount of at least about 9 mol% to less than about 50 mol% (Fig. 2, 236, dielectric region, example of metal oxides (MOx) that can be included in the dielectric region, 236 include a near-stoichiometric, stoichiometric, and sub- stoichiometric metal oxide material; a sub- stoichiometric oxide can be an oxide that has an oxygen percentage below a stoichiometric ratio for the oxide, the dielectric region, 236 can include other metal oxides such as a zirconium silicon oxide (ZrxSiyOz), [0033-0036]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have RODE as modified by TAMURA, SUZUKI and CHO to incorporate the teachings of ROCKLEIN, such that, the transistor structure, wherein the bulk metal oxide comprises ZrO2, wherein the dopant metal oxide comprises SiO2, and wherein the SiO2 is present in an amount of at least about 9 mol% to less than about 50 mol%, so that the discrete barrier dielectric materials within the bulk dielectric materials can result in discrete regions of stoichiometric oxides and sub-oxides being created under programming to establish a two-state resistive memory cell that can have a low resistance state and a high resistance state (ROCKLEIN, [0022], [0006]).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over RODE, in view of SUZUKI, and CHO, as applied to Claim(s) 1-4, 7, 9-12, and 15, above.
Regarding Claim 17, RODE teaches a method of forming (Fig. 6, 200, process flow in a method) an amorphous oxide film (Fig. 2, 110, gate dielectric), comprising:
performing a plasma-enhanced atomic layer deposition (ALD) process ([0036]) to form an amorphous oxide film (Fig. 2, 110, gate dielectric) comprising a bulk metal oxide (Fig. 2, 116, high-k dielectric) and a dopant metal oxide (Fig. 2, 114, low-k dielectric), wherein the bulk metal oxide (Fig. 2, 116, high-k dielectric) comprises ZrO2, HfO2 or a combination thereof (Fig. 2, 116, high-k dielectric, [0044]), wherein the dopant metal oxide (Fig. 2, 114, low-k dielectric) comprises SiO2, A1203, NO, or combinations thereof (Fig. 2, 114, low-k dielectric, [0043]), wherein the amorphous oxide film (Fig. 2, 110, gate dielectric) has a dielectric constant (k) of about 8 to about 28 ([0044]), and wherein performing the plasma-enhanced ALD process ([0012]) comprises:
performing one or more ALD deposition super-cycles (Fig. 6, repeat steps 220 and 225 for N times, [0045]), wherein performing each of the one or more ALD deposition super-cycles comprises (Fig. 6, repeat steps 220 and 225 for N times, [0045]):
performing one or more first ALD deposition cycles (Fig. 6, repeat steps 220 and 225 for N times, [0045]) to deposit a bulk metal oxide layer (Fig. 6, 225, deposit a layer of high-k dielectric on the layer of low-k dielectric) of the bulk metal oxide (Fig. 2, 116, high-k dielectric); and
performing one or more second ALD deposition cycles (Fig. 6, repeat steps 220 and 225 for N times, [0045]) to deposit a dopant metal oxide layer (Fig. 6, 220, deposit a thin layer of low-k dielectric) to form the amorphous oxide layer ([0012]) of the dopant metal oxide (Fig. 2, 114, low-k dielectric).
Though RODE teaches a method of forming an amorphous oxide film, comprising: a high-k dielectric, 116 has a dielectric constant greater than 3.9, RODE does not explicitly disclose a method of forming an amorphous oxide film, comprising: wherein the amorphous oxide film comprises has a dielectric constant (k) of about 8 to about 28.
SUZUKI teaches a method of forming ([0025]) an amorphous oxide film, comprising: wherein the amorphous oxide film (Fig. 6, 102/103/104, hafnium oxide films) has a dielectric constant (k) of about 8 to about 28 ([0059-0060]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified RODE to incorporate the teachings of SUZUKI, such that, an article, comprising: wherein the amorphous oxide film comprises has a dielectric constant (k) of about 8 to about 28, so that the cell capacity is in proportion to the dielectric constant of the capacitor insulating film (SUZUKI, [0005]).
RODE as modified by SUZUKI does not explicitly disclose a method of forming an amorphous oxide film, comprising: wherein the amorphous oxide film comprises a first ratio of the bulk metal oxide to the dopant metal oxide within a first thickness of the amorphous oxide film, a second ratio of the bulk metal oxide to the dopant metal oxide within a second thickness of the amorphous oxide film, and a third ratio of the bulk metal oxide to the dopant metal oxide within a third thickness of the amorphous oxide film.
CHO teaches a method of forming ([0023]) an amorphous oxide film (Fig. 4e, 43, dielectric film), comprising: wherein the amorphous oxide film (Fig. 4e, 43, dielectric film) comprises a first ratio of the bulk metal oxide to the dopant metal oxide within a first thickness of the amorphous oxide film (Fig. 4e, 47, film containing mixture of HfO2 and Al2O3 rich in Al (“Al-rich HfO2—Al2O3 film”) have a thickness ranging from 5 to 30 Å, [0042-0045]), a second ratio of the bulk metal oxide to the dopant metal oxide within a second thickness of the amorphous oxide film (Fig. 4e, 49, film containing mixture of HfO2 and Al2O3 rich in Hf (“Hf-rich HfO2—Al2O3 film”) have a thickness ranging from 10 to 100 Å, [0042-0045]), and a third ratio of the bulk metal oxide to the dopant metal oxide within a third thickness of the amorphous oxide film (Fig. 4e, pure Al2O3 film may be used instead of Al-rich HfO2—Al2O3 film, [0042-0045]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have RODE as modified by TAMURA and SUZUKI to incorporate the teachings of CHO, such that, a method of forming an amorphous oxide film, comprising: wherein the amorphous oxide film comprises a first ratio of the bulk metal oxide to the dopant metal oxide within a first thickness of the amorphous oxide film, a second ratio of the bulk metal oxide to the dopant metal oxide within a second thickness of the amorphous oxide film, and a third ratio of the bulk metal oxide to the dopant metal oxide within a third thickness of the amorphous oxide film, so that thereby providing a capacitor having a high capacitance (CHO, [0002]).
The combination of RODE, SUZUKI and CHO does not appear to expressly state an article, wherein the amorphous oxide film comprises a first ratio of the bulk metal oxide to the dopant metal oxide within a first thickness of the amorphous oxide film, a second ratio of the bulk metal oxide to the dopant metal oxide within a second thickness of the amorphous oxide film, and a third ratio of the bulk metal oxide to the dopant metal oxide within a third thickness of the amorphous oxide film; however, where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges (for example ratio and thickness in the present case) involves only routine skill in the art. See MPEP §2144.05 II A; see also In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
In the case at hand, CHO teaches the general conditions of claim 1. Specifically, the field indicated by CHO regarding the dimensions such as the ratio of the bulk metal oxide (e.g. HfO2) to the dopant metal oxide (e.g. Al2O3) and the respective thickness of the dielectric film are the variables describe by the range is “result-effective,” i.e. the prior art discloses/teaches that the range/variable in question is one that, which changed, results in a demonstrable/desired effect. For instance, a ratio of high-k bulk metal oxide to the low-k dopant metal oxide with the respective thickness can be changed to the effect of having a desirable device characteristics such as reducing or increase the dielectric constant to control the electrical conductivity of a channel through which charge carriers (e.g. electrons or holes) flow between the source and drain. Therefore, one having ordinary skill at the time the application at hand would find it obvious to discover the optimum or workable ranges, for example, a first ratio, a second ratio, and a third ratio of bulk metal oxide to dopant metal oxide with respective thickness of a dielectric film stacked structure using only routine skill in the art.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over RODE, in view of SUZUKI, and CHO, as applied to Claim(s) 17, above, further in view of Jung Wook Lim et al, (hereinafter LIM), US 20050142712 A1, Kie Ahn et al, (hereinafter AHN), US 20060246741 A1, and Vijay Narayanan et al, (hereinafter NARAYANAN), US 20180040710 A1.
Regarding Claim 18, RODE as modified by SUZUKI, and CHO, teaches the method of claim 17.
RODE as modified by SUZUKI and CHO does not explicitly disclose the method, wherein: performing each of the one or more first ALD deposition cycles comprises: contacting a surface with at least one of a Zr precursor or an Hf precursor in a first half reaction; and contacting the surface with a first oxygen reactant in a second half reaction to form the bulk metal oxide layer; and performing each of the one or more second ALD deposition cycles comprises: contacting the surface with at least one of a Si precursor, an Al precursor or an N precursor in a third half reaction; and contacting the surface with the first oxygen reactant or a second oxygen reactant in a fourth half reaction to form the dopant metal oxide layer.
LIM teaches the method (Figs. 1/4, flow chart of forming a gate dielectric layer, thin film transistor using gate dielectric layer; NMOS for a thin film transistor (TFT), [0016-0017], [0024], [0027], [0039]), wherein:
performing each of the one or more first ALD deposition cycles (Figs. 1-2, 3, ALD oxide layer, [0031-0035], [0039]); (Fig. 1, at operation S20, a plasma oxide layer is formed using oxygen plasma; at operation S30, an ALD oxide (SiO2) layer or a high dielectric layer is deposited by a plasma-enhanced ALD or PEALD process; [0031]) comprises:
contacting a surface with at least one of a Zr precursor or an Hf precursor in a first half reaction (Fig. 1, [0014], [0019]); and
contacting the surface with a first oxygen reactant in a second half reaction (Fig. 1, oxygen plasma, [0031-0040]) to form the bulk metal oxide layer (Figs. 1-2, 4, high dielectric layer, [0031-0035], [0039]); and
performing each of the one or more second ALD deposition cycles (Figs. 1-2, 3, ALD oxide layer, [0031-0035], [0039]); (Fig. 1, at operation S20, a plasma oxide layer is formed using oxygen plasma; at operation S30, an ALD oxide (SiO2) layer or a high dielectric layer is deposited by a plasma-enhanced ALD or PEALD process; [0031]) comprises:
contacting the surface with at least one of a Si precursor, an Al precursor or an N precursor in a third half reaction (Fig. 1, [0019], [0031]); and
contacting the surface with the first oxygen reactant or a second oxygen reactant in a fourth half reaction (Fig. 1, oxygen plasma, [0031-0040]) to form the dopant metal oxide layer (Figs. 1-2, 3, ALD oxide layer, [0031-0035], [0039]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have RODE as modified by SUZUKI and CHO, to incorporate the teachings of LIM, such that the method, wherein: performing each of the one or more first ALD deposition cycles comprises: contacting a surface with at least one of a Zr precursor or an Hf precursor in a first half reaction; and contacting the surface with a first oxygen reactant in a second half reaction to form the bulk metal oxide layer; and performing each of the one or more second ALD deposition cycles comprises: contacting the surface with at least one of a Si precursor, an Al precursor or an N precursor in a third half reaction; and contacting the surface with the first oxygen reactant or a second oxygen reactant in a fourth half reaction to form the dopant metal oxide layer. The above-mentioned steps are indeed specific to the method for forming a gate dielectric layer, in which the gate dielectric layer is formed by finely forming a plasma and depositing an atomic layer deposition (ALD) oxide layer, thereby enhancing interfacial characteristics and decreasing current leakage (LIM, [0002]).
Though LIM teaches the ALD deposition cycles using silicate layer formed by combination of SiO2 and at least one of HfO2, ZrO2 etc., [0019], RODE as modified by SUZUKI, CHO, and LIM does not explicitly disclose the method wherein performing each of the one or more first ALD deposition cycles comprises: contacting a surface with at least one of a Zr precursor or an Hf precursor in a first half reaction; and contacting the surface with a first oxygen reactant in a second half reaction.
AHN teaches the method (Fig. 2A, atomic layer deposition system for processing a layer, [0015]) wherein:
performing each of the one or more first ALD deposition cycles (Fig. 4, flow diagram of a method to process a nanolaminate of HfO2/ZrO2 by atomic layer deposition, step 430, hafnium cycles performed, [0076]; step 455, zirconium cycles, [0084]; [0017-0018]) comprises:
contacting a surface with at least one of a Zr precursor or an Hf precursor in a first half reaction (Fig. 4, 410, pulse precursor containing hafnium, HfO2 using HfI4 precursor; 435, pulse precursor containing zirconium, ZrI4 or ZrCl4, [0042], [0072], [0077]); and
contacting the surface with a first oxygen reactant in a second half reaction (Fig. 4, 420, pulse first oxygen containing precursor, vapor solution H2O-H2O2 can be used as the oxygen containing precursor, [0073]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have RODE as modified by SUZUKI, CHO, and LIM to incorporate the teachings of AHN, such that the method wherein performing each of the one or more first ALD deposition cycles comprises: contacting a surface with at least one of a Zr precursor or an Hf precursor in a first half reaction; and contacting the surface with a first oxygen reactant in a second half reaction, so that to produce HfO2/ZrO2 nanolaminates processed in relatively low temperatures can provide amorphous dielectric films having relatively low leakage current for use as dielectric layers in electronic devices and systems (AHN, Fig. 4, [0128]).
RODE as modified by SUZUKI, CHO, LIM, and AHN does not explicitly disclose the method wherein each of the one or more second ALD deposition cycles comprises: contacting the surface with at least one of a Si precursor, an Al precursor or an N precursor in a third half reaction; and contacting the surface with the first oxygen reactant or a second oxygen reactant in a fourth half reaction.
NARAYANAN teaches the method (Fig. 1, method for forming a semiconductor device, [0007]) wherein:
performing each of the one or more second ALD deposition cycles (Figs. 1 and 8, flow charts illustrating the first and last method of a gate forming with metal oxide or binary metal oxide layers using atomic layer deposition chamber (ALD), [0034]) comprises:
contacting the surface with at least one of a Si precursor, an Al precursor or an N precursor in a third half reaction (Fig. 1, step 10, aluminum containing gas precursor and/or nitrogen plasma and/or a hydrogen plasma, [0038], [0061]); and
contacting the surface with the first oxygen reactant or a second oxygen reactant in a fourth half reaction (Fig. 1, oxygen containing atmosphere exposure, [0028], [0034]). [Note: It should also be noted that substituting (oxygen containing plasma) for (nitrogen containing plasma) in formation of binary metal oxide interlayer, TiAlON, in the prior-art, is a simple substitution of one known element for another to obtain predictable results (See MPEP2143)"].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have RODE as modified by SUZUKI, CHO, LIM, and AHN to incorporate the teachings of NARAYANAN, such that the method wherein: performing each of the one or more second ALD deposition cycles comprises: contacting the surface with at least one of a Si precursor, an Al precursor or an N precursor in a third half reaction; and contacting the surface with the first oxygen reactant or a second oxygen reactant in a fourth half reaction, to produce binary metal oxide, (TiAlON) layer having appropriate thickness with high quality, further deposited on high k dielectric HfO2 layer, and thus can obtain a capacitance equivalent thickness (CET) as low as 10 Å, with low leakage small hysteresis and good interface quality (NARAYANAN, [0027], [0063]).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over RODE as modified by SUZUKI, CHO, LIM, AHN, and NARAYANAN as applied to Claim(s) 18 above, and further in view of Hideaki Machida et al, (hereinafter MACHIDA), JP 2003124460 A.
Regarding Claim 19, RODE as modified by SUZUKI, CHO, LIM, AHN, NARAYANAN, teaches the method of claim 18.
RODE as modified by SUZUKI, CHO, LIM, AHN, NARAYANAN, does not explicitly disclose the method, wherein: the Zr precursor is used for the first half reaction, wherein the Si precursor is used for the second half reaction, and wherein the first oxygen reactant and the second oxygen reactant are independently selected from a group consisting of water (H2O), ozone (O3), oxygen (O2) hydrogen peroxide (H2O2) and oxygen radical (O-).
MACHIDA teaches the method (Fig. 1, method for forming a gate oxide film, [0001]), wherein: the Zr precursor is used for the first half reaction (Zr alkoxide compounds, Zr β-diketonate compounds, Zr alkylamide compounds, [0025], [0040]), wherein the Si precursor is used for the second half reaction (silicon-based compound, [0014], [0045]), and wherein the first oxygen reactant and the second oxygen reactant are independently selected from a group consisting of water (H2O), ozone (O3), oxygen (O2) hydrogen peroxide (H2O2) and oxygen radical (O-) (oxidizing atmosphere selected from the group consisting of oxygen, nitrous oxide, ozone, water and hydrogen peroxide, [0017]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have RODE as modified by SUZUKI, CHO, LIM, AHN, NARAYANAN, to incorporate the teachings of MACHIDA, such that the method, wherein: the Zr precursor is used for the first half reaction, wherein the Si precursor is used for the second half reaction, and wherein the first oxygen reactant and the second oxygen reactant are independently selected from a group consisting of water (H2O), ozone (O3), oxygen (O2) hydrogen peroxide (H2O2) and oxygen radical (O-), so that to produce the gate oxide film interface with the silicon layer must be stable and also the dielectric constant must be high with thickness as thin as 10 nm or less for miniaturization in order to improve the signal processing speed, in particular, the distance between the source and rain becoming shorter (MACHIDA, [0001-0006]).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over RODE as modified by SUZUKI, CHO, LIM, AHN, and NARAYANAN as applied to Claim(s) 18 above, and further in view of Yuia Zhai et al, (hereinafter ZHAI), US 20190206691 A1.
Regarding Claim 20, RODE as modified by SUZUKI, CHO, LIM, AHN, NARAYANAN, teaches the method of claim 18.
LIM further teaches the method (Figs. 1/4, flow chart of forming a gate dielectric layer, thin film transistor using gate dielectric layer; NMOS for a thin film transistor (TFT), [0016-0017], [0024], [0027], [0039]) of claim 18, wherein:
performing the plasma-enhanced ALD (Figs. 1-2, 3, ALD oxide layer, [0031-0035], [0039]); (Fig. 1, at operation S20, a plasma oxide layer is formed using oxygen plasma; at operation S30, an ALD oxide (SiO2) layer or a high dielectric layer is deposited by a plasma-enhanced ALD or PEALD process; [0031]) further comprises:
performing one or more third deposition cycles to deposit an adhesion metal oxide layer on the surface before performing the one or more ALD deposition super-cycles (Figs. 1-2, 3, ALD oxide layer, [0031-0035], [0039]); (Fig. 1, at operation S20, a plasma oxide layer is formed using oxygen plasma; at operation S30, an ALD oxide (SiO2) layer or a high dielectric layer is deposited by a plasma-enhanced ALD or PEALD process; [0031]), wherein the adhesion metal oxide layer comprises one or more of SiO2, A12O3, HfO2, SiCON, SiC or combinations thereof (Fig. 1, [0019], [0031]).
Though LIM teaches the deposition cycle via ALD process, RODE as modified by SUZUKI, CHO, LIM, AHN, NARAYANAN, does not explicitly disclose the method wherein: performing one or more third deposition cycles to deposit an adhesion metal oxide layer on the surface before performing the one or more ALD deposition super-cycles, wherein the adhesion metal oxide layer comprises one or more of SiO2, A12O3, HfO2, SiCON, SiC or combinations thereof.
ZHAI teaches the method (Fig. 1, cross-sectional view of a processing chamber that may be used to deposit a gate insulating layer, [0009]) wherein: performing one or more third deposition cycles to deposit an adhesion metal oxide layer (Fig. 2, 210A, the interface layer, [0025]) on the surface (Fig. 2, 204, channel layer) before performing the one or more ALD deposition super-cycles (Fig. 1, PECVD, [0015]) wherein the adhesion metal oxide layer (Fig. 2, the interface layer, 210A has a good interface between both the channel layer, 204 and the high-k dielectric layer, 210B thereby improving adhesion, [0027]) comprises one or more of SiO2, A12O3, HfO2, SiCON, SiC or combinations thereof (Fig. 2, SiO2, Al2O3, TiO2, [0025]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have RODE as modified by SUZUKI, CHO, LIM, AHN, NARAYANAN, to incorporate the teachings of ZHAI, such that the method wherein: performing one or more third deposition cycles to deposit an adhesion metal oxide layer on the surface before performing the one or more ALD deposition super-cycles, wherein the adhesion metal oxide layer comprises one or more of SiO2, A12O3, HfO2, SiCON, SiC or combinations thereof, so that the silicon containing interface layer improves adhesion and interaction between the active channel layer and the metal gate with the high-k dielectric value of the gate layer enables for a faster driving current that improves brightness and performance of the display device (ZHAI, [0032]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20150170837 A1 – Figure 1
STATEMENT OF RELEVANCE – A simplified cross-sectional view of decoupling capacitor stacks of a first hafnium oxide layer, 104, an aluminum oxide layer, 106 and a second hafnium oxide layer with predetermined thicknesses.
US 20040091612 A1 – Figure 4
STATEMENT OF RELEVANCE – A cross-section of a substrate carrying a stack composed layers of amorphous hafnium oxide, and the layers of silicon oxide.
NPL Reference: Atomic Layer Deposition and Properties of HfO2-Al2O3 Nanolaminates, Kaupo Kukli, Marianna Kemell, Helena Castan, Salvado Duenas, Helina Seemen, Mihkel Rahn, Joseph Link, Raivo Stern, Mikko Ritala, and Markku Leskela, ECS Journal of Solid State Science and Technology, 7, 9, P501-P508, 2018; DOI: 10.1149/2.0261809jss.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/ALI NARAGHI/Primary Examiner, Art Unit 2817
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