DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 10/13/2023 are in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 5, 8, and 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim(s) 5, 8, and 13 recites the limitation “the first metal”, “the second metal” in “2nd line of claim 5; 3rd to 5th line of claim 8; and 2nd line of claim 13. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 4, 7, 9-10, 12, 15, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung Wook Lim et al, (hereinafter LIM), US 20050142712 A1, in view of Jung-Yu Hsieh et al, (hereinafter HSIEH), US 20030025148 A1.
Regarding Claim 1, LIM teaches an article (Fig. 4, thin film transistor using gate dielectric layer; NMOS for a thin film transistor (TFT), [0016-0017], [0027], [0039]), comprising:
a substrate (Fig. 1, wafer in S10, Fig. 2, 1, silicon layer is formed on a general substrate, [0033]); and
an amorphous oxide film overlaying at least a portion of the substrate (Fig. 1, S20, forming plasma oxide layer, a silicon, 1, for the gate dielectric layer is made of poly silicon or amorphous silicon, the oxygen plasma is generated on the silicon layer, 1, so that the plasma oxide layer, 2 is grown as shown in Fig. 2, [0033]), wherein the amorphous oxide film comprises a first oxide (Figs. 1-2, 4, high dielectric layer, [0031-0035], [0039]) and a second oxide (Figs. 1-2, 3, ALD oxide layer, [0031-0035], [0039]); (Fig. 1, at operation S20, a plasma oxide layer is formed using oxygen plasma; at operation S30, an ALD oxide (SiO2) layer or a high dielectric layer is deposited by a plasma-enhanced ALD or PEALD process; [0031]),
wherein the first oxide (Figs. 1-2, 4, high dielectric layer, [0031-0035], [0039]) comprises zirconium oxide (ZrO2), hafnium oxide (HfO2) or a combination thereof (Fig. 2, 2, plasma oxide layer and 3, ALD oxide layer; to get a higher dielectric constant, the high dielectric layer can be formed on the plasma oxide layer, her the high dielectric layer includes zirconium oxide (ZrO2), hafnium oxide (HfO2) etc., [0019], [0034]),
wherein the second oxide (Figs. 1-2, 3, ALD oxide layer, [0031-0035], [0039]) comprises silicon dioxide (SiO2), aluminum oxide (A12O3), nitric oxide (NO) or combinations thereof (Fig. 2, 2, plasma oxide layer and 3, ALD oxide layer are deposited by in-situ for forming a high dielectric layer includes the high dielectric layer, aluminum oxide (Al2O3) or a silicate layer formed by combination of silicon dioxide (SiO2) and at least one of Al2O3 etc. [0019], [0034]),
wherein the amorphous oxide film is conformal (Fig. 2, 2, plasma oxide layer and 3, ALD oxide layers having uniformity with regard to the relatively large wafer is good, [0013]) and comprises a porosity of less than about 1% (the ALD oxide layer, 3 is deposited with a thickness of 50 nm~150 nm at a low temperature by the PEALD process or the ALD process for good thin film density, [0034]; Note: the porosity in % with film thickness for related films are tabulated in NPL1), and
Though LIM teaches the gate dielectric thin film comprises a high K dielectric oxides, LIM does not explicitly disclose an article comprising: wherein the amorphous oxide film comprises a dielectric constant (k) of about 8 to about 28.
HSIEH teaches an article (Fig. 1, flash memory, [0017]) comprising: wherein the amorphous oxide film comprises (Fig. 1, 104, dielectric layer, [0020]), a dielectric constant (k) of about 8 to about 28 (Table 1, dielectric constants of the high-dielectric constant materials, [0029-0030]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified LIM to incorporate the teachings of HSIEH, such that an article, comprising: wherein the amorphous oxide film comprises a dielectric constant (k) of about 8 to about 28, so that the amount of variation of the threshold voltage is greatly reduced and data retention of the flash memory is enhanced (HSIEH, [0014]).
Regarding Claim 2, LIM as modified by HSIEH teaches the article (Fig. 4, thin film transistor using gate dielectric layer; NMOS for a thin film transistor (TFT), [0016-0017], [0027], [0039]), of claim 1, wherein the substrate (Fig. 1, wafer in S10, Fig. 2, 1, silicon layer is formed on a general substrate, [0033]) comprises silicon (Si), germanium (Ge), one or more group III-V semiconductor, InP, InAs, bare glass (SiO2) or combinations thereof (Fig. 4, single crystal silicon substrate, [0027]).
Regarding Claim 4, LIM as modified by HSIEH teaches the article (Fig. 4, thin film transistor using gate dielectric layer; NMOS for a thin film transistor (TFT), [0016-0017], [0027], [0039]), of claim 1, wherein the first oxide comprises ZrO2 (Fig. 2, 2, plasma oxide layer and 3, ALD oxide layer; to get a higher dielectric constant, the high dielectric layer can be formed on the plasma oxide layer, her the high dielectric layer includes zirconium oxide (ZrO2), hafnium oxide (HfO2) etc., [0019], [0034] and the second oxide comprises SiO2 (Fig. 2, 2, plasma oxide layer and 3, ALD oxide layer are deposited by in-situ for forming a high dielectric layer includes the high dielectric layer, aluminum oxide (Al2O3) or a silicate layer formed by combination of silicon dioxide (SiO2) and at least one of Al2O3 etc. [0019], [0034]).
Regarding Claim 7, LIM as modified by HSIEH teaches the article (Fig. 4, thin film transistor using gate dielectric layer; NMOS for a thin film transistor (TFT), [0016-0017], [0027], [0039]) of claim 1, wherein the amorphous oxide film (Fig. 1, S20, forming plasma oxide layer, a silicon, 1, for the gate dielectric layer is made of poly silicon or amorphous silicon, the oxygen plasma is generated on the silicon layer, 1, so that the plasma oxide layer, 2 is grown as shown in Fig. 2, [0033]) comprises a thickness of at least about 200 A to about 2,000 A (In the case that the Al2O3 gate dielectric layer was formed on the single crystal silicon substrate, the Al2O3 gate dielectric layer had a thickness of 100 nm. Oppositely, in the case that the plasma oxide layer was added between the Al2O3 gate dielectric layer and the single crystal silicon substrate, the plasma oxide layer had a thickness of 20 nm and the PEALD Al2O3 gate dielectric layer had a thickness of 80 nm; (100 nm + 20 nm + 80 nm = 200 nm = 2000Å; ranging from 20 nm to 200 nm meaning 200 Å to 2000 Å; [0044]; In another embodiment, the natural oxide layer having a thickness of 5 nm; ALD oxide layer with a thickness of 15 nm; Al2O3 having a thickness of 50 nm; and the whole layer thickness is about 70 nm which is equivalent to 700 Å, [0043], therefore the thickness range from 50 Å to 700 Å).
Regarding Claim 9, LIM teaches a transistor structure (Fig. 4, thin film transistor using gate dielectric layer; NMOS for a thin film transistor (TFT), [0016-0017], [0027], [0039]), comprising:
a gate (Fig. 4, gate dielectric layer, [0044]);
a source (Fig. 4, source/drain, [0045]);
a drain (Fig. 4, source/drain, [0045]); and
an amorphous oxide film (Fig. 1, S20, forming plasma oxide layer, a silicon, 1, for the gate dielectric layer is made of poly silicon or amorphous silicon, the oxygen plasma is generated on the silicon layer, 1, so that the plasma oxide layer, 2 is grown as shown in Fig. 2, [0033]) separating the gate (Fig. 4, gate dielectric layer, [0044])from at least one of the source or the drain (Fig. 4, source/drain, [0045]),
wherein the amorphous oxide film (Fig. 1, S20, forming plasma oxide layer, a silicon, 1, for the gate dielectric layer is made of poly silicon or amorphous silicon, the oxygen plasma is generated on the silicon layer, 1, so that the plasma oxide layer, 2 is grown as shown in Fig. 2, [0033]) comprises a first oxide (Figs. 1-2, 4, high dielectric layer, [0031-0035], [0039]) and a second oxide (Figs. 1-2, 3, ALD oxide layer, [0031-0035], [0039]), wherein the first oxide comprises zirconium oxide (ZrO2), hafnium oxide (HfO2) or a combination thereof (Fig. 2, 2, plasma oxide layer and 3, ALD oxide layer; to get a higher dielectric constant, the high dielectric layer can be formed on the plasma oxide layer, her the high dielectric layer includes zirconium oxide (ZrO2), hafnium oxide (HfO2) etc., [0019], [0034]),
wherein the second oxide comprises silicon dioxide (SiO2), aluminum oxide (A1203), nitric oxide (NO) or combinations thereof (Fig. 2, 2, plasma oxide layer and 3, ALD oxide layer are deposited by in-situ for forming a high dielectric layer includes the high dielectric layer, aluminum oxide (Al2O3) or a silicate layer formed by combination of silicon dioxide (SiO2) and at least one of Al2O3 etc. [0019], [0034]),
wherein the amorphous oxide film (Fig. 1, S20, forming plasma oxide layer, a silicon, 1, for the gate dielectric layer is made of poly silicon or amorphous silicon, the oxygen plasma is generated on the silicon layer, 1, so that the plasma oxide layer, 2 is grown as shown in Fig. 2, [0033]) comprises a porosity of less than about 1% (the ALD oxide layer, 3 is deposited with a thickness of 50 nm~150 nm at a low temperature by the PEALD process or the ALD process for good thin film density, [0034]; Note: the porosity in % with film thickness for related films are tabulated in NPL2), and
Though LIM teaches the gate dielectric thin film comprises a high K dielectric oxides, LIM does not explicitly disclose an article comprising: wherein the amorphous oxide film comprises a dielectric constant (k) of about 8 to about 28.
HSIEH teaches an article (Fig. 1, flash memory, [0017]) comprising: wherein the amorphous oxide film comprises (Fig. 1, 104, dielectric layer, [0020]), a dielectric constant (k) of about 8 to about 28 (Table 1, dielectric constants of the high-dielectric constant materials, [0029-0030]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified LIM to incorporate the teachings of HSIEH, such that an article, comprising: wherein the amorphous oxide film comprises a dielectric constant (k) of about 8 to about 28, so that the amount of variation of the threshold voltage is greatly reduced and data retention of the flash memory is enhanced (HSIEH, [0014]).
Regarding Claim 10, LIM as modified by HSIEH teaches the transistor structure (Fig. 4, thin film transistor using gate dielectric layer; NMOS for a thin film transistor (TFT), [0016-0017], [0027], [0039]), of claim 9, wherein the substrate (Fig. 1, wafer in S10, Fig. 2, 1, silicon layer is formed on a general substrate, [0033]) comprises silicon (Si), germanium (Ge), one or more group III-V semiconductor, InP, InAs, bare glass (SiO2) or combinations thereof (Fig. 4, single crystal silicon substrate, [0027]).
Regarding Claim 12, LIM as modified by HSIEH teaches the transistor structure (Fig. 4, thin film transistor using gate dielectric layer; NMOS for a thin film transistor (TFT), [0016-0017], [0027], [0039]), of claim 9, wherein the first oxide comprises ZrO2 (Fig. 2, 2, plasma oxide layer and 3, ALD oxide layer; to get a higher dielectric constant, the high dielectric layer can be formed on the plasma oxide layer, her the high dielectric layer includes zirconium oxide (ZrO2), hafnium oxide (HfO2) etc., [0019], [0034] and the second oxide comprises SiO2 (Fig. 2, 2, plasma oxide layer and 3, ALD oxide layer are deposited by in-situ for forming a high dielectric layer includes the high dielectric layer, aluminum oxide (Al2O3) or a silicate layer formed by combination of silicon dioxide (SiO2) and at least one of Al2O3 etc. [0019], [0034]).
Regarding Claim 15, LIM as modified by HSIEH teaches the transistor structure (Fig. 4, thin film transistor using gate dielectric layer; NMOS for a thin film transistor (TFT), [0016-0017], [0027], [0039]) of claim 9, wherein the amorphous oxide film (Fig. 1, S20, forming plasma oxide layer, a silicon, 1, for the gate dielectric layer is made of poly silicon or amorphous silicon, the oxygen plasma is generated on the silicon layer, 1, so that the plasma oxide layer, 2 is grown as shown in Fig. 2, [0033]) comprises a thickness of at least about 200 A to about 2,000 A (In the case that the Al2O3 gate dielectric layer was formed on the single crystal silicon substrate, the Al2O3 gate dielectric layer had a thickness of 100 nm. Oppositely, in the case that the plasma oxide layer was added between the Al2O3 gate dielectric layer and the single crystal silicon substrate, the plasma oxide layer had a thickness of 20 nm and the PEALD Al2O3 gate dielectric layer had a thickness of 80 nm; (100 nm + 20 nm + 80 nm = 200 nm = 2000Å; ranging from 20 nm to 200 nm meaning 200 Å to 2000 Å; [0044]; In another embodiment, the natural oxide layer having a thickness of 5 nm; ALD oxide layer with a thickness of 15 nm; Al2O3 having a thickness of 50 nm; and the whole layer thickness is about 70 nm which is equivalent to 700 Å, [0043], therefore the thickness range from 50 Å to 700 Å).
Regarding Claim 17, LIM teaches a method (Figs. 1/4, flow chart of forming a gate dielectric layer, thin film transistor using gate dielectric layer; NMOS for a thin film transistor (TFT), [0016-0017], [0024], [0027], [0039]) of forming an amorphous oxide film (Fig. 1, S20, forming plasma oxide layer, a silicon, 1, for the gate dielectric layer is made of poly silicon or amorphous silicon, the oxygen plasma is generated on the silicon layer, 1, so that the plasma oxide layer, 2 is grown as shown in Fig. 2, [0033]), comprising:
performing a plasma-enhanced atomic layer deposition (ALD) process (Figs. 1-2, 3, ALD oxide layer, [0031-0035], [0039]); (Fig. 1, at operation S20, a plasma oxide layer is formed using oxygen plasma; at operation S30, an ALD oxide (SiO2) layer or a high dielectric layer is deposited by a plasma-enhanced ALD or PEALD process; [0031]) to form an amorphous oxide film comprising a first oxide (Figs. 1-2, 4, high dielectric layer, [0031-0035], [0039]) and a second oxide (Figs. 1-2, 3, ALD oxide layer, [0031-0035], [0039]), wherein the first oxide comprises ZrO2, HfO2 or a combination thereof (Fig. 2, 2, plasma oxide layer and 3, ALD oxide layer; to get a higher dielectric constant, the high dielectric layer can be formed on the plasma oxide layer, her the high dielectric layer includes zirconium oxide (ZrO2), hafnium oxide (HfO2) etc., [0019], [0034]), wherein the second oxide comprises SiO2, A12O3, NO, or combinations thereof (Fig. 2, 2, plasma oxide layer and 3, ALD oxide layer are deposited by in-situ for forming a high dielectric layer includes the high dielectric layer, aluminum oxide (Al2O3) or a silicate layer formed by combination of silicon dioxide (SiO2) and at least one of Al2O3 etc. [0019], [0034]), and
wherein performing the plasma-enhanced ALD process (Figs. 1-2, 3, ALD oxide layer, [0031-0035], [0039]); (Fig. 1, at operation S20, a plasma oxide layer is formed using oxygen plasma; at operation S30, an ALD oxide (SiO2) layer or a high dielectric layer is deposited by a plasma-enhanced ALD or PEALD process; [0031]) comprises:
performing one or more ALD deposition super-cycles (Figs. 1-2, 3, ALD oxide layer, [0031-0035], [0039]); (Fig. 1, at operation S20, a plasma oxide layer is formed using oxygen plasma; at operation S30, an ALD oxide (SiO2) layer or a high dielectric layer is deposited by a plasma-enhanced ALD or PEALD process; [0031]), each ALD deposition super-cycle (Fig. 1, S30) comprising:
performing one or more first ALD deposition cycles to deposit a first oxide layer of the first oxide (Fig. 1, S20, Fig. 2, 2, plasma oxide layer and 3, ALD oxide layer; to get a higher dielectric constant, the high dielectric layer can be formed on the plasma oxide layer, her the high dielectric layer includes zirconium oxide (ZrO2), hafnium oxide (HfO2) etc., [0019], [0034]); and
performing one or more second ALD deposition cycles to deposit a second oxide layer to form the amorphous oxide layer of the second oxide (Fig. 1, S30, Fig. 2, 2, plasma oxide layer and 3, ALD oxide layer are deposited by in-situ for forming a high dielectric layer includes the high dielectric layer, aluminum oxide (Al2O3) or a silicate layer formed by combination of silicon dioxide (SiO2) and at least one of Al2O3 etc. [0019], [0034]).
Though LIM teaches the gate dielectric thin film comprises a high K dielectric oxides, LIM does not explicitly disclose a method of forming an amorphous oxide film comprising: wherein the amorphous oxide film comprises a dielectric constant (k) of about 8 to about 28.
HSIEH teaches a method of forming an amorphous oxide film (Fig. 1, method of forming a charge trapping layer on the flash memory substrate, [0007], [0017]) comprising:
wherein the amorphous oxide film comprises (Fig. 1, 104, dielectric layer, [0020]), a dielectric constant (k) of about 8 to about 28 (Table 1, dielectric constants of the high-dielectric constant materials, [0029-0030]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified LIM to incorporate the teachings of HSIEH, such that a method of forming an amorphous oxide film comprising: wherein the amorphous oxide film comprises a dielectric constant (k) of about 8 to about 28, so that the amount of variation of the threshold voltage is greatly reduced and data retention of the flash memory is enhanced (HSIEH, [0014]).
Claim(s) 3, 11, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over LIM, in view of HSIEH, and further in view of Hideaki Machida et al, (hereinafter MACHIDA), JP 2003124460 A.
Regarding Claim 3, LIM as modified by HSIEH teaches the article of claim 1.
LIM further teaches the article (Fig. 4, thin film transistor using gate dielectric layer; NMOS for a thin film transistor (TFT), [0016-0017], [0027], [0039]).
LIM though teaches the article produced by the PEALD and ALD processes having good thin film density [0034], LIM as modified by HSIEH does not explicitly disclose, the article, wherein a molar ratio of the first oxide to the second oxide is about 1:1 to about 100:1.
MACHIDA teaches the article (a gate oxide film, [0001]), wherein a molar ratio ([0025]) of the first oxide (oxide film forming material, particularly the gate oxide film forming material comprises one or more first compounds selected from the group consisting of Zr/Hf alkoxide compounds etc., [0025]) to the second oxide (a group of silicon based compound, [0014]) is about 1:1 to about 100:1 (the molar ratio of the first compound to the second compound is preferably 1000:1 to 1:100, particularly preferably 100:1 to 1:10, [0020]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LIM as modified by HSIEH to incorporate the teachings of MACHIDA, such that the article, wherein a molar ratio of the first oxide to the second oxide is about 1:1 to about 100:1, so to produce a gate dielectric oxide film that can efficiently operate under conditions of charge accumulations from source and drain that pass through the gate oxide film of a miniaturized semiconductor device (MACHIDA, [0001-0009]).
Regarding Claim 11, LIM as modified by HSIEH teaches the transistor structure of claim 9.
LIM further teaches the transistor structure (Fig. 4, thin film transistor using gate dielectric layer; NMOS for a thin film transistor (TFT), [0016-0017], [0027], [0039]).
LIM though teaches the transistor structure produced by the PEALD and ALD processes having good thin film density [0034], LIM as modified by HSIEH does not explicitly disclose, the transistor structure, wherein a molar ratio of the first oxide to the second oxide is about 1:1 to about 100:1.
MACHIDA teaches the transistor structure (a gate oxide film, [0001]), wherein a molar ratio ([0025]) of the first oxide (oxide film forming material, particularly the gate oxide film forming material comprises one or more first compounds selected from the group consisting of Zr/Hf alkoxide compounds etc., [0025]) to the second oxide (a group of silicon based compound, [0014]) is about 1:1 to about 100:1 (the molar ratio of the first compound to the second compound is preferably 1000:1 to 1:100, particularly preferably 100:1 to 1:10, [0020]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LIM as modified by HSIEH to incorporate the teachings of MACHIDA, such that the transistor structure, wherein a molar ratio of the first oxide to the second oxide is about 1:1 to about 100:1, so to produce a gate dielectric oxide film that can efficiently operate under conditions of charge accumulations from source and drain that pass through the gate oxide film of a miniaturized semiconductor device (MACHIDA, [0001-0009]).
Regarding Claim 19, LIM as modified by HSIEH teaches the method of claim 17.
LIM as modified by HSIEH does not explicitly disclose the method, wherein: the Zr precursor is used for the first half reaction, wherein the Si precursor is used for the second half reaction, and wherein the first oxygen reactant and the second oxygen reactant is independently selected from a group consisting of water (H2O), ozone (O3), oxygen (O2) hydrogen peroxide (H2O2) and oxygen radical (O-).
MACHIDA teaches the method (Fig. 1, method for forming a gate oxide film, [0001]), wherein: the Zr precursor is used for the first half reaction (Zr alkoxide compounds, Zr β-diketonate compounds, Zr alkylamide compounds, [0025], [0040]), wherein the Si precursor is used for the second half reaction (silicon-based compound, [0014], [0045]), and wherein the first oxygen reactant and the second oxygen reactant is independently selected from a group consisting of water (H2O), ozone (O3), oxygen (O2) hydrogen peroxide (H2O2) and oxygen radical (O-) (oxidizing atmosphere selected from the group consisting of oxygen, nitrous oxide, ozone, water and hydrogen peroxide, [0017]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LIM as modified by HSIEH to incorporate the teachings of MACHIDA, such that the method, wherein: the Zr precursor is used for the first half reaction, wherein the Si precursor is used for the second half reaction, and wherein the first oxygen reactant and the second oxygen reactant is independently selected from a group consisting of water (H2O), ozone (O3), oxygen (O2) hydrogen peroxide (H2O2) and oxygen radical (O-), so that to produce the gate oxide film interface with the silicon layer must be stable and also the dielectric constant must be high with thickness as thin as 10 nm or less for miniaturization in order to improve the signal processing speed, in particular, the distance between the source and rain becoming shorter (MACHIDA, [0001-0006]).
Claim(s) 5-6, 8, 13-14, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable LIM, in view of HSIEH, and further in view of Shigenori Hayashi et al, (hereinafter HAYASHI), US 2006028126 A1.
Regarding Claim 5, LIM as modified by HSIEH teaches the article of claim 1.
LIM further teaches the article (Fig. 4, thin film transistor using gate dielectric layer; NMOS for a thin film transistor (TFT), [0016-0017], [0027], [0039]).
LIM though teaches the article, the second metal oxide of the amorphous oxide film; and a silicate layer formed by combination of silicon dioxide (SiO2) and at least one of Al2O3, TiO2, Ta2O5, HfO2, ZrO2 [0019], LIM as modified by HSIEH does not explicitly disclose the article, wherein the second oxide is a doping metal oxide, and wherein the amorphous oxide film comprises the second metal in an amount of about 1 mol% to about 50 mol%.
HAYASHI teaches the article (Fig 2, a partial cross-sectional view illustrating a gate insulating film and a portion near the gate insulating film in the semiconductor device, [0032]) wherein the second oxide (Fig. 15A, 14, silicon oxide, SiO2 in HfO2-SiO2, [0011], [0054]) is a doping metal oxide, and wherein the amorphous oxide film article (Fig 15A, 15, a gate insulating film, [0032]) comprises the second metal in an amount of about 1 mol% to about 50 mol% (Fig. 12, stable phases of hafnium silicate (HfxSi1-xO4) are SiO2, Hf0.5Si0.5O2 and HfO2, [0064]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LIM as modified by HSIEH to incorporate the teachings of HAYASHI, such that the article, wherein the second oxide is a doping metal oxide, and wherein the amorphous oxide film comprises the second metal in an amount of about 1 mol% to about 50 mol%, so that to optimize the electron mobility in a region under the metal oxide film (15), that is the channel region of the semiconductor device (HAYASHI, Fig. 19, [0070]).
Regarding Claim 6, LIM as modified by HSIEH teaches the article of claim 1.
LIM further teaches the article (Fig. 4, thin film transistor using gate dielectric layer; NMOS for a thin film transistor (TFT), [0016-0017], [0027], [0039]).
LIM though teaches the article, wherein the first oxide comprises ZrO2, wherein the second oxide comprises SiO2; and a silicate layer formed by combination of silicon dioxide (SiO2) and at least one of Al2O3, TiO2, Ta2O5, HfO2, ZrO2 [0019], LIM as modified by HSIEH does not explicitly disclose the article, wherein the first oxide comprises ZrO2, wherein the second oxide comprises SiO2, and wherein the SiO2 is present in an amount of at least about 9 mol% to about 50 mol%.
HAYASHI teaches the article (Fig 2, a partial cross-sectional view illustrating a gate insulating film and a portion near the gate insulating film in the semiconductor device, [0032]) wherein the second oxide (Fig. 15A, 14, silicon oxide, SiO2 in ZrO2-SiO2, HfO2-SiO2, [0011], [0054]) is a doping metal oxide, and wherein the amorphous oxide film article (Fig 15A, 15, a gate insulating film, [0032]) comprises the second metal in an amount of about 1 mol% to about 50 mol% (Figs. 12-13, stable phases of hafnium silicate (HfxSi1-xO4) are SiO2, Hf0.5Si0.5O2 and HfO2, [0064]). [it should be noted that substituting (Zr) for (Hf) in above compound HfxSi1-xO4 is a simple substitution of one known element for another to obtain predictable results (See MPEP2143)"].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LIM as modified by HSIEH to incorporate the teachings of HAYASHI, such that the article, wherein the first oxide comprises ZrO2, wherein the second oxide comprises SiO2, and wherein the SiO2 is present in an amount of at least about 9 mol% to about 50 mol%, so that to optimize the electron mobility in a region under the metal oxide film (15), that is the channel region of the semiconductor device (HAYASHI, Fig. 19, [0070]).
Regarding Claim 8, LIM as modified by HSIEH teaches the article of claim 1.
LIM further teaches the method (Fig. 4, thin film transistor using gate dielectric layer; NMOS for a thin film transistor (TFT), [0016-0017], [0027], [0039]).
LIM as modified by HSIEH does not teaches the article, wherein the amorphous oxide film comprises a first ratio of the first metal to the second metal within a first thickness of the amorphous oxide film, a second ratio of the first metal to the second metal within a second thickness of the amorphous oxide film, and a third ratio of the first metal to the second metal within a third thickness of the amorphous oxide film.
HAYASHI teaches the article (Fig 2, a partial cross-sectional view illustrating a gate insulating film and a portion near the gate insulating film in the semiconductor device, [0032]) wherein the amorphous oxide film (Fig 15A, 15, a gate insulating film, [0032]) comprises a first ratio of the first metal to the second metal within a first thickness of the amorphous oxide film (Fig. 2, first metal oxide film 105a which is a low-κ stable phase having a Hf concentration x in hafnium silicate (HfxSi1-xO4) of 0.25 and has a thickness of 1.0 nm, [0083]), a second ratio of the first metal to the second metal within a second thickness of the amorphous oxide film (Fig. 2, a second metal oxide film 105b which is a high-κ stable phase having a Hf concentration x of 0.50 and has a thickness of 1.5 nm, [0083]) and a third ratio of the first metal to the second metal within a third thickness of the amorphous oxide film (Fig. 2, a third metal oxide film 105c which is a low-κ stable phase having a Hf concentration x of 0.25 and has a thickness of 0.5 nm, [0083]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LIM as modified by HSIEH to incorporate the teachings of HAYASHI, such that the article, wherein the amorphous oxide film comprises a first ratio of the first metal to the second metal within a first thickness of the amorphous oxide film, a second ratio of the first metal to the second metal within a second thickness of the amorphous oxide film, and a third ratio of the first metal to the second metal within a third thickness of the amorphous oxide film, so that the Hf concentration reduces the leakage currents, Jg at the same equivalent oxide thickness, EOT (HAYASHI, Fig. 20, [0095]).
Regarding Claim 13, LIM as modified by HSIEH teaches the transistor structure of claim 9.
LIM further teaches the transistor structure (Fig. 4, thin film transistor using gate dielectric layer; NMOS for a thin film transistor (TFT), [0016-0017], [0027], [0039]).
LIM though teaches the transistor structure, the second metal oxide of the amorphous oxide film; and a silicate layer formed by combination of silicon dioxide (SiO2) and at least one of Al2O3, TiO2, Ta2O5, HfO2, ZrO2 [0019], LIM as modified by HSIEH does not explicitly disclose the transistor structure, wherein the second oxide is a doping metal oxide, and wherein the amorphous oxide film comprises the second metal in an amount of about 1 mol% to about 50 mol%.
HAYASHI teaches the transistor structure (Fig 2, a partial cross-sectional view illustrating a gate insulating film and a portion near the gate insulating film in the semiconductor device, [0032]) wherein the second oxide (Fig. 15A, 14, silicon oxide, SiO2 in HfO2-SiO2, [0011], [0054]) is a doping metal oxide, and wherein the amorphous oxide film article (Fig 15A, 15, a gate insulating film, [0032]) comprises the second metal in an amount of about 1 mol% to about 50 mol% (Fig. 12, stable phases of hafnium silicate (HfxSi1-xO4) are SiO2, Hf0.5Si0.5O2 and HfO2, [0064]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LIM as modified by HSIEH to incorporate the teachings of HAYASHI, such that the transistor structure, wherein the second oxide is a doping metal oxide, and wherein the amorphous oxide film comprises the second metal in an amount of about 1 mol% to about 50 mol%, so that to optimize the electron mobility in a region under the metal oxide film (15), that is the channel region of the semiconductor device (HAYASHI, Fig. 19, [0070]).
Regarding Claim 14, LIM as modified by HSIEH teaches the transistor structure of claim 9.
LIM further teaches the transistor structure (Fig. 4, thin film transistor using gate dielectric layer; NMOS for a thin film transistor (TFT), [0016-0017], [0027], [0039]).
LIM though teaches the transistor structure, wherein the first oxide comprises ZrO2, wherein the second oxide comprises SiO2; and a silicate layer formed by combination of silicon dioxide (SiO2) and at least one of Al2O3, TiO2, Ta2O5, HfO2, ZrO2 [0019], LIM as modified by HSIEH does not explicitly disclose the transistor structure, wherein the first oxide comprises ZrO2, wherein the second oxide comprises SiO2, and wherein the SiO2 is present in an amount of at least about 9 mol% to about 50 mol%.
HAYASHI teaches the transistor structure (Fig 2, a partial cross-sectional view illustrating a gate insulating film and a portion near the gate insulating film in the semiconductor device, [0032]) wherein the second oxide (Fig. 15A, 14, silicon oxide, SiO2 in ZrO2-SiO2, HfO2-SiO2, [0011], [0054]) is a doping metal oxide, and wherein the amorphous oxide film article (Fig 15A, 15, a gate insulating film, [0032]) comprises the second metal in an amount of about 1 mol% to about 50 mol% (Figs. 12-13, stable phases of hafnium silicate (HfxSi1-xO4) are SiO2, Hf0.5Si0.5O2 and HfO2, [0064]). [it should be noted that substituting (Zr) for (Hf) in above compound HfxSi1-xO4 is a simple substitution of one known element for another to obtain predictable results (See MPEP2143)"].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LIM as modified by HSIEH to incorporate the teachings of HAYASHI, such that the transistor structure, wherein the first oxide comprises ZrO2, wherein the second oxide comprises SiO2, and wherein the SiO2 is present in an amount of at least about 9 mol% to about 50 mol%, so that to optimize the electron mobility in a region under the metal oxide film (15), that is the channel region of the semiconductor device (HAYASHI, Fig. 19, [0070]).
Regarding Claim 16, LIM as modified by HSIEH teaches the transistor structure of claim 9.
LIM further teaches the transistor structure (Fig. 4, thin film transistor using gate dielectric layer; NMOS for a thin film transistor (TFT), [0016-0017], [0027], [0039]).
LIM as modified by HSIEH does not teaches the transistor structure, wherein the amorphous oxide film comprises a first ratio of the first metal to the second metal within a first thickness of the amorphous oxide film, a second ratio of the first metal to the second metal within a second thickness of the amorphous oxide film, and a third ratio of the first metal to the second metal within a third thickness of the amorphous oxide film.
HAYASHI teaches the transistor structure (Fig 2, a partial cross-sectional view illustrating a gate insulating film and a portion near the gate insulating film in the semiconductor device, [0032]) wherein the amorphous oxide film (Fig 15A, 15, a gate insulating film, [0032]) comprises a first ratio of the first metal to the second metal within a first thickness of the amorphous oxide film (Fig. 2, first metal oxide film 105a which is a low-κ stable phase having a Hf concentration x in hafnium silicate (HfxSi1-xO4) of 0.25 and has a thickness of 1.0 nm, [0083]), a second ratio of the first metal to the second metal within a second thickness of the amorphous oxide film (Fig. 2, a second metal oxide film 105b which is a high-κ stable phase having a Hf concentration x of 0.50 and has a thickness of 1.5 nm, [0083]) and a third ratio of the first metal to the second metal within a third thickness of the amorphous oxide film (Fig. 2, a third metal oxide film 105c which is a low-κ stable phase having a Hf concentration x of 0.25 and has a thickness of 0.5 nm, [0083]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LIM as modified by HSIEH to incorporate the teachings of HAYASHI, such that the transistor structure, wherein the amorphous oxide film comprises a first ratio of the first metal to the second metal within a first thickness of the amorphous oxide film, a second ratio of the first metal to the second metal within a second thickness of the amorphous oxide film, and a third ratio of the first metal to the second metal within a third thickness of the amorphous oxide film, so that the Hf concentration reduces the leakage currents, Jg at the same equivalent oxide thickness, EOT (HAYASHI, Fig. 20, [0095]).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable LIM, in view of HSIEH, in view of Kie Ahn et al, (hereinafter AHN), US 20060246741 A1, and further in view of Vijay Narayanan et al, (hereinafter NARAYANAN), US 20180040710 A1.
Regarding Claim 18, LIM as modified by HSIEH teaches the method of claim 17.
LIM further teaches the method (Figs. 1/4, flow chart of forming a gate dielectric layer, thin film transistor using gate dielectric layer; NMOS for a thin film transistor (TFT), [0016-0017], [0024], [0027], [0039]), wherein:
each of the one or more first ALD deposition cycles (Figs. 1-2, 3, ALD oxide layer, [0031-0035], [0039]); (Fig. 1, at operation S20, a plasma oxide layer is formed using oxygen plasma; at operation S30, an ALD oxide (SiO2) layer or a high dielectric layer is deposited by a plasma-enhanced ALD or PEALD process; [0031]) comprises:
contacting a surface with at least one of a Zr precursor or an Hf precursor in a first half reaction (Fig. 1, [0014], [0019]); and
contacting the surface with a first oxygen reactant in a second half reaction (Fig. 1, oxygen plasma, [0031-0040]) to form the first oxide layer (Figs. 1-2, 4, high dielectric layer, [0031-0035], [0039]); and
each of the one or more second ALD deposition cycles (Figs. 1-2, 3, ALD oxide layer, [0031-0035], [0039]); (Fig. 1, at operation S20, a plasma oxide layer is formed using oxygen plasma; at operation S30, an ALD oxide (SiO2) layer or a high dielectric layer is deposited by a plasma-enhanced ALD or PEALD process; [0031]) comprises:
contacting the surface with at least one of a Si precursor, an Al precursor or an N precursor in a third half reaction (Fig. 1, [0019], [0031]); and
contacting the surface with the first oxygen reactant or a second oxygen reactant in a fourth half reaction (Fig. 1, oxygen plasma, [0031-0040]) to form the second oxide layer (Figs. 1-2, 3, ALD oxide layer, [0031-0035], [0039]).
Though LIM teaches the ALD deposition cycles using silicate layer formed by combination of SiO2 and at least one of HfO2, ZrO2 etc, [0019], LIM as modified by HSIEH does not explicitly disclose the method wherein each of the one or more first ALD deposition cycles comprises: contacting a surface with at least one of a Zr precursor or an Hf precursor in a first half reaction; and contacting the surface with a first oxygen reactant in a second half reaction.
AHN teaches the method (Fig. 2A, atomic layer deposition system for processing a layer, [0015]) wherein:
each of the one or more first ALD deposition cycles (Fig. 4, flow diagram of a method to process a nanolaminate of HfO2/ZrO2 by atomic layer deposition, step 430, hafnium cycles performed, [0076]; step 455, zirconium cycles, [0084]; [0017-0018]) comprises:
contacting a surface with at least one of a Zr precursor or an Hf precursor in a first half reaction (Fig. 4, 410, pulse precursor containing hafnium, HfO2 using HfI4 precursor; 435, pulse precursor containing zirconium, ZrI4 or ZrCl4, [0042], [0072], [0077]); and
contacting the surface with a first oxygen reactant in a second half reaction (Fig. 4, 420, pulse first oxygen containing precursor, vapor solution H2O-H2O2 can be used as the oxygen containing precursor, [0073]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LIM as modified by HSIEH to incorporate the teachings of AHN, such that the method wherein each of the one or more first ALD deposition cycles comprises: contacting a surface with at least one of a Zr precursor or an Hf precursor in a first half reaction; and contacting the surface with a first oxygen reactant in a second half reaction, so that to produce HfO2/ZrO2 nanolaminates processed in relatively low temperatures can provide amorphous dielectric films having relatively low leakage current for use as dielectric layers in electronic devices and systems (AHN, Fig. 4, [0128]).
LIM as modified by HSIEH and AHN does not explicitly disclose the method wherein each of the one or more second ALD deposition cycles comprises: contacting the surface with at least one of a Si precursor, an Al precursor or an N precursor in a third half reaction; and contacting the surface with the first oxygen reactant or a second oxygen reactant in a fourth half reaction.
NARAYANAN teaches the method (Fig. 1, method for forming a semiconductor device, [0007]) wherein:
each of the one or more second ALD deposition cycles (Figs. 1 and 8, flow charts illustrating the first and last method of a gate forming with metal oxide or binary metal oxide layers using atomic layer deposition chamber (ALD), [0034]) comprises:
contacting the surface with at least one of a Si precursor, an Al precursor or an N precursor in a third half reaction (Fig. 1, step 10, aluminum containing gas precursor and/or nitrogen plasma and/or a hydrogen plasma, [0038], [0061]); and
contacting the surface with the first oxygen reactant or a second oxygen reactant in a fourth half reaction (Fig. 1, oxygen containing atmosphere exposure, [0028], [0034]). [Note: It should also be noted that substituting (oxygen containing plasma) for (nitrogen containing plasma) in formation of binary metal oxide interlayer, TiAlON, in the prior-art, is a simple substitution of one known element for another to obtain predictable results (See MPEP2143)"].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LIM as modified by HSIEH and AHN to incorporate the teachings of NARAYANAN, such that the method wherein: each of the one or more second ALD deposition cycles comprises: contacting the surface with at least one of a Si precursor, an Al precursor or an N precursor in a third half reaction; and contacting the surface with the first oxygen reactant or a second oxygen reactant in a fourth half reaction, to produce binary metal oxide, (TiAlON) layer having appropriate thickness with high quality, further deposited on high k dielectric HfO2 layer, and thus can obtain a capacitance equivalent thickness (CET) as low as 10 Å, with low leakage small hysteresis and good interface quality (NARAYANAN, [0027], [0063]).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable LIM, in view of HSIEH, and further in view of Yuia Zhai et al, (hereinafter ZHAI), US 20190206691 A1.
Regarding Claim 20, LIM as modified by HSIEH teaches the method of claim 17.
LIM further teaches the method (Figs. 1/4, flow chart of forming a gate dielectric layer, thin film transistor using gate dielectric layer; NMOS for a thin film transistor (TFT), [0016-0017], [0024], [0027], [0039]) of claim 17, wherein:
the plasma-enhanced atomic layer deposition process (Figs. 1-2, 3, ALD oxide layer, [0031-0035], [0039]); (Fig. 1, at operation S20, a plasma oxide layer is formed using oxygen plasma; at operation S30, an ALD oxide (SiO2) layer or a high dielectric layer is deposited by a plasma-enhanced ALD or PEALD process; [0031]) further comprises:
performing one or more third deposition cycles to deposit an adhesion metal oxide layer on the surface before performing the one or more ALD deposition super-cycles (Figs. 1-2, 3, ALD oxide layer, [0031-0035], [0039]); (Fig. 1, at operation S20, a plasma oxide layer is formed using oxygen plasma; at operation S30, an ALD oxide (SiO2) layer or a high dielectric layer is deposited by a plasma-enhanced ALD or PEALD process; [0031]), wherein the adhesion metal oxide layer comprises one or more of SiO2, A12O3, HfO2, SiCON, SiC or combinations thereof (Fig. 1, [0019], [0031]).
Though LIM teaches the deposition cycle via ALD process, LIM as modified by HSIEH does not explicitly disclose the method wherein: performing one or more third deposition cycles to deposit an adhesion metal oxide layer on the surface before performing the one or more ALD deposition super-cycles, wherein the adhesion metal oxide layer comprises one or more of SiO2, A12O3, HfO2, SiCON, SiC or combinations thereof.
ZHAI teaches the method (Fig. 1, cross-sectional view of a processing chamber that may be used to deposit a gate insulating layer, [0009]) wherein: performing one or more third deposition cycles to deposit an adhesion metal oxide layer (Fig. 2, 210A, the interface layer, [0025]) on the surface (Fig. 2, 204, channel layer) before performing the one or more ALD deposition super-cycles (Fig. 1, PECVD, [0015]) wherein the adhesion metal oxide layer (Fig. 2, the interface layer, 210A has a good interface between both the channel layer, 204 and the high-k dielectric layer, 210B thereby improving adhesion, [0027]) comprises one or more of SiO2, A12O3, HfO2, SiCON, SiC or combinations thereof (Fig. 2, SiO2, Al2O3, TiO2, [0025]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LIM as modified by HSIEH to incorporate the teachings of ZHAI, such that the method wherein: performing one or more third deposition cycles to deposit an adhesion metal oxide layer on the surface before performing the one or more ALD deposition super-cycles, wherein the adhesion metal oxide layer comprises one or more of SiO2, A12O3, HfO2, SiCON, SiC or combinations thereof, so that the silicon containing interface layer improves adhesion and interaction between the active channel layer and the metal gate with the high-k dielectric value of the gate layer enables for a faster driving current that improves brightness and performance of the display device (ZHAI, [0032]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20070096104 – Figure 1
STATEMENT OF RELEVANCE – The graph showing gate leakage (Ig) with equivalent oxide thickness (EOT) with HfO2, SiO2 and HfSiO compounds.
US 20110037117 A1 – Figures 2 and 3
STATEMENT OF RELEVANCE – Flow diagram of elements of a method to form a dielectric layer containing a lanthanum aluminum oxide layer.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
1 Table 1 and Fig. 7: Thickness (L in nm) and open porosity (ϕ in %) of sample SGP-0.2 shows ϕ value is about 8% for film thickness, L of 80.5 nm (as closed to the prior art of 50~150 nm); NPL - :Comparing methods for measuring thickness, refractive index and porosity of mesoporous thin films, Tiphaine Galy, Michal Marszewsi, Sophia King, Yan Yan, Sarah H. Tolbert and Laurent Pilon, Microporous and Mesoporous Materials, 291, 109677 (2020); DOI: 10.1016/j.micromeso.2019.109677.
2 Table 1 and Fig. 7: Thickness (L in nm) and open porosity (ϕ in %) of sample SGP-0.2 shows ϕ value is about 8% for film thickness, L of 80.5 nm (as closed to the prior art of 50~150 nm); NPL - :Comparing methods for measuring thickness, refractive index and porosity of mesoporous thin films, Tiphaine Galy, Michal Marszewsi, Sophia King, Yan Yan, Sarah H. Tolbert and Laurent Pilon, Microporous and Mesoporous Materials, 291, 109677 (2020); DOI: 10.1016/j.micromeso.2019.109677.