DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on 6/26/2026 is/are in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner.
Response to Amendment
The amendment with respect to claim(s) 1, 3-7, 8-15, and 17-20 filed on 6/26/2026 have been fully considered for examination based on their merits. The previously presented claim(s) 2 has been considered. Claim(s) 8, and 16 are canceled.
Response to Arguments
Applicant’s arguments with respect to independent claim(s) 1, 9, and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 7, and 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Judit (Gloria) Lisoni Reyes et al, (hereinafter REYES), US 20140346582 A1.
Regarding Claim 1, REYES teaches an article (Fig. 1, 100, NVM device), comprising:
a substrate (Fig. 1, 105); and
an amorphous oxide film (Fig. 1, 150, inter-gate dielectric (IGD) structure; may comprise an amorphous layer, [0011], [0054], [0057]) overlaying at least a portion of the substrate (Fig. 1, 105), wherein the amorphous oxide film (Fig. 1, 150, inter-gate dielectric (IGD) structure; may comprise an amorphous layer, [0011], [0054], [0057]) comprises a bulk metal oxide (Fig. 1, 155/165, first layer/third layer) and a dopant metal oxide (Fig. 1, 160, second layer) used to convert the bulk metal oxide from a crystalline phase to an amorphous phase (Fig. 1, 160, second layer may comprise one of the aluminum oxide layer may be annealed to provide a crystalline layer or it may comprise an amorphous layer, [0011]),
wherein the bulk metal oxide (Fig. 1, 155/165, first layer/third layer) comprises zirconium oxide (ZrO2), hafnium oxide (HfO2) or a combination thereof (Fig. 1, 155/165, first layer/third layer of the IGD structure, 150, comprises HfAlO, due to the presence of HfO2 (hafnium oxide) and Al2O3 process cycles, [0067]),
wherein the dopant metal oxide (Fig. 1, 160, second layer) comprises silicon dioxide (SiO2), aluminum oxide (A1203), nitric oxide (NO) or combinations thereof (Fig. 1, 160, the second layer of the inter-gate dielectric structure may comprise one of: an aluminum oxide layer and a silicon oxide layer, [0011]),
wherein the amorphous oxide film (Fig. 1, 150, inter-gate dielectric (IGD) structure; may comprise an amorphous layer, [0011], [0054], [0057]) is conformal and comprises has a porosity of less than about 1% (due to the presence of hafnium oxide (HfO2), no defective and a good quality high-k interfacial layer is formed, [0067]; due to the good morphological properties HfAlO, and its good stability with TiN, a HfAlO-Al2O3-HfAlO stack has been successfully used as IGD structure on a Si/TiN/HFG, [0124]),
wherein the amorphous oxide film (Fig. 1, 150, inter-gate dielectric (IGD) structure; may comprise an amorphous layer, [0011], [0054], [0057]) comprises has a dielectric constant (k) of about 8 to about 28 (Fig. 1, 150, IGD structure, HfAlO as high-k layer (~19), and Al2O3 as low-k layer (~9), [0109]; an HOH IGD structure or stack comprise a layer of SiO2 sandwiched in between two HfAlO layers, dielectric constant of stoichiometric SiO2 which is known to be about 3.9, [0055], [0059]), and
wherein the amorphous oxide film (Fig. 1, 150, inter-gate dielectric (IGD) structure; may comprise an amorphous layer, [0011], [0054], [0057]) comprises a first ratio of the bulk metal oxide to the dopant metal oxide within a first thickness of the amorphous oxide film (Fig. 1, 150, IGD structure, HaH ratio (HfAlO/Al2O3/HfAlO (HaH with no Al2O3 PDA), [0112-0113], (HaH thickness (nm) = 8, 5, 8; EOT = 6.6 nm) [0119-0120]), a second ratio of the bulk metal oxide to the dopant metal oxide within a second thickness of the amorphous oxide film (Fig. 1, 150, IGD structure, HaH ratio HfAlO/Al2O3/HfAlO (HaH with no Al2O3 PDA), [0112-0113], (HaH thickness (nm) = 8, 5, 4; EOT = 5.3 nm), [0119-0120]), and a third ratio of the bulk metal oxide to the dopant metal oxide within a third thickness of the amorphous oxide film (Fig. 1, 150, IGD structure, HaH ratio HfAlO/Al2O3/HfAlO (HaH with no Al2O3 PDA), [0112-0113], (HaH thickness (nm) = 6, 4, 4; EOT = 4.7 nm), [0119-0120]).
Regarding Claim 2, REYES teaches the article (Fig. 1, 100, NVM device) of claim 1, wherein the substrate (Fig. 1, 105) comprises silicon (Si), germanium (Ge), one or more group III-V semiconductor, InP, InAs, bare glass (SiO2) or combinations thereof (Si semiconductor substrate, 105, [0095]).
Regarding Claim 3, REYES teaches the article (Fig. 1, 100, NVM device) article of claim 1, wherein a molar ratio of the bulk metal oxide (Fig. 1, 155/165, first layer/third layer of the IGD structure, 150, comprises HfAlO, due to the presence of HfO2 (hafnium oxide) and Al2O3 process cycles, [0067]) to the dopant metal oxide ((Fig. 1, 160, the second layer of the inter-gate dielectric structure may comprise one of: an aluminum oxide layer and a silicon oxide layer, [0011]) is about 1:1 to about 100:1 (Fig. 1, 150, IGD structure with various high-k IGD single layers or stacks: HfO2, HfAlO, Al2O3, [0101]; IGD structure, the characteristics have a 1:1 relationship as shown by the ISPP and ISPE slopes as shown in Figure 9, [0102]).
Regarding Claim 4, REYES teaches the article (Fig. 1, 100, NVM device) article of claim 1, wherein the bulk metal oxide comprises ZrO2 (Fig. 1, 155/165, first layer/third layer of the IGD structure, 150 may comprise Ti-O based layer or TiO2, [0099]; it should be noted that substituting (Zr) for (Ti) is a simple substitution of one known element for another to obtain predictable results (See MPEP2143)") and the oxide comprises SiO2 (Fig. 1, 160, the second layer of the inter-gate dielectric structure may comprise one of: an aluminum oxide layer and a silicon oxide layer, [0011]).
Regarding Claim 7, REYES teaches the article (Fig. 1, 100, NVM device) article of claim 1, wherein the amorphous oxide film (Fig. 1, 150, inter-gate dielectric (IGD) structure; may comprise an amorphous layer, [0011], [0054], [0057]) has a thickness of at least about 200 Å to about 2,000 Å (Fig. 1, 150, three-layer IGD structures, namely, HaH with layer thickness of 10nm/5nm/10nm (or total IGD structure thickness is therefore, 20 nm) [0111-0113]; Note: 1 Å = 0.1 nm).
Regarding Claim 17, REYES teaches a method of forming an amorphous oxide film (Fig. 1, 100, a method of manufacturing a non-volatile (NVM) device, [0018]; Fig. 1, 150, inter-gate dielectric (IGD) structure; may comprise an amorphous layer, [0011], [0054], [0057]), comprising:
performing a plasma-enhanced atomic layer deposition (ALD) process ([0067]) to form an amorphous oxide film (Fig. 1, 150, inter-gate dielectric (IGD) structure; may comprise an amorphous layer, [0011], [0054], [0057]) comprising a bulk metal oxide (Fig. 1, 155/165, first layer/third layer) and a dopant metal oxide (Fig. 1, 160, second layer), wherein the bulk metal oxide (Fig. 1, 155/165, first layer/third layer) comprises ZrO2, HfO2 or a combination thereof (Fig. 1, 155/165, first layer/third layer of the IGD structure, 150, comprises HfAlO, due to the presence of HfO2 (hafnium oxide) and Al2O3 process cycles, [0067]), wherein the dopant metal oxide (Fig. 1, 160, second layer) comprises SiO2, A1203, NO, or combinations thereof (Fig. 1, 160, the second layer of the inter-gate dielectric structure may comprise one of: an aluminum oxide layer and a silicon oxide layer, [0011]), wherein the amorphous oxide film (Fig. 1, 150, inter-gate dielectric (IGD) structure; may comprise an amorphous layer, [0011], [0054], [0057]) has a dielectric constant (k) of about 8 to about 28 (Fig. 1, 150, IGD structure, HfAlO as high-k layer (~19), and Al2O3 as low-k layer (~9), [0109]; an HOH IGD structure or stack comprise a layer of SiO2 sandwiched in between two HfAlO layers, dielectric constant of stoichiometric SiO2 which is known to be about 3.9, [0055], [0059]), wherein the amorphous oxide film (Fig. 1, 150, inter-gate dielectric (IGD) structure; may comprise an amorphous layer, [0011], [0054], [0057]) comprises a first ratio of the bulk metal oxide to the dopant metal oxide within a first thickness of the amorphous oxide film (Fig. 1, 150, IGD structure, HaH ratio (HfAlO/Al2O3/HfAlO (HaH with no Al2O3 PDA), [0112-0113], (HaH thickness (nm) = 8, 5, 8; EOT = 6.6 nm) [0119-0120]), a second ratio of the bulk metal oxide to the dopant metal oxide within a second thickness of the amorphous oxide film (Fig. 1, 150, IGD structure, HaH ratio HfAlO/Al2O3/HfAlO (HaH with no Al2O3 PDA), [0112-0113], (HaH thickness (nm) = 8, 5, 4; EOT = 5.3 nm), [0119-0120]), and a third ratio of the bulk metal oxide to the dopant metal oxide within a third thickness of the amorphous oxide film (Fig. 1, 150, IGD structure, HaH ratio HfAlO/Al2O3/HfAlO (HaH with no Al2O3 PDA), [0112-0113], (HaH thickness (nm) = 6, 4, 4; EOT = 4.7 nm), [0119-0120]), and wherein performing the plasma- enhanced ALD process ([0067], [0071], [0079]) comprises:
performing one or more ALD deposition super-cycles ([0067], [0071], [0079]), wherein performing each of the one or more ALD deposition super-cycles comprises ([0067], [0071], [0079]):
performing one or more first ALD deposition cycles ([0071], [0079])to deposit a bulk metal oxide layer (Fig. 1, 155/165, first layer/third layer of the IGD structure, 150, comprises HfAlO, due to the presence of HfO2 (hafnium oxide) and Al2O3 process cycles, [0067]) of the bulk metal oxide (Fig. 1, 155/165, first layer/third layer); and
performing one or more second ALD deposition cycles ([0067]) to deposit a dopant metal oxide layer (Fig. 1, 160, the second layer of the inter-gate dielectric structure may comprise one of: an aluminum oxide layer and a silicon oxide layer, [0011]) to form the amorphous oxide layer of the dopant metal oxide (Fig. 1, 160, second layer; the aluminum oxide layer may be annealed to provide a crystalline layer or it may comprise an amorphous layer, [0011]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over REYES as applied to Claim(s) 1-4, 7, and 17 above, and in view of Matthew N. Rocklein et al, (hereinafter ROCKLEIN), US 20120292584 A1.
Regarding Claim 5, REYES teaches the transistor structure of claim 1.
REYES does not explicitly disclose the transistor structure, wherein the amorphous oxide film comprises the dopant metal oxide in an amount of at least about 1 mol% to less than about 50 mol%.
ROCKLEIN teaches the transistor structure (Fig. 1, 100, memory cell array coupled to a select device, e.g. access device such as field effect transistor (FET) or bipolar junction transistor, BJT, [0015]), wherein the amorphous oxide film (Fig. 2, 236/238, dielectric region/barrier dielectric region can be (maybe) formed to be amorphous, [0034], [0036]) comprises the dopant metal oxide (SiO2/Al2O3, AlxOy, [0034], [0036]) in an amount of at least about 1 mol% to less than about 50 mol% (Fig. 2, 236, dielectric region, example of metal oxides (MOx) that can be included in the dielectric region, 236 include a near-stoichiometric, stoichiometric, and sub- stoichiometric metal oxide material; a sub- stoichiometric oxide can be an oxide that has an oxygen percentage below a stoichiometric ratio for the oxide, the dielectric region, 236 can include other metal oxides such as a zirconium silicon oxide (ZrxSiyOz), and/or a hafnium silicon oxide (HfxSiyOz), (AlxHfyOz) [0033-0034], [0045]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified REYES to incorporate the teachings of ROCKLEIN, such that, the transistor structure, wherein the amorphous oxide film comprises the dopant metal oxide in an amount of at least about 1 mol% to less than about 50 mol%, so that the discrete barrier dielectric materials within the bulk dielectric materials can result in discrete regions of stoichiometric oxides and sub-oxides being created under programming to establish a two-state resistive memory cell that can have a low resistance state and a high resistance state (ROCKLEIN, [0022], [0006]).
Regarding Claim 6, REYES teaches the transistor structure of claim 1.
REYES does not explicitly disclose the transistor structure, wherein the bulk metal oxide comprises ZrO2, wherein the dopant metal oxide comprises SiO2, and wherein the SiO2 is present in an amount of at least about 9 mol% to less than about 50 mol%.
ROCKLEIN teaches the transistor structure (Fig. 1, 100, memory cell array coupled to a select device, e.g. access device such as field effect transistor (FET) or bipolar junction transistor, BJT, [0015]), wherein the bulk metal oxide comprises ZrO2 ([0034]), wherein the dopant metal oxide comprises SiO2 ([0034], [0036]), and wherein the SiO2 is present in an amount of at least about 9 mol% to less than about 50 mol% (Fig. 2, 236, dielectric region, example of metal oxides (MOx) that can be included in the dielectric region, 236 include a near-stoichiometric, stoichiometric, and sub- stoichiometric metal oxide material; a sub- stoichiometric oxide can be an oxide that has an oxygen percentage below a stoichiometric ratio for the oxide, the dielectric region, 236 can include other metal oxides such as a zirconium silicon oxide (ZrxSiyOz), [0033-0036]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified REYES to incorporate the teachings of ROCKLEIN, such that, the transistor structure, wherein the bulk metal oxide comprises ZrO2, wherein the dopant metal oxide comprises SiO2, and wherein the SiO2 is present in an amount of at least about 9 mol% to less than about 50 mol%, so that the discrete barrier dielectric materials within the bulk dielectric materials can result in discrete regions of stoichiometric oxides and sub-oxides being created under programming to establish a two-state resistive memory cell that can have a low resistance state and a high resistance state (ROCKLEIN, [0022], [0006]).
Claim(s) 9-12, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over REYES as applied to Claim(s) 1-4, 7, and 17 above, and in view of Chun-Hsiung Tsai el al, (hereinafter TSAI), US 20170110550 A1.
Regarding Claim 9, REYES teaches a transistor structure (Fig. 1, 100, NVM device), comprising:
a gate (Fig. 1, 170, control gate (CG) structure, [0064]);
an amorphous oxide film (Fig. 1, 150, inter-gate dielectric (IGD) structure; may comprise an amorphous layer, [0011], [0054], [0057]) overlaying at least a portion of the substrate (Fig. 1, 105), wherein the amorphous oxide film (Fig. 1, 150, inter-gate dielectric (IGD) structure; may comprise an amorphous layer, [0011], [0054], [0057]) comprises a bulk metal oxide (Fig. 1, 155/165, first layer/third layer) and a dopant metal oxide (Fig. 1, 160, second layer) used to convert the bulk metal oxide from a crystalline phase to an amorphous phase (Fig. 1, 160, second layer may comprise one of the aluminum oxide layer may be annealed to provide a crystalline layer or it may comprise an amorphous layer, [0011]),
wherein the bulk metal oxide (Fig. 1, 155, first layer) comprises zirconium oxide (ZrO2), hafnium oxide (HfO2) or a combination thereof (Fig. 1, 155/165, first layer/third layer of the IGD structure, 150, comprises HfAlO, due to the presence of HfO2 (hafnium oxide) and Al2O3 process cycles, [0067]),
wherein the dopant metal oxide (Fig. 1, 160, second layer) comprises silicon dioxide (SiO2), aluminum oxide (A1203), nitric oxide (NO) or combinations thereof (Fig. 1, 160, the second layer of the inter-gate dielectric structure may comprise one of: an aluminum oxide layer and a silicon oxide layer, [0011]),
wherein the amorphous oxide film (Fig. 1, 150, inter-gate dielectric (IGD) structure; may comprise an amorphous layer, [0011], [0054], [0057]) is conformal and comprises has a porosity of less than about 1% (due to the presence of hafnium oxide (HfO2), no defective and a good quality high-k interfacial layer is formed, [0067]; due to the good morphological properties HfAlO, and its good stability with TiN, a HfAlO-Al2O3-HfAlO stack has been successfully used as IGD structure on a Si/TiN/HFG, [0124]),
wherein the amorphous oxide film (Fig. 1, 150, inter-gate dielectric (IGD) structure; may comprise an amorphous layer, [0011], [0054], [0057]) comprises has a dielectric constant (k) of about 8 to about 28 (Fig. 1, 150, IGD structure, HfAlO as high-k layer (~19), and Al2O3 as low-k layer (~9), [0109]; an HOH IGD structure or stack comprise a layer of SiO2 sandwiched in between two HfAlO layers, dielectric constant of stoichiometric SiO2 which is known to be about 3.9, [0055], [0059]), and
wherein the amorphous oxide film (Fig. 1, 150, inter-gate dielectric (IGD) structure; may comprise an amorphous layer, [0011], [0054], [0057]) comprises a first ratio of the bulk metal oxide to the dopant metal oxide within a first thickness of the amorphous oxide film (Fig. 1, 150, IGD structure, HaH ratio (HfAlO/Al2O3/HfAlO (HaH with no Al2O3 PDA), [0112-0113], (HaH thickness (nm) = 8, 5, 8; EOT = 6.6 nm) [0119-0120]), a second ratio of the bulk metal oxide to the dopant metal oxide within a second thickness of the amorphous oxide film (Fig. 1, 150, IGD structure, HaH ratio HfAlO/Al2O3/HfAlO (HaH with no Al2O3 PDA), [0112-0113], (HaH thickness (nm) = 8, 5, 4; EOT = 5.3 nm), [0119-0120]), and a third ratio of the bulk metal oxide to the dopant metal oxide within a third thickness of the amorphous oxide film (Fig. 1, 150, IGD structure, HaH ratio HfAlO/Al2O3/HfAlO (HaH with no Al2O3 PDA), [0112-0113], (HaH thickness (nm) = 6, 4, 4; EOT = 4.7 nm), [0119-0120]).
Though REYES teaches the control gate structure formation on top of the inter-gate dielectric (IGD) structure, REYES does not explicitly disclose a transistor structure, comprising: a gate, a source, and a drain.
TSAI teaches a transistor structure (Fig. 1, 100, semiconductor device), comprising: a gate (Fig. 1, 200, gate structure), a source (Fig. 1, 110), and a drain (Fig. 1, 111).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified REYES to incorporate the teachings of TSAI, such that, a transistor structure, comprising: a gate, a source, and a drain, so that the fabrication of both planar and 3D FETs, with enhanced semiconductor structure, to achieve higher device density as well as to optimize the device efficacy (TSAI, [0002-0003]).
Regarding Claim 10, REYES as modified by TSAI teaches the transistor structure of claim 9.
REYES further teaches the transistor structure (Fig. 1, 100, NVM device), further comprising a substrate (Fig. 1, 105) that comprises silicon (Si), germanium (Ge), one or more group III-V semiconductor, InP, InAs, bare glass (SiO2) or combinations thereof (Si semiconductor substrate, 105, [0095]), wherein the amorphous oxide film (Fig. 1, 150, inter-gate dielectric (IGD) structure; may comprise an amorphous layer, [0011], [0054], [0057]) overlays at least a portion of the substrate (Fig. 1, 105).
Regarding Claim 11, REYES as modified by TSAI teaches the transistor structure of claim 9.
REYES further teaches the transistor structure (Fig. 1, 100, NVM device), wherein a molar ratio of the bulk metal oxide (Fig. 1, 155/165, first layer/third layer of the IGD structure, 150, comprises HfAlO, due to the presence of HfO2 (hafnium oxide) and Al2O3 process cycles, [0067]) to the dopant metal oxide ((Fig. 1, 160, the second layer of the inter-gate dielectric structure may comprise one of: an aluminum oxide layer and a silicon oxide layer, [0011]) is about 1:1 to about 100:1 (Fig. 1, 150, IGD structure with various high-k IGD single layers or stacks: HfO2, HfAlO, Al2O3, [0101]; IGD structure, the characteristics have a 1:1 relationship as shown by the ISPP and ISPE slopes as shown in Figure 9, [0102]).
Regarding Claim 12, REYES as modified by TSAI teaches the transistor structure of claim 9.
REYES further teaches the transistor structure (Fig. 1, 100, NVM device), wherein the bulk metal oxide comprises ZrO2 (Fig. 1, 155/165, first layer/third layer of the IGD structure, 150 may comprise Ti-O based layer or TiO2, [0099]; it should be noted that substituting (Zr) for (Ti) is a simple substitution of one known element for another to obtain predictable results (See MPEP2143)") and the oxide comprises SiO2 (Fig. 1, 160, the second layer of the inter-gate dielectric structure may comprise one of: an aluminum oxide layer and a silicon oxide layer, [0011]).
Regarding Claim 15, REYES as modified by TSAI teaches the transistor structure of claim 9.
REYES further teaches the transistor structure (Fig. 1, 100, NVM device), wherein the amorphous oxide film (Fig. 1, 150, inter-gate dielectric (IGD) structure; may comprise an amorphous layer, [0011], [0054], [0057]) has a thickness of at least about 200 Å to about 2,000 Å (Fig. 1, 150, three-layer IGD structures, namely, HaH with layer thickness of 10nm/5nm/10nm (or total IGD structure thickness is therefore, 20 nm) [0111-0113]; Note: 1 Å = 0.1 nm).
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over REYES, in view of TSAI as applied to Claim(s) 9-12, and 15 above, and ROCKLEIN as applied to Claim(s) 5-6 above.
Regarding Claim 13, REYES as modified by TSAI teaches the transistor structure of claim 9.
REYES as modified by TSAI does not explicitly disclose the transistor structure, wherein the amorphous oxide film comprises the dopant metal oxide in an amount of at least about 1 mol% to less than about 50 mol%.
ROCKLEIN teaches the transistor structure (Fig. 1, 100, memory cell array coupled to a select device, e.g. access device such as field effect transistor (FET) or bipolar junction transistor, BJT, [0015]), wherein the amorphous oxide film (Fig. 2, 236/238, dielectric region/barrier dielectric region can be (maybe) formed to be amorphous, [0034], [0036]) comprises the dopant metal oxide (SiO2/Al2O3, AlxOy, [0034], [0036]) in an amount of at least about 1 mol% to less than about 50 mol% (Fig. 2, 236, dielectric region, example of metal oxides (MOx) that can be included in the dielectric region, 236 include a near-stoichiometric, stoichiometric, and sub- stoichiometric metal oxide material; a sub- stoichiometric oxide can be an oxide that has an oxygen percentage below a stoichiometric ratio for the oxide, the dielectric region, 236 can include other metal oxides such as a zirconium silicon oxide (ZrxSiyOz), and/or a hafnium silicon oxide (HfxSiyOz), (AlxHfyOz) [0033-0034], [0045]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have REYES as modified by TSAI to incorporate the teachings of ROCKLEIN, such that, the transistor structure, wherein the amorphous oxide film comprises the dopant metal oxide in an amount of at least about 1 mol% to less than about 50 mol%, so that the discrete barrier dielectric materials within the bulk dielectric materials can result in discrete regions of stoichiometric oxides and sub-oxides being created under programming to establish a two-state resistive memory cell that can have a low resistance state and a high resistance state (ROCKLEIN, [0022], [0006]).
Regarding Claim 14, REYES as modified by TSAI teaches the transistor structure of claim 9.
REYES as modified by TSAI does not explicitly disclose the transistor structure, wherein the bulk metal oxide comprises ZrO2, wherein the dopant metal oxide comprises SiO2, and wherein the SiO2 is present in an amount of at least about 9 mol% to less than about 50 mol%.
ROCKLEIN teaches the transistor structure (Fig. 1, 100, memory cell array coupled to a select device, e.g. access device such as field effect transistor (FET) or bipolar junction transistor, BJT, [0015]), wherein the bulk metal oxide comprises ZrO2 ([0034]), wherein the dopant metal oxide comprises SiO2 ([0034], [0036]), and wherein the SiO2 is present in an amount of at least about 9 mol% to less than about 50 mol% (Fig. 2, 236, dielectric region, example of metal oxides (MOx) that can be included in the dielectric region, 236 include a near-stoichiometric, stoichiometric, and sub- stoichiometric metal oxide material; a sub- stoichiometric oxide can be an oxide that has an oxygen percentage below a stoichiometric ratio for the oxide, the dielectric region, 236 can include other metal oxides such as a zirconium silicon oxide (ZrxSiyOz), [0033-0036]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have REYES as modified by TSAI to incorporate the teachings of ROCKLEIN, such that, the transistor structure, wherein the bulk metal oxide comprises ZrO2, wherein the dopant metal oxide comprises SiO2, and wherein the SiO2 is present in an amount of at least about 9 mol% to less than about 50 mol%, so that the discrete barrier dielectric materials within the bulk dielectric materials can result in discrete regions of stoichiometric oxides and sub-oxides being created under programming to establish a two-state resistive memory cell that can have a low resistance state and a high resistance state (ROCKLEIN, [0022], [0006]).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over REYES as applied to Claim(s) 1, 9, and 17 above, in view of LIM, AHN, and NARAYANAN (prior art used in the previous Office Action filed on 01/21/2026).
Regarding Claim 18, REYES teaches the method (Fig. 1, 100, a method of manufacturing a non-volatile (NVM) device, [0018]; Fig. 1, 150, inter-gate dielectric (IGD) structure; may comprise an amorphous layer, [0011], [0054], [0057]) of claim 17.
REYES does not explicitly disclose the method, wherein: performing each of the one or more first ALD deposition cycles comprises: contacting a surface with at least one of a Zr precursor or an Hf precursor in a first half reaction; and contacting the surface with a first oxygen reactant in a second half reaction to form the bulk metal oxide layer; and performing each of the one or more second ALD deposition cycles comprises: contacting the surface with at least one of a Si precursor, an Al precursor or an N precursor in a third half reaction; and contacting the surface with the first oxygen reactant or a second oxygen reactant in a fourth half reaction to form the dopant metal oxide layer.
LIM teaches the method (Figs. 1/4, flow chart of forming a gate dielectric layer, thin film transistor using gate dielectric layer; NMOS for a thin film transistor (TFT), [0016-0017], [0024], [0027], [0039]), wherein:
performing each of the one or more first ALD deposition cycles (Figs. 1-2, 3, ALD oxide layer, [0031-0035], [0039]); (Fig. 1, at operation S20, a plasma oxide layer is formed using oxygen plasma; at operation S30, an ALD oxide (SiO2) layer or a high dielectric layer is deposited by a plasma-enhanced ALD or PEALD process; [0031]) comprises:
contacting a surface with at least one of a Zr precursor or an Hf precursor in a first half reaction (Fig. 1, [0014], [0019]); and
contacting the surface with a first oxygen reactant in a second half reaction (Fig. 1, oxygen plasma, [0031-0040]) to form the bulk metal oxide layer (Figs. 1-2, 4, high dielectric layer, [0031-0035], [0039]); and
performing each of the one or more second ALD deposition cycles (Figs. 1-2, 3, ALD oxide layer, [0031-0035], [0039]); (Fig. 1, at operation S20, a plasma oxide layer is formed using oxygen plasma; at operation S30, an ALD oxide (SiO2) layer or a high dielectric layer is deposited by a plasma-enhanced ALD or PEALD process; [0031]) comprises:
contacting the surface with at least one of a Si precursor, an Al precursor or an N precursor in a third half reaction (Fig. 1, [0019], [0031]); and
contacting the surface with the first oxygen reactant or a second oxygen reactant in a fourth half reaction (Fig. 1, oxygen plasma, [0031-0040]) to form the dopant metal oxide layer (Figs. 1-2, 3, ALD oxide layer, [0031-0035], [0039]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified REYES to incorporate the teachings of LIM, such that the method, wherein: performing each of the one or more first ALD deposition cycles comprises: contacting a surface with at least one of a Zr precursor or an Hf precursor in a first half reaction; and contacting the surface with a first oxygen reactant in a second half reaction to form the bulk metal oxide layer; and performing each of the one or more second ALD deposition cycles comprises: contacting the surface with at least one of a Si precursor, an Al precursor or an N precursor in a third half reaction; and contacting the surface with the first oxygen reactant or a second oxygen reactant in a fourth half reaction to form the dopant metal oxide layer. The above mentioned steps are indeed specific to the method for forming a gate dielectric layer, in which the gate dielectric layer is formed by finely forming a plasma and depositing an atomic layer deposition (ALD) oxide layer, thereby enhancing interfacial characteristics and decreasing current leakage (LIM, [0002]).
Though LIM teaches the ALD deposition cycles using silicate layer formed by combination of SiO2 and at least one of HfO2, ZrO2 etc, [0019], REYES as modified by LIM does not explicitly disclose the method wherein performing each of the one or more first ALD deposition cycles comprises: contacting a surface with at least one of a Zr precursor or an Hf precursor in a first half reaction; and contacting the surface with a first oxygen reactant in a second half reaction.
AHN teaches the method (Fig. 2A, atomic layer deposition system for processing a layer, [0015]) wherein:
performing each of the one or more first ALD deposition cycles (Fig. 4, flow diagram of a method to process a nanolaminate of HfO2/ZrO2 by atomic layer deposition, step 430, hafnium cycles performed, [0076]; step 455, zirconium cycles, [0084]; [0017-0018]) comprises:
contacting a surface with at least one of a Zr precursor or an Hf precursor in a first half reaction (Fig. 4, 410, pulse precursor containing hafnium, HfO2 using HfI4 precursor; 435, pulse precursor containing zirconium, ZrI4 or ZrCl4, [0042], [0072], [0077]); and
contacting the surface with a first oxygen reactant in a second half reaction (Fig. 4, 420, pulse first oxygen containing precursor, vapor solution H2O-H2O2 can be used as the oxygen containing precursor, [0073]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have REYES as modified by LIM to incorporate the teachings of AHN, such that the method wherein performing each of the one or more first ALD deposition cycles comprises: contacting a surface with at least one of a Zr precursor or an Hf precursor in a first half reaction; and contacting the surface with a first oxygen reactant in a second half reaction, so that to produce HfO2/ZrO2 nanolaminates processed in relatively low temperatures can provide amorphous dielectric films having relatively low leakage current for use as dielectric layers in electronic devices and systems (AHN, Fig. 4, [0128]).
REYES as modified by LIM and AHN does not explicitly disclose the method wherein each of the one or more second ALD deposition cycles comprises: contacting the surface with at least one of a Si precursor, an Al precursor or an N precursor in a third half reaction; and contacting the surface with the first oxygen reactant or a second oxygen reactant in a fourth half reaction.
NARAYANAN teaches the method (Fig. 1, method for forming a semiconductor device, [0007]) wherein:
performing each of the one or more second ALD deposition cycles (Figs. 1 and 8, flow charts illustrating the first and last method of a gate forming with metal oxide or binary metal oxide layers using atomic layer deposition chamber (ALD), [0034]) comprises:
contacting the surface with at least one of a Si precursor, an Al precursor or an N precursor in a third half reaction (Fig. 1, step 10, aluminum containing gas precursor and/or nitrogen plasma and/or a hydrogen plasma, [0038], [0061]); and
contacting the surface with the first oxygen reactant or a second oxygen reactant in a fourth half reaction (Fig. 1, oxygen containing atmosphere exposure, [0028], [0034]). [Note: It should also be noted that substituting (oxygen containing plasma) for (nitrogen containing plasma) in formation of binary metal oxide interlayer, TiAlON, in the prior-art, is a simple substitution of one known element for another to obtain predictable results (See MPEP2143)"].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have REYES modified by LIM and AHN to incorporate the teachings of NARAYANAN, such that the method wherein: performing each of the one or more second ALD deposition cycles comprises: contacting the surface with at least one of a Si precursor, an Al precursor or an N precursor in a third half reaction; and contacting the surface with the first oxygen reactant or a second oxygen reactant in a fourth half reaction, to produce binary metal oxide, (TiAlON) layer having appropriate thickness with high quality, further deposited on high k dielectric HfO2 layer, and thus can obtain a capacitance equivalent thickness (CET) as low as 10 Å, with low leakage small hysteresis and good interface quality (NARAYANAN, [0027], [0063]).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over REYES in view of LIM, AHN, and NARAYANAN as applied to Claim(s) 1, 9, and 17 above, and further in view of MACHIDA (prior art used in the previous Office Action filed on 01/21/2026).
Regarding Claim 19, REYES as modified by LIM, AHN, and NARAYANAN teaches the method of claim 18.
REYES as modified by LIM, AHN, and NARAYANAN does not explicitly disclose the method, wherein: the Zr precursor is used for the first half reaction, wherein the Si precursor is used for the second half reaction, and wherein the first oxygen reactant and the second oxygen reactant are independently selected from a group consisting of water (H2O), ozone (O3), oxygen (O2) hydrogen peroxide (H2O2) and oxygen radical (O-).
MACHIDA teaches the method (Fig. 1, method for forming a gate oxide film, [0001]), wherein: the Zr precursor is used for the first half reaction (Zr alkoxide compounds, Zr β-diketonate compounds, Zr alkylamide compounds, [0025], [0040]), wherein the Si precursor is used for the second half reaction (silicon-based compound, [0014], [0045]), and wherein the first oxygen reactant and the second oxygen reactant are independently selected from a group consisting of water (H2O), ozone (O3), oxygen (O2) hydrogen peroxide (H2O2) and oxygen radical (O-) (oxidizing atmosphere selected from the group consisting of oxygen, nitrous oxide, ozone, water and hydrogen peroxide, [0017]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have REYES as modified by LIM, AHN, and NARAYANAN to incorporate the teachings of MACHIDA, such that the method, wherein: the Zr precursor is used for the first half reaction, wherein the Si precursor is used for the second half reaction, and wherein the first oxygen reactant and the second oxygen reactant are independently selected from a group consisting of water (H2O), ozone (O3), oxygen (O2) hydrogen peroxide (H2O2) and oxygen radical (O-), so that to produce the gate oxide film interface with the silicon layer must be stable and also the dielectric constant must be high with thickness as thin as 10 nm or less for miniaturization in order to improve the signal processing speed, in particular, the distance between the source and rain becoming shorter (MACHIDA, [0001-0006]).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over REYES in view of LIM, AHN, and NARAYANAN as applied to Claim(s) 1, 9, and 17 above, and further in view of Yuia Zhai et al, (hereinafter ZHAI), US 20190206691 A1 (prior art used in the previous Office Action filed on 01/21/2026).
Regarding Claim 20, REYES as modified by LIM, AHN, and NARAYANAN method of claim 18.
LIM further teaches the method (Figs. 1/4, flow chart of forming a gate dielectric layer, thin film transistor using gate dielectric layer; NMOS for a thin film transistor (TFT), [0016-0017], [0024], [0027], [0039]) of claim 18, wherein:
performing the plasma-enhanced ALD (Figs. 1-2, 3, ALD oxide layer, [0031-0035], [0039]); (Fig. 1, at operation S20, a plasma oxide layer is formed using oxygen plasma; at operation S30, an ALD oxide (SiO2) layer or a high dielectric layer is deposited by a plasma-enhanced ALD or PEALD process; [0031]) further comprises:
performing one or more third deposition cycles to deposit an adhesion metal oxide layer on the surface before performing the one or more ALD deposition super-cycles (Figs. 1-2, 3, ALD oxide layer, [0031-0035], [0039]); (Fig. 1, at operation S20, a plasma oxide layer is formed using oxygen plasma; at operation S30, an ALD oxide (SiO2) layer or a high dielectric layer is deposited by a plasma-enhanced ALD or PEALD process; [0031]), wherein the adhesion metal oxide layer comprises one or more of SiO2, A12O3, HfO2, SiCON, SiC or combinations thereof (Fig. 1, [0019], [0031]).
Though LIM teaches the deposition cycle via ALD process, REYES as modified by LIM, AHN, and NARAYANAN does not explicitly disclose the method wherein: performing one or more third deposition cycles to deposit an adhesion metal oxide layer on the surface before performing the one or more ALD deposition super-cycles, wherein the adhesion metal oxide layer comprises one or more of SiO2, A12O3, HfO2, SiCON, SiC or combinations thereof.
ZHAI teaches the method (Fig. 1, cross-sectional view of a processing chamber that may be used to deposit a gate insulating layer, [0009]) wherein: performing one or more third deposition cycles to deposit an adhesion metal oxide layer (Fig. 2, 210A, the interface layer, [0025]) on the surface (Fig. 2, 204, channel layer) before performing the one or more ALD deposition super-cycles (Fig. 1, PECVD, [0015]) wherein the adhesion metal oxide layer (Fig. 2, the interface layer, 210A has a good interface between both the channel layer, 204 and the high-k dielectric layer, 210B thereby improving adhesion, [0027]) comprises one or more of SiO2, A12O3, HfO2, SiCON, SiC or combinations thereof (Fig. 2, SiO2, Al2O3, TiO2, [0025]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have REYES as modified by LIM, AHN, and NARAYANAN to incorporate the teachings of ZHAI, such that the method wherein: performing one or more third deposition cycles to deposit an adhesion metal oxide layer on the surface before performing the one or more ALD deposition super-cycles, wherein the adhesion metal oxide layer comprises one or more of SiO2, A12O3, HfO2, SiCON, SiC or combinations thereof, so that the silicon containing interface layer improves adhesion and interaction between the active channel layer and the metal gate with the high-k dielectric value of the gate layer enables for a faster driving current that improves brightness and performance of the display device (ZHAI, [0032]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20180366547 A1 – Figure 3A, [0046-0047]
STATEMENT OF RELEVANCE – The paraelectric material can be hafnium silicon oxide doped with a dielectric material, the dielectric material being selected from a group of HfO2, ZrO2. The ferroelectric material can be HfO2, ZrO2 and further include an amount of dopants, from a group of Si, Al with the concentration of dopants ranges from 2% to 10%.
US 6617639 A1 – Figure 6
STATEMENT OF RELEVANCE – The cross-sectional view after depositing the top dielectric material layer (36). The top dielectric material layer, 36 includes a composite dielectric material comprising elements of at least two high-K dielectric materials, which replaces the silicon dioxide layer of a conventional ONO structure.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARLON T FLETCHER can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
Prosecution Insights