DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement(s) (IDS) submitted on 10/20/2023 and 06/10/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner. Claim Status The second claim set filed 10/20/2023 has been considered by Examiner. Claims 1, 3-7, and 9-14 are currently amended; Claims 1-15 have been fully considered in Examination. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness . This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim s 1-2 and 4-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo (U.S. PG Pub No U S 2019 / 0229149A1 ) in view of Yeh (U.S. PG Pub No US2017 /0 104128A1 ). Regarding claim 1, Yoo teaches a method [see fig. 2, 0012] for forming a matrix ( 187, at least 3 x3 matrix shown ) fig. 2 [0013] of light-emitting diode, LED, elements ( blue, red, green LED-subpixels ) fig. 2-223 [0018] of different colours (R, G, B) [0018] , comprising: epitaxially growing a first layer (n- GaN , MQW-B, p- GaN ; in blue s-pix site [0015]) fig. 2-201 [0015, 0032-0034] on (supported by left sidewall of) a GaN sacrificial layer ( middle -right p- GaN ) fig. 2-201 [0015] , the first layer (n- GaN , MQW-B, p- GaN ; in blue s-pix site [0015]) fig. 2-201 [0015, 0032-0034] comprising a stacked structure of a first n-doped GaN layer ( left n- GaN ) fig. 2-201 [0015] , a first p-doped GaN layer ( left p- GaN ) fig. 2-201 [0015] , and a first InxGa (1-x)N layer ( left MQW-B ) fig. 2-201 [0015] arranged (vertically) therebetween, wherein x lies within the range of 0.10- 0.75 (for blue pixel MQW-B, x ~ 0.15-0.20 [0034]) ; patterning the first layer (removing excessive MQW-B material) [0016-0017] to form a first array (column) (implemented in plurality 187/189) fig. 2 [0013] of first LED elements (n- GaN , MQW-B, p- GaN ; in blue s-pix site [0015]) fig. 2-223 [0015, 0032-0034] arranged to emit light of a first colour (blue) ; forming a first etch mask ( second passivation layer) fig. 2-203 [0016] protecting the first array (blue-LED’s) and comprising a plurality of first trenches ( middle trench) [0016] (implemented in 3x3 plurality 187) fig. 2 [0013] exposing the sacrificial layer (right p- GaN ) fig. 2-207 [0016] ; epitaxially growing a second array of second LED elements (n- GaN , MQW-G, p- GaN ; in green s-pix site [0016]) fig. 2-209 [0016, 0032-0034] in the plurality of first trenches (middle trench) [0016] , wherein the second LED elements (comprising green MQW-G) are arranged to emit light of a second colour (green) and comprise a stacked structure of a second n-doped GaN layer ( middle n- GaN ) [0016] , a second p-doped GaN layer ( middle p- GaN [0016] ), and a second InyGa (1-y)N layer (left MQW-B) fig. 2-209 [0016] arranged therebetween, wherein y lies within the range of 0.20-0.28 (for green pixel MQW-G, y ~ 0.20-0.25 [0034]) ; forming a second etch mask (third passivation layer) fig. 2-211 [0016] protecting the second array (green pixels) and comprising a plurality of second trenches ( right trenches) [0017] exposing the (right sidewall of) sacrificial layer (middle-right p- GaN ) fig. 2-213 [0016-0017] ; and epitaxially growing a third array of third LED elements (n- GaN , MQW-R, p- GaN ; in red s-pix site [0016]) fig. 2-217 [0017, 0032-0034] in the plurality of second trenches (right trench) , wherein the third LED elements (n- GaN , MQW-R, p- GaN ; in red s-pix site [0016]) fig. 2-217 [0017, 0032-0034] are arranged to emit light of a third colour (red) and comprise a stacked structure of a third n-doped GaN layer ( right n- GaN ) [0017] , a third p-doped GaN layer ( right p- GaN ) [0017] , and a third InzGa (1-z)N layer ( right MQW-R [0017]) arranged therebetween, wherein the first (B-LED- sub_pixels ) , second (G-LED- sub_pixels ) and third arrays (R-LED- sub_pixels ) (implemented in 3x3 plurality 187) fig. 2 [0013] form the matrix (implemented in 3x3 matrix 187) fig. 2 [0013] . However, Yoo does not explicitly disclose wherein z (for a third InzGa (1- z)N layer used in red LED [0017, 0032-0034]) lies within the range of 0.28-0.33 (concentration not specified). Yeh teaches a method [see title] wherein z (for InzGa (1- z)N layer (4) fig. 1 [0033] used in red LED [0033]) lies within the range of 0.28-0.33 (may be greater than about 30% [0033], i.e , z ~ 0.31 for red MQW [0033]). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Yoo such that the InGaN MQW layer intended for red light emission [0033] to comprise indium in a relative concentration on the order of about 30% indium [0033] in order to ensure fully-functional red output [0033-0034] with high spectral purity and output power [0034], as taught by Yeh . Regarding claim 2, Yoo teaches the method [see fig. 2, 0012] of claim 1. Yoo also teaches wherein the first InxGa (1- x)N layer (MQW-B) fig. 2-223 [0016, 0034] [0018] has a thickness of 0.5-3 nm (2nm [0034]), the second InyGa (1-y)N layer (MQW-G) fig. 2-223 [0016, 0034] has a thickness of 2-3 nm (2nm [0034]). However, Yoo does not explicitly disclose and the third InzGa (1- z)N layer (MQW-R) fig. 2-223 [0017, 0034] has a thickness of 2.8-3.5 nm (thickness for MQW-R not specified). Yeh teaches a method [see title] wherein the third InzGa (1- z)N layer (for InzGa (1-z)N layer (4) fig. 1 [0033] used in red LED [0033]) has a thickness of 2.8-3.5 nm (each MQW-Red may be about 3nm thick [0033]). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Yoo such that the InGaN MQW layer intended for red light emission [0033] to have a thickness on the order of a few nm [0033] in order to, along with other features, ensure fully-functional red output [0033-0034] with high spectral purity and output power [0034], as taught by Yeh . Regarding claim 4, Yoo teaches the method [see fig. 2, 0012] of claim 1. Yoo also teaches wherein the GaN sacrificial layer (middle-right p- GaN ) fig. 2-201 [0015] is p-doped [0015-0016]. Regarding claim 5, Yoo teaches the method [see fig. 2, 0012] of claim 1. Yoo also teaches wherein the matrix is configured to form a plurality of pixels (implemented in 3x3 plurality 187) fig. 2 [0013] for a display device [0009-0012], and wherein each pixel (R, G, B) is formed of at least one of the first LED elements (B) and a plurality of the second (G) and third ® LED elements (respectively comprising blue, green, red light emitting sub-pixel-areas) fig. 2-223 [0018]. Regarding claim 6, Yoo teaches the method [see fig. 2, 0012] of claim 1. Yoo also teaches wherein the first colour (B) is blue [0015-0018], the second colour (G) is green [0016-0018] and the third colour (R) is red [0017-0018] Regarding claim 7, Yoo teaches the method [see fig. 2, 0012] of claim 1. Yoo also teaches further comprising forming AlGaN barrier layers (buffer-BG’s) fig. 2-223 [0019] (buffer-BG = AlGaN / GaN bilayer [0019]) abutting opposite sides (left/right sidewalls) of at least one of the first InxGa (1- x)N layer (MQW-B) fig. 2-223 [0016, 0019] and the second InyGa (1-y)N layer (MQW-G) fig. 2-223 [0016, 0019]. Regarding claim 8, Yoo teaches the method [see fig. 2, 0012] of claim 7. Yoo also teaches further comprising forming an undoped GaN layer (buffer-BG = AlGaN / GaN bilayer [0019]) fig. 2-223 [0019] abutting at least one of the AlGaN barrier layers ( AlGaN / GaN bilayer mutually-abutting each other presumably undoped [0019]). Regarding claim 9, Yoo teaches the method [see fig. 2, 0012] of claim 1. Yoo also teaches wherein the first etch mask (second passivation layer) fig. 2-203 [0016] and the second etch mask (third passivation layer) fig. 2-211 [0016] are hardmasks (of SiN [0014-0015]). Regarding claim 10, Yoo teaches the method [see fig. 2, 0012] of claim 1. Yoo also teaches wherein the second etch mask (third passivation layer) fig. 2-211 [0016] is formed by covering the second array of second LED elements (comprising middle MQW-G) fig. 2-211[0016] with a mask material (third passivation layer) fig. 2-211 [0016] ( SiN ) [0014-0015] and forming the plurality of second trenches (middle trench) fig. 2-207 [0016] in the layer forming the first etch mask (second passivation layer) fig. 2-203 [0016]. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yoo (U.S. PG Pub No U S 2019 / 0229149A1 ) in view of Oohata (U.S. PG Pub No US200 3/ 0 160258 A1 ). Regarding claim 3, Yoo teaches the method [see fig. 2, 0012] of claim 1. Yoo also teaches wherein a maximum lateral width of each of the first LED elements (comprising MQW-B) fig. 2-223 [0016, 0034] [0018] lies within the range of 0.1-25 microns (sub-pixel may be 1-12 microns in width [0009]). However, Yoo does not explicitly disclose wherein a maximum lateral width of each of the second LED elements (comprising MQW-G) fig. 2-223 [0016, 0034] [0018] lies within the range of 2-3 nm, and/or wherein a maximum lateral width of each of the third LED elements (MQW-R) fig. 2-223 [0016, 0034] [0018] lies within the range of 2.8-3.5 nm. Oohata teaches a method [see title ] wherein a maximum lateral width of each of the third LED elements ( maximum width taken near uppermost level of 2) fig. 5 [0061] lies within the range of 2.8-3.5 nm ( width of InGaN layer 2 varies from microns [0064, 0066] to less than one nm / atom-wide at upper tip; maximum lateral width at a given level therebetween necessarily is about 3nm to the closest atomic-width). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Yoo such that gallium-nitride materials of the LED are slanted so as to produce an upper corner of atomic-width [0060-0061] in order to reduce crystal defects [0061] so that internal light emission efficiency is higher [0061] and luminance is enhanced [0061], as taught by Oohata . Claim s 1 1-1 2 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo (U.S. PG Pub No U S 2019 / 0229149A1 ) modified by Yeh (U.S. PG Pub No US2017 /0 104128A1 ) , as applied in claim 1 above, and further in view of Pezeshki (U.S. PG Pub No US2021 / 0208337A1 ). Regarding claim 1 1 , Yoo teaches the method [see fig. 2, 0012] of claim 1. Yoo also teaches wherein the GaN sacrificial layer ( middle-right p- GaN ) fig. 2-201 [0015] is arranged on a substrate ( (111) substrate) [0019] comprising a layer comprising a plurality of AIN pillars ( isolation sidewalls 184/185) fig. 2-183 [0013] , and wherein the plurality of pillars (184/185) are (partially) embedded by the material of the GaN sacrificial layer ( middle-right p- GaN ) fig. 2-201 [0015] . However, Yoo does not explicitly disclose comprising a plurality of AIN pillars (141) (SiO2 instead [0013]). Pezeshki teaches a method [see title] comprising a plurality of AIN pillars (passivation coating (not shown) around pillars could be AlN instead of SiO2 [0042]). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Yoo such that the pillars between the conductive LED layers of Yoo are formed, at least in part, by AlN instead of SiO2 [0042] because of the material’s suitable dielectric passivation properties [0042] as well as favorabel opical properties [0042], as taught by Pezeshki . Regarding claim 12, Yoo teaches the method [see fig. 2, 0012] of claim 11. Yoo also teaches further comprising: forming a plurality of third trenches ( left trenches hosting MQW-B) fig. 2-201 [0016] between at least some of the first (left) , second (middle) and third (right) LED elements (between first and second and first and third LED elements), the plurality of third trenches (left trenches between 184/185 pillars) extending down to the layer comprising the plurality of pillars (184/185) ; selectively removing at least some of the material of the GaN sacrificial layer (middle-p-type GaN removed) fig. 2 207 [0016] between the plurality of pillars (left/right 184/185 SiO2 pillars) [0013, 0015] . Claim s 1 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yoo (U.S. PG Pub No U S 2019 / 0229149A1 ) modified by Yeh (U.S. PG Pub No US2017 /0 104128A1 ) and Pezeshki (U.S. PG Pub No US2021 / 0208337A1 ) , as applied in claim 11 above, and further in view of Yu (U.S PG Pub No US2012 / 0256187A1 ) . Regarding claim 13, Yoo teaches the method [see fig. 2, 0012] of claim 12. However, Yoo does not explicitly disclose bonding the first (B-LED- sub_pixels ), second (G-LED- sub_pixels ) and third (R-LED- sub_pixels ) LED elements [see fig. 2-223] to a carrier substrate; followed by: r eleasing the first (B-LED- sub_pixels ), second (G-LED- sub_pixels ) and third (R-LED- sub_pixels ) LED elements [see fig. 2-223] elements from the substrate ((111) substrate)) by removing the plurality of pillars (left/right 184/185 SiO2 pillars) [0013, 0015] . Yu teaches a method [see title, 0033] comprising bonding the first, second and third LED elements (plurality of LED elements 124a-b) fig. 12 [0033] to a carrier substrate (150) fig. 13 [0033]; followed by: releasing the first, second a nd third LED elements (plurality of LED elements 124a-b) from the substrate (102) fig. 12 [0032] by removing the plurality of pillars (partially-removing pillar shaped portions of 126 from each other [0020, figs. 13-14]). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Yoo such that the light emitting elements are further processed by use of a carrier substrate [0032-0033] in order to facilitate further selective processing and transfer [0039] into a larger array [0049], reducing manufacturing costs and improving LED assembly quality [0049], as taught by Yu . Claim s 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo (U.S. PG Pub No U S 2019 / 0229149A1 ) in view of Yeh (U.S. PG Pub No US2017 /0 104128A1 ) , as applied in claim 1 above, and further in view of Strassburg (U.S. PG Pub No US2014 /0 353581A1 ). Regarding claim 14, Yoo teaches the method [see fig. 2, 0012] of claim 1. However, Yoo does not explicitly disclose further comprising: forming a fourth LED element below at least one of the first (B-LED- sub_pixels ), second (G-LED- sub_pixels ) and third (R-LED- sub_pixels ) LED elements [see fig. 2-223] , wherein the fourth LED element comprises a fourth IndGa (1-d)N layer (212) for optically pumping said first InxGa (1-x)N, second InyGa (1-y)N or third InzGa (1-z)N layer [0016-0017, 0032-0034] . Strassburg teaches a method [see title, 0055] further comprising: forming a fourth LED element (a first individual column l) fig. 1 [0057] (partially) below at least one of the first (a second individual column spanning l) [0057] , second (a third individual column spanning l) [0057] and third (a fourth individual column spanning l) [0057] , wherein the fourth LED element comprises a fourth IndGa (1-d)N layer (a first column comprising a first 6-layer) fig. 1 [0041-0045] for optically pumping (enabling collective optical pumping of) said first InxGa (1-x)N, second InyGa (1-y)N or third InzGa (1-z)N layer (lower layer 21 enables optical pumping of upper LED structures shown in fig. 1 [0062-0064]). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Yoo such that the LED elements are implemented as the stacked columns of Strassburg [0041-0045, 0057] in order to enable optical pumping [0064] that enhances light generation of the display system comprising a plurality of LED elements [0046], as taught by Strasburg . Regarding claim 15, Yoo teaches the method [see fig. 2, 0012] of claim 14. Y oo in view of Strassburg also teaches wherein the indium composition d is less than 0.05 (may comprise a n+ layer with indium content of about 3% [0043]) and the fourth IndGa (1- d)N layer (a first column comprising a first 6-layer) fig. 1 [0041-0045] has a thickness of 1-6 n m (individual spacer layer may be about 2-5 nm [0045]). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. All references made available on the PTO-892 form are considered relevant to the present disclosure because they all feature LED’s with most of the claimed layers. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT SEAN AYERS WINTERS whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-3308 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday - Friday 10:30 am - 7:00 pm (EST) . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT N. Drew Richards can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571) 272-1736 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SEAN AYERS WINTERS/ Examiner, Art Unit 2892 12/0 8/2025 /ERIC W JONES/ Primary Examiner, Art Unit 2892