DETAILED ACTION
This Action is responsive to the Restriction /Election Response filed on 07/07/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election of Group II (drawn to a manufacturing method of a display device), Species 4 (e.g., reading on FIG. 3D), and Sub-Species A1 (e.g., reading on FIG. 3E) in the reply filed on 07/07/2026 is acknowledged and entered into the record. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-11 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Ito (JP 2008/098106A), in view of Kim (US 2022/0293640), in view of Malinowski et al (“Photolithographic Patterning of Organic Photodetectors with a Non-Fluorinated Photoresist System”).
Regarding claim 8, Ito (see, e.g., FIG. 1(a) to FIG. 1(i)) discloses a manufacturing method of a display device, comprising the steps of:
forming a first electrode 2 (left) (Para 0030);
forming an insulator 3 comprising a first opening portion e.g., opening in insulator 3 above electrode layer 2 (left) and a second opening portion e.g., opening in insulator 3 above electrode layer 2 (right) (Para 0030);
forming, by a wet process e.g., spin coating method of a coating solution, a first material layer 6 (4, 5), portion in opening and on insulator 3 above electrode layer 2 (left) (see FIG. 1a) comprising an organic compound e.g., dye-based luminescent: cyclopentamine derivatives in the first opening portion e.g., opening in insulator 3 above electrode layer 2 (left) (see FIG. 1a) and a second material layer 6 (4, 5), portion in opening and on insulator 3 above electrode layer 2 (right) (see FIG. 1a) comprising an organic compound e.g., dye-based luminescent: cyclopentamine derivatives in the second opening portion e.g., opening in insulator 3 above electrode layer 2 (right) (see FIG. 1a) (Para 0030, Para 0045-Para 0050, Para 0054-Para 0055, Para 0061-Para 0064);
selectively forming a first resist mask 8’ (left) (see FIG. 1e) and a second resist mask 8’ (right) (see FIG. 1e) over the first material layer 6 (4, 5), portion in opening and on insulator 3 above electrode layer 2 (left) (see FIG. 1e) and the second material layer 6 (4, 5), portion in opening and on insulator 3 above electrode layer 2 (right) (see FIG. 1e), respectively (Para 0099); and
processing e.g., etching the first material layer 6 (4, 5), portion in opening and on insulator 3 above electrode layer 2 (left) using the first resist mask 8’ (left) (see FIG. 1f) to form a third material layer 5’ (left) (see FIG. 1f), and processing the second material layer 6 (4, 5), portion in opening and on insulator 3 above electrode layer 2 (right) using the second resist mask 8’ (right) (see FIG. 1f) to form a fourth material layer 5’ (right) (see FIG. 1f) (Para 0104-Para 0105),
wherein:
the first opening portion e.g., opening in insulator 3 above electrode layer 2 (left) overlaps with the first electrode 2 (left),
the first light-emitting element 2 (left), 4’ (left), 5’ (left), 9 (left) (see FIG. 1i) includes the third material layer 5’ (left) (Para 0030, Para 0104-Para 0105, Para 0115, Para 0265), and
a second light-emitting element 2 (right), 4’ (right), 5’ (right), 9 (right) (see FIG. 1i) includes the fourth material layer 5’ (right) (Para 0030, Para 0104-Para 0105, Para 0115, Para 0265),
Although Ito shows substantial features of the claimed invention, Ito fails to expressly teach forming, over a substrate, a first transistor comprising silicon in a channel formation region and a second transistor comprising an oxide semiconductor in a channel formation region; forming a first electrode of a first light-emitting element electrically connected to the first transistor; processing the first material so as not to overlap with a top surface of the insulator; and processing the second material layer so as not to overlap with a top surface of the insulator.
Kim (see, e.g., FIG. 4), on the other hand, teaches forming, over a substrate 101, a first transistor e.g., silicon transistor in AR1 region comprising silicon e.g., polycrystalline silicon in a channel formation region 105 and a second transistor e.g., oxide semiconductor transistor in AR2 region comprising an oxide semiconductor e.g., gallium indium zinc oxide GIZO) in a channel formation region 135 (Para 0078, Para 0079, Para 0086, Para 0098, Para 0120); forming a first electrode ANO of a first light-emitting element CAT, EL, ANO electrically connected to the first transistor e.g., silicon transistor in AR1 region for the purpose of providing a driving transistor and a compensation transistor for the display (Para 0078, Para 0079, Para 0086, Para 0098, Para 0120).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a first transistor comprising silicon in a channel formation region and a second transistor comprising an oxide semiconductor in a channel formation region as described by Huang to the device of Ito for the purpose of providing a driving transistor and a compensation transistor for the display (Para 0078).
Ito fails to expressly teach processing the first material so as not to overlap with a top surface of the insulator; and processing the second material layer so as not to overlap with a top surface of the insulator. Malinowski (see, e.g., FIG. 1d) does, on the other hand, disclose processing e.g., by patterning with photolithography using a photoresist an active layer e.g., P3HT:PCBM so as not to overlap with a top surface of the insulator e.g., interlayer (pg 2, col. 1, para 2; pg 2, col. 2, para 1). However, differences in width of active layer will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such difference is critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. See In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph) of the processing the first material so as not to overlap with a top surface of the insulator; and processing the second material layer so as not to overlap with a top surface of the insulator, it would have been obvious to one of ordinary skill in the art to modify the processing of the first material so as not to overlap with a top surface of the insulator; and modify the processing of the second material layer so as not to overlap with a top surface of the insulator of Ito as taught by Malinowski through routine experimentation.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed processing the first material so as not to overlap with a top surface of the insulator; and processing the second material layer so as not to overlap with a top surface of the insulator or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 9, Ito (see, e.g., FIG. 1(a) to FIG. 1(i)) discloses a manufacturing method of a display device, comprising the steps of:
forming a first electrode 2 (left) (Para 0030);
forming an insulator 3 comprising a first opening portion e.g., opening in insulator 3 above electrode layer 2 (left) and a second opening portion e.g., opening in insulator 3 above electrode layer 2 (right) (Para 0030);
forming, by a wet process e.g., spin coating method of a coating solution, a first material layer 6 (4, 5), portion in opening and on insulator 3 above electrode layer 2 (left) (see FIG. 1a) comprising a light emitting material e.g., dye-based luminescent: cyclopentamine derivatives in the first opening portion e.g., opening in insulator 3 above electrode layer 2 (left) (see FIG. 1a) and a second material layer 6 (4, 5), portion in opening and on insulator 3 above electrode layer 2 (right) (see FIG. 1a) comprising a light emitting material e.g., dye-based luminescent: cyclopentamine derivatives in the second opening portion e.g., opening in insulator 3 above electrode layer 2 (right) (see FIG. 1a) (Para 0030, Para 0045-Para 0050, Para 0054-Para 0055, Para 0061-Para 0064);
selectively forming a first resist mask 8’ (left) (see FIG. 1e) and a second resist mask 8’ (right) (see FIG. 1e) over the first material layer 6 (4, 5), portion in opening and on insulator 3 above electrode layer 2 (left) (see FIG. 1e) and the second material layer 6 (4, 5), portion in opening and on insulator 3 above electrode layer 2 (right) (see FIG. 1e), respectively (Para 0099); and
processing e.g., etching the first material layer 6 (4, 5), portion in opening and on insulator 3 above electrode layer 2 (left) using the first resist mask 8’ (left) (see FIG. 1f) to form a third material layer 5’ (left) (see FIG. 1f), and processing the second material layer 6 (4, 5), portion in opening and on insulator 3 above electrode layer 2 (right) using the second resist mask 8’ (right) (see FIG. 1f) to form a fourth material layer 5’ (right) (see FIG. 1f) (Para 0104-Para 0105),
wherein:
the first opening portion e.g., opening in insulator 3 above electrode layer 2 (left) overlaps with the first electrode 2 (left),
the first light-emitting element 2 (left), 4’ (left), 5’ (left), 9 (left) (see FIG. 1i) includes the third material layer 5’ (left) (Para 0030, Para 0104-Para 0105, Para 0115, Para 0265), and
a second light-emitting element 2 (right), 4’ (right), 5’ (right), 9 (right) (see FIG. 1i) includes the fourth material layer 5’ (right) (Para 0030, Para 0104-Para 0105, Para 0115, Para 0265),
Although Ito shows substantial features of the claimed invention, Ito fails to expressly teach forming, over a substrate, a first transistor comprising silicon in a channel formation region and a second transistor comprising an oxide semiconductor in a channel formation region; forming a first electrode of a first light-emitting element electrically connected to the first transistor; processing the first material so as not to overlap with a top surface of the insulator; and processing the second material layer so as not to overlap with a top surface of the insulator.
Kim (see, e.g., FIG. 4), on the other hand, teaches forming, over a substrate 101, a first transistor e.g., silicon transistor in AR1 region comprising silicon e.g., polycrystalline silicon in a channel formation region 105 and a second transistor e.g., oxide semiconductor transistor in AR2 region comprising an oxide semiconductor e.g., gallium indium zinc oxide GIZO) in a channel formation region 135 (Para 0078, Para 0079, Para 0086, Para 0098, Para 0120); forming a first electrode ANO of a first light-emitting element CAT, EL, ANO electrically connected to the first transistor e.g., silicon transistor in AR1 region for the purpose of providing a driving transistor and a compensation transistor for the display (Para 0078, Para 0079, Para 0086, Para 0098, Para 0120).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a first transistor comprising silicon in a channel formation region and a second transistor comprising an oxide semiconductor in a channel formation region as described by Huang to the device of Ito for the purpose of providing a driving transistor and a compensation transistor for the display (Para 0078).
Ito fails to expressly teach processing the first material so as not to overlap with a top surface of the insulator; and processing the second material layer so as not to overlap with a top surface of the insulator. Malinowski (see, e.g., FIG. 1d) does, on the other hand, disclose processing e.g., by patterning with photolithography using a photoresist an active layer e.g., P3HT:PCBM so as not to overlap with a top surface of the insulator e.g., interlayer (pg 2, col. 1, para 2; pg 2, col. 2, para 1). However, differences in width of active layer will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such difference is critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. See In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph) of the processing the first material so as not to overlap with a top surface of the insulator; and processing the second material layer so as not to overlap with a top surface of the insulator, it would have been obvious to one of ordinary skill in the art to modify the processing of the first material so as not to overlap with a top surface of the insulator; and modify the processing of the second material layer so as not to overlap with a top surface of the insulator of Ito as taught by Malinowski through routine experimentation.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed processing the first material so as not to overlap with a top surface of the insulator; and processing the second material layer so as not to overlap with a top surface of the insulator or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 10, Ito (see, e.g., FIG. 1(a) to FIG. 1(i)) teaches the manufacturing method of a display device according to claim 8, wherein an inkjet method or a spin coating method is used as the wet process e.g., spin coating method of a coating solution (Para 0229, Para 0230).
Regarding claim 11, Ito (see, e.g., FIG. 1(a) to FIG. 1(i)) teaches the manufacturing method of a display device according to claim 8, further comprising the step of: forming a sacrificial layer 7 below the first resist mask 8’ (left) and the second resist mask 8’ (right) (Para 0006, Para 0030, Para 0032).
Regarding claim 21, Ito (see, e.g., FIG. 1(a) to FIG. 1(i)) teaches the manufacturing method of a display device according to claim 9, wherein an inkjet method or a spin coating method is used as the wet process e.g., spin coating method of a coating solution (Para 0229, Para 0230).
Regarding claim 22, Ito (see, e.g., FIG. 1(a) to FIG. 1(i)) teaches the manufacturing method of a display device according to claim 9, further comprising the step of: forming a sacrificial layer 7 below the first resist mask 8’ (left) and the second resist mask 8’ (right) (Para 0006, Para 0030, Para 0032).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTONIO CRITE whose telephone number is (571) 270-5267. The examiner can normally be reached Monday - Friday, 10:00 am - 6:30 pm.
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/ANTONIO B CRITE/Primary Examiner, Art Unit 2817
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