DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s amendment filed on April 03, 2026. Claims 1, 3, 6-7 and 11 have been amended. No new claim has been added. Claim 5 has been canceled. Currently claims 1-4 and 6-15 are pending.
Response to Arguments
Applicant’s arguments with respect to amended claim 1 filed on April 03, 2026 have been fully considered but they are not persuasive. The reason is set forth below,
Regarding Amended Claim 1, in the applicant’s arguments page 6-7, applicant stated "Thus, Qi discloses that the N+ regions include the first N+ portion region 74 & 46 (i.e., sidewall portion 74 and bottom portion 46) and the second N+ portion region 55. The trench is located above the N+ region 46 and partially surrounded by the P well 44, P+ junctions 53 are at both sides of the trench, and N+ junctions 55 are at both sides of the P+ junction 53. As such, (1) the second N+ region 55 is not provided on the P well 44; (2) since the second N+ regions 55 are provided at both sides of the P+ junction 53, and the P+ junctions 53 are provided at both sides of the trench, the second N+ regions 55 is not connected to the sidewall portion 74.
In contrast, in the present application, (1) the N+ contact region is provided on the P well region, thus both the first portion and second portion included in the N+ contact region are also provided on the P well region. Furthermore, (2) Applicant's claim 1 recites "the second portion is connected to the sidewall portion at a side of the second portion away from the substrate." Therefore, Qi fails to teach or suggest the limitations of Applicant's claim 1, as amended herein. The disclosures of Sun and Luo fail to remedy these deficiencies.”.
However, the amended claim does not claim the first portion and second portion included in the N+ contact region is also provided on the P well region. Furthermore, QI et al. Fig. 1 shows the second portion 55 is connected to the P+ junction 53 which is connected to side walls of 74, so 55 is connected to the sidewalls of 74 through 53. Therefore, the current prior art of record SUN, Wei-feng (CN 106024876 A) “SUN et al.” in view of LUO, Xiao-rong (CN 110504309 A) “LUO et al.” further in view of QI, Shukun (US 20190245069 A1) “QI et al.” still reads on the amended claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102, if the differences between the
claimed invention and the prior art are such that the claimed invention as a whole would have
been obvious before the effective filing date of the claimed invention to a person having
ordinary skill in the art to which the claimed invention pertains. Patentability shall not be
negated by the manner in which the invention was made.
Claims 1-2, 4 and 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over SUN, Wei-feng (CN 106024876 A) “SUN et al.” in view of LUO, Xiao-rong (CN 110504309 A) “LUO et al.” further in view of QI, Shukun (US 20190245069 A1) “QI et al.”.
Regarding Independent Claim 1, SUN et al. Figs. 1-11 discloses a reverse conducting lateral insulated-gate bipolar transistor (“A reverse conducting type for eliminating hysteresis phenomenon of the transverse insulated gate bipolar transistor device” ¶ [0028]), comprising:
a drift region (“N-type drift region 3” ¶ [0028]) formed on a substrate (“a P-type substrate 1 with buried oxide 2” ¶ [0028]),
a gate (“gate electrode” ¶ [0035]; Fig. 3 shows a gate electrode located on the N-type drift region 3) located on the drift region 3,
an emitter region (“emitter region 6” ¶ [0028]) located on the drift region 3 and adjacent to a side of the gate 17, and
a collector region (“collector region 13” ¶ [0028]) located on the drift region 3and away from a side of the gate 17; wherein:
two or more N-well regions arranged at intervals are provided on a side of the drift region on which the collector region is located (“a heavily doped 12 in each N-type buffer region of the N-type buffer region array of P-type collector region 13” ¶ [0028]);
a P+ contact region (“heavily doped P-type collector region 13” ¶ [0028]) is provided on a N-well region (equivalent to a P+ contact region provided on the N-well region);
an N+ contact region (“N type heavily doped region 14” ¶ [0028]) is provided on the P-well region (equivalent to an N+ contact region); and
both the P+ contact region and the N+ contact region are electrically connected to a collector leading-out terminal (Fig. 3 and 5 shows P+ contact region and N+ contact region are connected through V+).
the N+ contact region’s 14 the bottom portion is connected to the sidewall portion at a side of the bottom portion adjacent to the substrate (Fig. 2 shows bottom portion of 14 connected to side portions),
However, SUN et al. does not disclose, a P-well region is provided between two adjacent N-well regions of the two or more N-well regions arranged at intervals;
the N+ contact region comprises a first portion and a second portion, the first portion comprises a sidewall portion and a bottom portion, the sidewall portion extends in a direction perpendicular to a plane on which the substrate is located, the second portion is connected to the sidewall portion at a side of the second portion away from the substrate, and a depth of the sidewall portion is greater than a depth of the second portion.
In the similar field of endeavor of lateral insulated-gate bipolar transistor, LUO et al. Figs. 1-3 discloses, a P-well region (“P-well region 42” ¶ [0018]) is provided between two adjacent N-well regions (“N-type buffer layer 8” ¶ [0018]) of the two or more N-well regions arranged at intervals (“N-type buffer layer 8” ¶ [0018]);
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the buffer region of SUN et al. using the buffer region including a P-well region of LUO et al. in order to segment the distribution area. This segmented distribution mode can increase the parasitic NPN tube area composed by N+ anode region the P-well and N-type buffer layer, thereby increasing the device off during electron extraction path, which is good for further accelerating device is off and reduce off loss (LUO et al. ¶ [0024]).
However, LUO et al. does not disclose, wherein the N+ contact region comprises a first portion and a second portion, the first portion comprises a sidewall portion and a bottom portion, the sidewall portion extends in a direction perpendicular to a plane on which the substrate is located, the second portion is connected to the sidewall portion at a side of the second portion away from the substrate, and a depth of the sidewall portion is greater than a depth of the second portion.
In the similar field of endeavor of lateral insulated-gate bipolar transistor QI et al. Fig. 1 discloses, wherein the N+ contact region (55, 74 & 46) comprises a first portion (74 & 46) and a second portion (55), the first portion comprises a sidewall portion (side walls of 74) and a bottom portion 46 , the sidewall portion extends in a direction perpendicular to a plane on which the substrate 10 is located, the second portion (top of 55) is connected to the sidewall portion 74 at a side of the second portion away from the substrate 10, and a depth of the sidewall portion 74 is greater than a depth of the second portion 55.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the N+ contact region of SUN et al. as modified by LUO et al. with the N+ contact region of QI et al. in order to form a lower resistance path for hole injection, which starts to quickly extract the remaining minority carrier holes in the drift region, such that a faster switching speed is guaranteed, and the purpose of quick turning off can be achieved (QI et al., ¶ [0017]).
Regarding Claim 2, SUN et al. as modified by LUO et al. and QI et al. discloses limitations of claim 1. SUN et al. further discloses, an area of the first N-well region is equal to an area of the second N-well region (Fig. 1-2 shows the different buffer areas 12 are equal to each other),
However, SUN et al. does not disclose, wherein the two or more N-well regions arranged at intervals at least comprises a first N-well region and a second N-well region, the P-well region at least comprises a first P- well region provided between the first N-well region and the second N-well region, and the first N- well region and the second N-well region are symmetrically arranged with respect to the first P-well region.
In the similar field of endeavor of lateral insulated-gate bipolar transistor, LUO et al. Figs. 1-3 discloses, wherein the two or more N-well regions (“N-type buffer layer 8” ¶ [0018]) arranged at intervals at least comprises a first N-well region and a second N-well region, the P-well region (“P-well region 42” ¶ [0018]) at least comprises a first P- well region provided between the first N-well region and the second N-well region (“N-type buffer layer 8” ¶ [0018]), and the first N- well region and the second N-well region are symmetrically arranged (Fig. 3 shows the first N- well region and the second N-well region are symmetrically arranged with respect to the first P-well region 42) with respect to the first P-well region (“P-well region 42” ¶ [0018]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the buffer region of SUN et al. using the buffer region including a P-well region of LUO et al. in order to segment the distribution area. This segmented distribution mode can increase the parasitic NPN tube area composed by N+ anode region the P-well and N-type buffer layer, thereby increasing the device off during electron extraction path, which is good for further accelerating device is off and reduce off loss (LUO et al. ¶ [0024]).
Regarding Claim 4, SUN et al. as modified by LUO et al. and QI et al. discloses limitations of claim 1. SUN et al. does not disclose, wherein the N+ contact region is enclosed by the P-well region in a direction parallel to a plane on which the substrate is located.
In the similar field of endeavor of lateral insulated-gate bipolar transistor, LUO et al. Figs. 1-3 discloses, wherein the N+ contact region (“N+ anode region 62” ¶ [0018]) is enclosed by the P-well region (“P-well region 42” ¶ [0018]) in a direction parallel (Figures 1-2, shows the P-well region 42 surrounds the N + anode region 62 in a direction parallel to the plane of the silicon substrate 1) to a plane on which the substrate (“substrate 1” ¶ [0016]) is located.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the buffer region of SUN et al. using the buffer region including a P-well region of LUO et al. in order to segment the distribution area. This segmented distribution mode can increase the parasitic NPN tube area composed by N+ anode region the P-well and N-type buffer layer, thereby increasing the device off during electron extraction path, which is good for further accelerating device is off and reduce off loss (LUO et al. ¶ [0024]).
Regarding Claim 10, SUN et al. as modified by LUO et al. and QI et al. discloses limitations of claim 1. SUN et al. does not disclose, wherein there exists a plurality of P-well regions, a plurality of N+ contact regions are respectively located in the plurality of P-well regions, and the plurality of N+ contact regions are arranged alternatively with the P+ contact regions in a direction parallel to a plane where the substrate is located.
In the similar field of endeavor of lateral insulated-gate bipolar transistor, LUO et al. Figs. 1-3 discloses, wherein there exists a plurality of P-well regions(“P-well region 42” ¶ [0018]; Fig. 3 shows plurality of 42), a plurality of N+ contact regions (“N+ anode region 62” ¶ [0018]; Fig. 3 shows plurality of 62) are respectively located in the plurality of P-well regions 42, and the plurality of N+ contact regions 62 are arranged alternatively with the P+ contact regions (“P+ anode region 52” ¶ [0018]) in a direction parallel to a plane where the substrate 1 is located (Fig. 3, shows the plurality of N+ contact regions 62 are arranged alternatively with the P+ contact 52 regions in a direction parallel to a plane where the substrate 1 is located).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the buffer region of SUN et al. using the buffer region including a P-well region of LUO et al. in order to segment the distribution area. This segmented distribution mode can increase the parasitic NPN tube area composed by N+ anode region the P-well and N-type buffer layer, thereby increasing the device off during electron extraction path, which is good for further accelerating device is off and reduce off loss (LUO et al. ¶ [0024]).
Regarding Claim 11, SUN et al. as modified by LUO et al. and QI et al. discloses limitations of claim 10. SUN et al. does not disclose, wherein the two or more N-well regions provided at intervals are arranged alternatively with the plurality of P-well regions in a direction parallel to a plane where the substrate is located.
In the similar field of endeavor of lateral insulated-gate bipolar transistor, LUO et al. Figs. 1-3 discloses, wherein the two or more N-well regions 8 provided at intervals are arranged alternatively with the plurality of P-well regions 42 in a direction parallel to a plane where the substrate 1 is located (Fig. 3, shows N-well regions 8 provided at intervals are arranged alternatively with the plurality of P-well regions 42 in a direction parallel to a plane where the substrate 1 is located).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the buffer region of SUN et al. using the buffer region including a P-well region of LUO et al. in order to segment the distribution area. This segmented distribution mode can increase the parasitic NPN tube area composed by N+ anode region the P-well and N-type buffer layer, thereby increasing the device off during electron extraction path, which is good for further accelerating device is off and reduce off loss (LUO et al. ¶ [0024]).
Regarding Claim 12, SUN et al. as modified by LUO et al. and QI et al. discloses limitations of claim 1. SUN et al. does not disclose, wherein a potential barrier between the P-well region and the drift region is lower than a potential barrier between the P-well region and the N-well region.
In the similar field of endeavor of lateral insulated-gate bipolar transistor, LUO et al. Figs. 1-3 discloses, wherein a potential barrier between the P-well region and the drift region is lower than a potential barrier between the P-well region and the N-well region (“NPN structure opening device off in the process, an anode + anode by N region 62, P-well region 42 and the N-type buffer layer 8, which can accelerate the electron drift region stored in the extraction, reducing the off time and off loss. blocking device is turned on, the electronic drift region is the anode P well region 42 barrier” ¶ [0020]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the buffer region of SUN et al. using the NPN structure of LUO et al. in order to increase the carrier concentration of the drift region (LUO et al. ¶ [0020]).
Regarding Claim 13, SUN et al. as modified by LUO et al. and QI et al. discloses limitations of claim 1. SUN et al. further discloses, further comprising a channel region located on the drift region and adjacent to a side of the drift region on which the gate is located, wherein the channel region forms a conductive channel, and the N-well region is spaced from the channel region to serve as an N-type buffer layer of the reverse conducting lateral insulated-gate bipolar transistor (“the P-area and P-body region surface inversion occurs to form an electronic channel, emitter electron injected into the N-type drift region through the channel from the N-type emitter region,” ¶ [0034]).
Regarding Claim 14, SUN et al. as modified by LUO et al. and QI et al. discloses limitations of claim 13. SUN et al. further discloses, wherein a substrate ohmic contact region having a first conductivity type and a source ohmic contact region having a second conductivity type are provided in the channel region (“the P-area and P-body region surface inversion occurs to form an electronic channel, emitter electron injected into the N-type drift region through the channel from the N-type emitter region,” ¶ [0034]), and the source ohmic contact region is in contact with the channel region at a side of the source ohmic contact region facing the gate to induce a channel in the channel region (“partially enclosed area for eliminating the hysteresis phenomenon of the reverse conducting type transverse insulated gate bipolar transistor device, wherein, between the adjacent oxide layer isolation trench 11 is provided with a second N-type heavily doped region 8, the second N-type heavily doped region 8 is provided with a metal electrode 9 and partially enclosed region of the metal electrode 9 and the ohmic contact of the second N type heavily doped region 8, the N-type drift region 3 is provided with a metal electrode 10 and the metal electrode 10 and the N-type drift region 3 form a Schottky contact. the metal electrode 9 and the metal electrode 10 is connected.” ¶ [0029]).
Claims 3 is rejected under 35 U.S.C. 103 as being unpatentable over SUN, Wei-feng (CN 106024876 A) “SUN et al.” in view of LUO, Xiao-rong (CN 110504309 A) “LUO et al.” further in view of LIN, Zhi (US 20190252531 A1) “LIN et al.”.
Regarding Claim 3, SUN et al. as modified by LUO et al. and QI et al. discloses limitations of claim 2. However, SUN et al. does not disclose, wherein the first N-well region, the first P-well region and the second N-well regions are arranged in sequence in a direction from the emitter region to the collector region.
In the similar field of endeavor of lateral insulated-gate bipolar transistor, LIN et al. Fig. 12a discloses, wherein the first N-well region (“region 13” ¶ [0072), the first P-well region (“region 24 having a conductivity type of P type” ¶ [0072]) and the second N-well regions (“region 16 having a conductivity type of N type” ¶ [0072]) are arranged in sequence in a direction (Fig. 12a shows are 13, 24 and 16 are arranged in sequence in a direction from the emitter region 11 to the collector region 22.) from the emitter region 11 (“a semiconductor emitter region 11” ¶ [0072]) to the collector region 22 (“semiconductor collector region 22” ¶ [0072]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the buffer region of SUN et al. using the buffer region including a P-well region of LIN et al. in order to construct a super junction LIGBT on a bulk silicon substrate at a low cost to achieve fast turn-off. Specifically, this is achieved by making the semiconductor first substrate region a heavily doped region, thereby making the minority carriers injected from the semiconductor collector region are quickly compounded by the Auger effect, avoiding the accumulation of a large number of unbalanced carriers in the substrate and achieving the purpose of fast turn-off. In addition, since the total number of impurities in the semiconductor first drift region in the voltage-sustaining region is smaller than the total number of impurities in the semiconductor second drift region, the equivalent impurity in the voltage-sustaining layer is the second conductivity type. Specifically, along the direction in which the N-column and the P-column are arranged, by dividing the total number of impurities of the semiconductor second drift region minus the total number of impurities of the semiconductor first drift region by the length of the voltage-sustaining layer, the dose of the average impurity obtained is about 10.sup.12 cm.sup.−2; when the device is in the forward blocking state, an electric field is established between these equivalent impurities and the impurities in the semiconductor first substrate region and the impurities in the semiconductor field stop region to obtain a high breakdown voltage. (LIN et al. ¶ [0027]).
Regarding Claim 6, SUN et al. as modified by LUO et al. and QI et al. discloses limitations of claim 5. However, SUN et al. does not disclose, wherein the depth of the sidewall portion is greater than a depth of the P+ contact region.
In the similar field of endeavor of lateral insulated-gate bipolar transistor QI et al. Fig. 1 discloses, wherein the depth of the sidewall portion 74 is greater than a depth of the P+ contact region 53.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the N+ contact region of SUN et al. with the N+ contact region of QI et al. in order to form a lower resistance path for hole injection, which starts to quickly extract the remaining minority carrier holes in the drift region, such that a faster switching speed is guaranteed, and the purpose of quick turning off can be achieved (QI et al., ¶ [0017]).
Regarding Claim 7, SUN et al. as modified by LUO et al. and QI et al. discloses limitations of claim 5. However, SUN et al. does not disclose, wherein a trench is formed in the P-well region, and the sidewall portion and the bottom portion of the first portion are formed by doping a side surface and a bottom surface of the trench respectively.
In the similar field of endeavor of lateral insulated-gate bipolar transistor QI et al. Fig. 1 discloses, wherein a trench is formed in the P-well region, and the sidewall portion and the bottom portion of the first portion are formed by doping a side surface and a bottom surface of the trench respectively (“the implantation in the step S250 is performed by multiple implantations” ¶ [0046]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the N+ contact region of SUN et al. with the N+ contact region of QI et al. in order to obtain a dopant concentration gradient with slower varying (QI et al., ¶ [0046]).
Regarding Claim 8, SUN et al. as modified by LUO et al. and QI et al. discloses limitations of claim 7. However, SUN et al. does not disclose, wherein a filling structure is formed in the trench, and the second portion is located on the filling structure.
In the similar field of endeavor of lateral insulated-gate bipolar transistor QI et al. Fig. 1 discloses, wherein a filling structure 74 is formed in the trench, and the second portion is located on the filling structure (“a polysilicon 74 in the trench” ¶ [0016]; “polysilicon 74 is N+ heavily doped” ¶ [0041]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the N+ contact region of SUN et al. with the N+ contact region of QI et al. in order to form a lower resistance path for hole injection, which starts to quickly extract the remaining minority carrier holes in the drift region, such that a faster switching speed is guaranteed, and the purpose of quick turning off can be achieved (QI et al., ¶ [0017]).
Regarding Claim 9, SUN et al. as modified by LUO et al. and QI et al. discloses limitations of claim 8. However, SUN et al. does not disclose, wherein a material of the filling structure comprises an insulating material and/or polysilicon.
In the similar field of endeavor of lateral insulated-gate bipolar transistor QI et al. Fig. 1 discloses, wherein a material of the filling structure comprises an insulating material and/or polysilicon (“a polysilicon 74 in the trench” ¶ [0016]; “polysilicon 74 is N+ heavily doped” ¶ [0041]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the N+ contact region of SUN et al. with the N+ contact region of QI et al. in order to form a lower resistance path for hole injection, which starts to quickly extract the remaining minority carrier holes in the drift region, such that a faster switching speed is guaranteed, and the purpose of quick turning off can be achieved (QI et al., ¶ [0017]).
Claims 15 is rejected under 35 U.S.C. 103 as being unpatentable over SUN, Wei-feng (CN 106024876 A) “SUN et al.” in view of LUO, Xiao-rong (CN 110504309 A) “LUO et al.” further in view of QI, Shukun (US 20190245069 A1) “QI et al.” further in view of TOKURA, Norihito (US 20120061726 A1) “TOKURA et al.”.
Regarding Claim 15, SUN et al. as modified by LUO et al. and QI et al. discloses limitations of claim 1. SUN et al. does not disclose, further comprising a field oxide layer formed between the drift region and the gate, and the field oxide layer serves as an isolation field region between the drift region and the gate.
In the similar field of endeavor, TOKURA et al. Fig. 18 discloses, further comprising a field oxide layer (“a LOCOS oxide film 3 is formed to isolate each component part of the lateral IGBT” ¶ [0035]) formed between the drift region and the gate, and the field oxide layer serves as an isolation field region (“a LOCOS oxide film 3 is formed to isolate each component part of the lateral IGBT” ¶ [0035]) between the drift region 2 and the gate 11 (Fig. 18 shows a field oxide layer 3 is formed between the drift region 2 and the gate 11, and the field oxide layer 3 serves as an isolation field region between the drift region 2 and the gate 11).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the drift region of SUN et al. using drift region including a oxide layer of TOKURA et al. in order to isolate each component part of the lateral IGBT (TOKURA et al. ¶ [0035]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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