DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
2. The Amendments filed April 6th, 2026 in response to the Non-Final Office Action mailed 01/07/2026 are noted.
Applicant has not amended the Claims to overcome the objection(s) to minor grammatical informalities previously set forth in the Non-Final Office Action mailed 01/07/2026, so the objection(s) to minor grammatical informalities has been maintained.
Applicant’s amendment(s) to the claims have overcome the 35 U.S.C. § 112 rejection(s)
previously set forth in the Non-Final Office Action mailed 01/07/2026, so the 35 U.S.C. § 112
rejection(s) have been withdrawn.
Applicant’s amendments to the claims are noted.
3. Claims 1-20 remain pending in the application.
4. Claims 1-20 have been fully considered in examination.
Claim Objections
Claim 14, lines 3-4: “an additional metal layer at the second side that form…” should (still) read --- an additional metal layer at the second side that forms ---
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation "the integrated circuit package" in line 3. There is no specific prior recitation of “an integrated circuit package” in claim 4 or claim 1 on which claim 4 depends – rendering it unclear if “the integrated circuit package” in claim 4 refers to a previously recited “integrated” components or a newly-introduced entity. Therefore, for the purposes of examination, Examiner has interpreted “the integrated circuit package” as --- an integrated circuit package --- however, this edit may be altered if Applicant intends otherwise.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 17 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gambino (U.S. PG Pub No US2019/0043903A1) (of record).
Regarding claim 17, Gambino teaches an image sensor package [see fig. 9, 0063] comprising:
a first integrated circuit die (138) fig. 9 [0063] having image sensor pixels (individual pixels defined as comprising individual photodiodes 140 and individual 148s) fig. 9 [0064] arranged in a plurality of lines (148-lines);
a second integrated circuit die (154) fig. 9 [0066] mounted to the first integrated circuit die (138) and having inter-die connection (individual 152s with 156s) fig. 9 [0065] with the first integrated circuit die (138) on a per-pixel basis (per-148’s); and
a third integrated circuit die (166) fig. 9 [0069] mounted to the second integrated circuit die (154) and having inter-die connection (electrical-connection pathways facilitated by 172 [0069]) with the second integrated circuit die (154) on a per-pixel row basis (one 172 is provided per pixel row of 140s, as shown in fig. 9 cross-sectional view).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 11-12, 15, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Gambino (U.S. PG Pub No US2019/0043903A1) (of record) in view of Liu (U.S. PG Pub No US2019/0371766A1).
Regarding claim 1, Gambino teaches an image sensor [see fig. 9, 0063] comprising:
a first integrated circuit die (138) fig. 9 [0063] having image sensor pixel circuitry (comprising 148) fig. 9 [0064];
a second integrated circuit die (154) fig. 9 [0066] having charge storage circuitry (comprising 158) fig. 9 [0067], the second integrated circuit die (154) being mounted to the (bottom of) first integrated circuit die (138); and
a third integrated circuit die (166) fig. 9 [0069] having pixel readout circuitry (‘digital signal processing’) [0050, 0069] and having an inter-die connection structure (comprising 172) fig. 9 [0069] connected to the second integrated circuit die (154) and disposed on a (top) side of the third integrated circuit die (138) facing the second integrated circuit die (154), the third integrated circuit die (166) having a lateral outline different from a lateral outline of the second integrated circuit die (154) (presence of different elements on the inner sidewalls of dies 154, 166 leads to different inner sidewall outlines in dies 154 and 166).
However, Gambino does not explicitly disclose wherein an outermost perimeter of the third integrated circuit die (166) is one of larger than or smaller than an outermost perimeter of the second integrated circuit die (154) (insufficient size information).
Liu teaches a die package (102) figs. 1A-1C [0020] applicable to image sensors [see figs. 1A-1C, 0038] wherein an outermost perimeter (“footprint” [0040] – determined by length and width [0040]) of the third integrated circuit die (106-1) fig. 1A [0020] is one of larger than or smaller (“different” [0040]) than an outermost perimeter (“footprint” [0040]) of the second integrated circuit die (106-2) fig. 1A [0020] ( [see figs. 1B-1C, 0040] 106-1 and 106-2 may have “different” lengths/widths [0040] – and, consequently, different ‘footprints/perimeters [0040]; “different” condition being met by one die having a larger or smaller footprint/perimeter [0040] than the other - i.e, the ‘third’ die corresponding to 106-1 could have a smaller ‘footprint’ / perimeter than the second die corresponding to 106-2 [0040]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the dies of Gambino to explicitly have different relative sizes and footprints [0040], more specifically, such that one die has a smaller footprint than another [0040], in order to reduce the overall footprint of the die stack architecture [0013, 0015, 0040] so as to enhance the integration density of dies stacked in a vertical direction [0013, 0015] in the package, as taught by Liu.
Regarding claim 2, Gambino in view of Liu teaches the image sensor [see fig. 9, 0063] of claim 1. Gambino also teaches wherein the second integrated circuit die (154) fig. 9 [0066] has an interconnect layer (156) fig. 9 [0069] forming an inter-die connection structure (collective 156s in 154) that connects to (‘electrically couples to’ [0069] interconnected dies) the inter-die connection structure (172) fig. 9 [0069] of the third integrated circuit die (166) fig. 9 [0069], the interconnect layer (156) being formed on a (top) side of the second integrated circuit die (154) facing the first integrated circuit die (138) fig. 9 [0063].
Regarding claim 3, Gambino in view of Liu teaches the image sensor [see fig. 9, 0063] of claim 2. Gambino also teaches wherein the first integrated circuit die (138) fig. 9 [0063] has an interconnect layer (152) fig. 9 [0065] forming an inter-die connection structure (‘die-to-die interconnects’ [0065]) that connects to the second integrated circuit die (154) fig. 9 [0066], the interconnect layer (152) of the first integrated circuit die (138) fig. 9 [0063] being formed on a (bottom) side of the first integrated circuit die (138) facing the second integrated circuit die (154).
Regarding claim 4, Gambino in view of Liu teaches the image sensor [see fig. 9, 0063] of claim 1. However, Gambino does not explicitly disclose further comprising a package connection structure directly coupled to the second integrated circuit die (154) fig. 9 [0066] and configured to electrically couple to a surface external to an integrated circuit package (integrated circuit package defined as 136 with 154 with 166) fig. 9 [0066, 0069].
Liu teaches a die package (102) figs. 1A-1C [0020] applicable to image sensors [see figs. 1A-1C, 0038] further comprising a package connection structure (structure defined as 129 with 111-1 with 111-2 with 108, each physically/electrically coupled) fig. 1A [0024-0027] directly coupled to the second integrated circuit die (106-2) fig. 1A [0020] and configured to electrically couple to a surface (surface of 121) fig. 1A [0030] external to an integrated circuit package (integrated circuit package defined as components die stack 150 [0036] within and including 127 material [0036]) fig. 1A [0036].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the package of Gambino to include the additional conductive material [0027] of Liu directly coupled to the dies [0024-0027] in order to facilitate electrical connections between the dies and external circuitry [0030-0031, 0033] used to guide die operations [0030], thereby enhancing connectivity and controllability of the die package [0024-0027, 0030-0031], as taught by Liu.
Regarding claim 11, Gambino teaches an integrated circuit package [see fig. 9, 0063] (comprising first – third dies 138, 154, 166 and structures therebetween) comprising:
a first integrated circuit die (138) fig. 9 [0063];
a second integrated circuit die (154) fig. 9 [0066] having first (top) and second (bottom) opposing sides and attached to the first integrated circuit die (138) at the first (top) side; and
a third integrated circuit die (166) fig. 9 [0069] having inter-die connection structures (comprising 172) fig. 9 [0069] at a (top of 166) side facing the second integrated circuit die (166) and attached to the second integrated circuit die (154) at the side of the third integrated circuit die (166).
However, Gambino does not explicitly disclose wherein the third integrated circuit die (166) has an outermost perimeter that is smaller than an outermost perimeter of the second integrated circuit die (154) (insufficient size information).
Liu teaches a die package (102) figs. 1A-1C [0020] applicable to image sensors [see figs. 1A-1C, 0038] wherein the third integrated circuit die (106-1) fig. 1A [0020] has an outermost perimeter (“footprint” [0040] – determined by length and width [0040]) that is smaller than (“different from” – implying could be smaller or larger than [0040]) an outermost perimeter (“footprint” [0040]) of the second integrated circuit die (106-2) fig. 1A [0020] ([see figs. 1B-1C, 0040] 106-1 and 106-2 may have “different” lengths/widths [0040] – and, consequently, different ‘footprints/perimeters [0040]; “different” condition being met by one die having a larger or smaller footprint/perimeter [0040] than the other - i.e, the ‘third’ die corresponding to 106-1 could have a smaller ‘footprint’ / perimeter than the second die corresponding to 106-2 [0040]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the dies of Gambino to explicitly have different relative sizes and footprints [0040], more specifically, such that one die has a smaller footprint than another [0040], in order to reduce the overall footprint of the die stack architecture [0013, 0015, 0040] so as to enhance the integration density of dies stacked in a vertical direction [0013, 0015] in the package, as taught by Liu.
Regarding claim 12, Gambino in view of Liu teaches an integrated circuit package [see fig. 9, 0063] of claim 11. Gambino also teaches wherein the (width) dimension between the opposing lateral edges (inner sidewalls bordering 172) of the third integrated circuit die (166) fig. 9 [0069] is less than the dimension between the corresponding opposing lateral edges (inner sidewalls bordering 172) of the second integrated circuit die (154) fig. 9 [0068] (wider gap created by 172 in 154 die than in 166 die).
Regarding claim 15, Gambino in view of Liu teaches the integrated circuit package [see fig. 9, 0063] of claim 11. However, Gambino does not explicitly disclose further comprising a package connection structure directly coupled to the second integrated circuit die (154) fig. 9 [0066] and configured to electrically couple to a surface external to the integrated circuit package (integrated circuit package defined as 136 with 154 with 166) fig. 9 [0066, 0069].
Liu teaches a die package (102) figs. 1A-1C [0020] applicable to image sensors [see figs. 1A-1C, 0038] further comprising a package connection structure (structure defined as 129 with 111-1 with 111-2 with 108, each physically/electrically coupled) fig. 1A [0024-0027] directly coupled to the second integrated circuit die (106-2) fig. 1A [0020] and configured to electrically couple to a surface (surface of 121) fig. 1A [0030] external to an integrated circuit package (integrated circuit package defined as components die stack 150 [0036] within and including 127 material [0036]) fig. 1A [0036].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the package of Gambino to include the additional conductive material [0027] of Liu directly coupled to the dies [0024-0027] in order to facilitate electrical connections between the dies and external circuitry [0030-0031, 0033] used to guide die operations [0030], thereby enhancing connectivity and controllability of the die package [0024-0027, 0030-0031], as taught by Liu.
Regarding claim 18, Gambino teaches the image sensor [see fig. 9, 0063] of claim 17. However, Gambino does not explicitly disclose wherein the third integrated circuit die (166) has an outermost perimeter that is different from an outermost perimeter of the second integrated circuit die (154) (insufficient size information).
Liu teaches a die package (102) figs. 1A-1C [0020] applicable to image sensors [see figs. 1A-1C, 0038] wherein the third integrated circuit die (106-1) fig. 1A [0020] has an outermost perimeter (“footprint” [0040] – determined by length and width [0040]) that is different from [0040] an outermost perimeter (“footprint” [0040]) of the second integrated circuit die (106-2) fig. 1A [0020].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the dies of Gambino to explicitly have different relative sizes and footprints [0040], more specifically, such that one die has a smaller footprint than another [0040], in order to reduce the overall footprint of the die stack architecture [0013, 0015, 0040] so as to enhance the integration density of dies stacked in a vertical direction [0013, 0015] in the package, as taught by Liu.
Regarding claim 19, Gambino in view of Liu teaches the image sensor [see fig. 9, 0063] of claim 18. Gambino also teaches wherein the plurality of lines (comprising individual 148’s) fig. 9 [0064] is a plurality of pixel columns (individual columns comprising individual 148s with individual 140s), and wherein the third integrated circuit die (166) fig. 9 [0069] comprises pixel column readout circuitry (‘digital signal processing’) [0050, 0069].
Claims 5 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Gambino (U.S. PG Pub No US2019/0043903A1) (of record) modified by Liu (U.S. PG Pub No US2019/0371766A1), as applied in claims 1 and 11 above, and further in view of Ha (U.S. PG Pub No US2019/0067059A1).
Regarding claim 5, Gambino in view of Liu teaches the image sensor [see fig. 9, 0063] of claim 1. However, Gambino does not explicitly disclose further comprising a mold compound directly coupled to a sidewall of the first integrated circuit die (138) fig. 9 [0063], a sidewall of the second integrated circuit die (154) fig. 9 [0066], a sidewall of the third integrated circuit die (166) fig. 9 [0069], and a sidewall of a transparent layer.
Liu teaches a die package (102) figs. 1A-1C [0020] applicable to image sensors [see figs. 1A-1C, 0038] further comprising further comprising a mold compound (127) fig. 1A [0036] directly coupled to a sidewall of the first integrated circuit die (upper 106-1) fig. 1A [0020-0024], a sidewall of the second integrated circuit die (lower 106-2) fig. 1A [0020-0024], a sidewall of the third integrated circuit die (lower 106-1) fig. 1A [0020-0024], and a sidewall of a layer (107) fig. 1A [0034] (“die attach film” [0034]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the package of Gambino such that the plurality of stacked dies are directly surrounded by a mold compound [0036] in order to provide mechanical protection of the die stack [0036] and electronic connections thereto [0036], as taught by Liu.
However, Gambino in view of Liu does not explicitly disclose wherein the layer (107) [0034 Liu] (“die attach film” [0034]) is a transparent layer (material and optical properties of die attach film not specified).
Ha teaches a package comprising an image sensor [see fig. 2B, 0026, 0041] wherein the layer (30) fig. 2B [0031, 0034] (“die attach film” [0031]) is a transparent layer [0031] (such as PET [0031]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention such that the die attach film encapsulated by the mold material in the package of Gambino in view of Liu is formed of a transparent material [0031] like PET or epoxy [0031] in order to allow for light to be transmitted through the transparent film [0031, 0034] to/from the die surfaces [0034], supporting the attachment of the dies [0031] without hindering light sensor performance [0034], as taught by Ha.
Regarding claim 16, Gambino in view of Liu teaches the integrated circuit package [see fig. 9, 0063] (comprising first – third dies 138, 154, 166 and structures therebetween) of claim 11. However, Gambino does not explicitly disclose further comprising a mold compound directly coupled to a sidewall of the first integrated circuit die (138) fig. 9 [0063], a sidewall of the second integrated circuit die (154) fig. 9 [0066], a sidewall of the third integrated circuit die (166) fig. 9 [0069], and a sidewall of a transparent layer.
Liu teaches a die package (102) figs. 1A-1C [0020] applicable to image sensors [see figs. 1A-1C, 0038] further comprising further comprising a mold compound (127) fig. 1A [0036] directly coupled to a sidewall of the first integrated circuit die (upper 106-1) fig. 1A [0020-0024], a sidewall of the second integrated circuit die (lower 106-2) fig. 1A [0020-0024], a sidewall of the third integrated circuit die (lower 106-1) fig. 1A [0020-0024], and a sidewall of a layer (107) fig. 1A [0034] (“die attach film” [0034]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the package of Gambino such that the plurality of stacked dies are directly surrounded by a mold compound [0036] in order to provide mechanical protection of the die stack [0036] and electronic connections thereto [0036], as taught by Liu.
However, Gambino in view of Liu does not explicitly disclose wherein the layer (107) [0034 Liu] (“die attach film” [0034]) is a transparent layer (material and optical properties of die attach film not specified).
Ha teaches a package comprising an image sensor [see fig. 2B, 0026, 0041] wherein the layer (30) fig. 2B [0031, 0034] (“die attach film” [0031]) is a transparent layer [0031] (such as PET [0031]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention such that the die attach film encapsulated by the mold material in the package of Gambino in view of Liu is formed of a transparent material [0031] like PET or epoxy [0031] in order to allow for light to be transmitted through the transparent film [0031, 0034] to/from the die surfaces [0034], supporting the attachment of the dies [0031] without hindering light sensor performance [0034], as taught by Ha.
Claims 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Gambino (U.S. PG Pub No US2019/0043903A1) (of record) modified by Liu (U.S. PG Pub No US2019/0371766A1), as applied in claim 2 above, and further in view of Kim (U.S. PG Pub No US2016/0233196A1) (of record).
Regarding claim 6, Gambino in view of Liu teaches the image sensor [see fig. 9, 0063] of claim 2. However, Gambino does not explicitly disclose wherein a metal structure in a redistribution layer at an additional side of the second integrated circuit die (154) fig. 9 [0066] opposite the (top) side of the second integrated circuit die (154) forms a portion of the inter-die connection structure of the second integrated circuit die (154) that connects to the inter-die connection structure (comprising 172) fig. 9 [0069] of the third integrated circuit die (166) fig. 9 [0069].
Kim teaches a semiconductor device (300) fig. 3 [0058] wherein a metal structure (141) fig. 3 [0032] (copper) [0032] in a redistribution layer (comprising 141, 144) fig. 3 [0032, 0035] at (on) an additional (bottom) side of the second integrated circuit die (120) fig. 3 [0050] opposite the (top) side of the second integrated circuit die (120) forms a portion of the inter-die connection structure (comprising 141, 143, 170) fig. 6 [0033] of the second integrated circuit die (120) that connects to the inter-die connection structure (comprising 110) fig. 9 [0017] of the third integrated circuit die (150) fig. 3 [0050].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the die-interconnect structure of Gambino to comprise the redistribution layers of Kim [0032-0036] in order to promote additional electrical connections with the interconnect structures [0018] of the dies [0066] to facilitate signal distribution [0036], as taught by Kim.
Regarding claim 7, Gambino in view of Liu and Kim teaches the image sensor [see fig. 9, 0063] of claim 6. Gambino also teaches the inter-die connection structure (156) fig. 9 [0069] of the second integrated circuit die (154) fig. 9 [0066] and the inter-die connection structure (comprising 172) fig. 9 [0069] of the third integrated circuit die (156) fig. 9 [0069] form a hybrid bond (contribute to the formation of hybrid bond(s) [0017-0018, 0071-0072]).
Regarding claim 8, Gambino in view of Liu and Kim teaches the image sensor [see fig. 9, 0063] of claim 6. Gambino in view of Liu and Kim (with reference to Kim) also teaches wherein the inter-die connection structure (comprising 117) fig. 3 [0032] of the second integrated circuit die (120) fig. 3 [0050] and the inter-die connection structure (110) fig. 3 [0031] of the third integrated circuit die (150) fig. 3 [0050] form (host) a micro-bump connection (117, 110 form electrical connections with micron-sized solder bumps [0023, 0030]).
Regarding claim 9, Gambino in view of Liu and Kim teaches the image sensor [see fig. 9, 0063] of claim 6. Gambino in view of Liu and Kim (with reference to Kim) wherein the metal structure (141) fig. 3 [0032] (copper) [0032] in the redistribution layer (comprising 141, 144) fig. 3 [0032, 0035] forms a fan-in structure [0036] toward the third integrated circuit die (150) fig. 3 [0050] (redistribution structure may fan-in or fan-out [0080]).
Regarding claim 10, Gambino in view of Liu and Kim teaches the image sensor [see fig. 9, 0063] of claim 6. Gambino in view of Liu and Kim (with reference to Kim) wherein the metal structure (141) fig. 3 [0032] (copper) [0032] in the redistribution layer (comprising 141, 144) fig. 3 [0032, 0035] forms a fan-out structure [0080] toward the third integrated circuit die (150) fig. 3 [0050] (redistribution structure may fan-in or fan-out [0080]).
Claims 13-14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Gambino (U.S. PG Pub No US2019/0043903A1) (of record) modified by Liu (U.S. PG Pub No US2019/0371766A1), as applied in claim 18 above, and further in view of Madurawe (U.S. PG Pub No US2017/0221954A1) (of record).
Regarding claim 13, Gambino in view of Liu teaches the integrated circuit package [see fig. 9, 0063] of claim 12. However, Gambino does not explicitly disclose wherein the second integrated circuit die (154) fig. 9 [0066] includes a metal layer at the first side and a conductive via that extends through a substrate (154) second integrated circuit die (154), and wherein the metal layer and the conductive via form an inter-die connection structure that connects to a given one of the inter-die connection structures (comprising 172) fig. 9 [0069] of the third integrated circuit die (166) fig. 9 [0069].
Madurawe teaches an integrated circuit package [see fig. 6, 0032] wherein the second integrated circuit die (34) fig. 6 [0032] includes a metal layer (upper 66a fill material) fig. 6 [0037] at the first (top) side and a conductive via (lower 66a opening) fig. 6 [0037] that extends (partially) through a substrate (lower, semiconductor material of die 34) fig. 6 [0032] of the second integrated circuit die (34), and wherein the metal layer (upper 66a) and the conductive via (lower 66a) form an inter-die connection structure (connected to 38A/38B) [0031] that connects to a given one of the inter-die connection structures (comprising 38B) fig. 6 [0032] of the third integrated circuit die (36) fig. 6 [0031].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the package of Gambino such that a plurality of conductive vias are included in the die substrate [0032, 0037] in order to enhance the electrical interconnectivity [0004, 0032] of the circuitry of the upper and lower dies [0004, 0037], as taught by Madurawe.
Regarding claim 14, Gambino in view of Liu teaches an integrated circuit package [see fig. 9, 0063] of claim 13. Gambino in view of Liu and Madurawe (with reference to Madurawe) also teaches wherein the second integrated circuit die (34) fig. 6 [0032] includes an additional metal layer (38A) fig. 6 [0037] at the second (bottom) side that forms at least a part of the inter-die connection structure (comprising 38A) fig. 6 [0037] connecting to the given one of the inter-die connection structures (comprising 38B) fig. 6 [0037] of the third integrated circuit die (36) fig. 6 [0031].
Regarding claim 20, Gambino in view of Liu teaches the image sensor [see fig. 9, 0063] of claim 18. However, Gambino does not explicitly disclose wherein the plurality of lines (comprising individual 148’s) fig. 9 [0064] is a plurality of pixel rows, and wherein the third integrated circuit die (166) fig. 9 [0069] comprises pixel row control circuitry (not explicitly shown).
Madurawe teaches an image sensor [0049] wherein the plurality of lines (comprising individual 62s) fig. 6 [0025, 0035] is a plurality of pixel rows (22-rows) fig. 3 [0025], and wherein the third integrated circuit die (lower-die 36) fig. 6 [0035] comprises pixel row control circuitry (comprising row select transistor 56) fig. 6 [0025].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the image sensor of Gambino such that the photodiodes are arranged in a plurality of rows controlled by row select circuitry [0025, 0035, 0045] in order to facilitate high-image-quality [0005] while minimizing parasitic capacitance [0006, 0049-0050], as taught by Madurawe.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-16 and 18-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed 04/06/2026 with respect to claim 17 have been fully considered but they are not persuasive because they do not point out the supposed deficiencies with respect to the teachings of Gambino (U.S. PG Pub No US2019/0043903A1) (of record) and the amendment(s) to claim 17. Therefore, the rejection of claim 17 presented above is considered as a sufficient response-to-arguments.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hsu (US2020/0294965A1) (of record) teaches another example of a die stack structure with interconnective vias. Wan (US2014/0042298A1) (of record) teaches another example of a die-stacked image sensor.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SEAN AYERS WINTERS/Examiner, Art Unit 2892 06/16/2026
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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