DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Applicant amended claims 1-18 on 11/10/2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8 and 10-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Blednov et al. (US 2015/0303881) (hereafter Blednov).
Regarding claim 1, Blednov discloses a circuitry package 200 (Fig. 3, paragraph 0029) that is configured to be positioned on a printed circuit board (PCB) (PCB in Fig. 3, paragraph 0029) and a heat sink 150 (Fig. 3, paragraph 0032), the circuitry package comprising:
a body portion 25 (Fig. 3, paragraph 0040) having a first surface (top surface of 25 in Fig. 3);
a plurality of leads (60, 70, 90, and 95 in Fig. 3, paragraph 0043) on a logical plane (top surface of 20 in Fig. 3) and affixed on the first surface (top surface of 25 in Fig. 3) of the body portion 25 (Fig. 3), the plurality of leads (60, 70, 90, and 95 in Fig. 3) being positionable to make contact with the PCB (PCB in Fig. 3); and
a central paddle (30 and 104 in Fig. 3, paragraph 0031) affixed to the body portion 25 (Fig. 3) and extending in a direction (vertical direction in Fig. 3) substantially perpendicular to the logical plane (top surface of 20 in Fig. 3), the central paddle (30 and 104 in Fig. 3) configured to support at least one transistor die 20 (Fig. 3, paragraph 0041) near the logical plane (top surface of 20 in Fig. 3) and act as a thermal interface (see paragraph 0041, wherein “The conductive layer 97 may be a thick metal layer, e.g., a few um thick to spread the heat generated during the operation of the RF power transistor 100 to the flange 30 and to the heat sink 150 through the electrically isolating layer 25”) between the at least one transistor die 20 (Fig. 3) and the heat sink 150 (Fig. 3).
Regarding claim 2, Blednov further discloses the circuitry package of Claim 1, wherein a first end (top surface of 30 in Fig. 3) of the central paddle (30 and 104 in Fig. 3, paragraph 0031) is positioned on the logical plane (top surface of 20 in Fig. 3) and a second end (bottom surface of 30 in Fig. 3) of the central paddle (30 and 104 in Fig. 3) is positionable on the heat sink 150 (Fig. 3).
Regarding claim 3, Blednov further discloses the circuitry package of Claim 1, wherein a first end (top surface of 104 in Fig. 3) of the central paddle (30 and 104 in Fig. 3) is positioned at an offset (see Fig. 3, wherein top surface of 104 and top surface of 20 are vertically offset) from the logical plane (top surface of 20 in Fig. 3) and a second end (bottom surface of 30 in Fig. 3) of the central paddle (30 and 104 in Fig. 3) is positionable on the heat sink 150 (Fig. 3).
Regarding claim 4, Blednov further discloses the circuitry package of Claim 1, wherein the plurality of leads (60, 70, 90, and 95 in Fig. 4) are positioned to prevent overlapping between the plurality of leads (60, 70, 90, and 95 in Fig. 4) and the central paddle 104 (Fig. 4) in the direction (stacking direction in Fig. 4) perpendicular to the logical plane (plane of 20 in Fig. 4).
Regarding claim 5, Blednov further discloses the circuitry package of Claim 1, wherein the central paddle (30 and 104 in Fig. 3) comprises an extended ground conductor 6 (Fig. 3, paragraph 0034).
Regarding claim 6, Blednov further discloses the circuitry package of Claim 1, wherein the circuitry package 200 (Fig. 3) is positionable in a slot (see Fig. 3, wherein 200 is formed between PCB) of the PCB (PCB in Fig. 3).
Regarding claim 7, Blednov further discloses the circuitry package of Claim 6, wherein the plurality of leads (60, 70, 90, and 95 in Fig. 3) are positionable to make contact with signal traces 40 (Fig. 3, paragraph 0031) on a first side (top surface of left PCB in Fig. 3) of the PCB (PCB in Fig. 3), the heat sink 150 (Fig. 3) is positioned on a second side (bottom surface of left PCB in Fig. 3) of the PCB (PCB in Fig. 3), and the central paddle (30 and 104 in Fig. 3) is configured to extend through the slot (see Fig. 3, wherein 104 is between 40 and 150) between the first and second sides of the PCB (PCB in Fig. 3).
Regarding claim 8, Blednov further discloses the circuitry package of Claim 1, wherein the circuitry package 200 (Fig. 3) includes at least one extension portion 85 (Fig. 3, paragraph 0043) that extends past the logical plane (top surface of 20 in Fig. 3) and parallel (see Fig. 3, wherein 85 is vertically parallel to lateral surface of 104) to the central paddle (30 and 104 in Fig. 3).
Regarding claim 10, Blednov discloses a power amplifier, comprising:
a printed circuit board (PCB in Fig. 3, paragraph 0029);
a heat sink 150 (Fig. 3, paragraph 0032); and
a power transistor package 200 (Fig. 3, paragraph 0029) positioned on the printed circuit board (PCB) (PCB in Fig. 3) and the heat sink 150 (Fig. 3), the power transistor package 200 (Fig. 3) including:
a body portion 25 (Fig. 3, paragraph 0040) having a first surface (top surface of 25 in Fig. 3);
a plurality of leads (60, 70, 90, and 95 in Fig. 3, paragraph 0043) affixed on the first surface (top surface of 25 in Fig. 3) of the body portion 25 (Fig. 3) and on a logical plane, the plurality of leads (60, 70, 90, and 95 in Fig. 3) being positionable to make contact with the PCB (PCB in Fig. 3); and
a central paddle (30 and 104 in Fig. 3, paragraph 0031) affixed to the body portion 25 (Fig. 3) and extending in a direction (vertical direction in Fig. 3) substantially perpendicular to the logical plane (top surface of 20 in Fig. 3), the central paddle (30 and 104 in Fig. 3) configured to support at least one transistor die 20 (Fig. 3, paragraph 0041) near the logical plane (top surface of 20 in Fig. 3) and act as a thermal interface (see paragraph 0041, wherein “The conductive layer 97 may be a thick metal layer, e.g., a few um thick to spread the heat generated during the operation of the RF power transistor 100 to the flange 30 and to the heat sink 150 through the electrically isolating layer 25”) between the at least one transistor die 20 (Fig. 3) and the heat sink 150 (Fig. 3).
Regarding claim 11, Blednov further discloses the power amplifier of Claim 10, wherein a first end (top surface of 30 in Fig. 3) of the central paddle (30 and 104 in Fig. 3) is positioned along the logical plane (top surface of 20 in Fig. 3) and a second end (bottom surface of 30 in Fig. 3) of the central paddle (30 and 104 in Fig. 3) is positionable on the heat sink 150 (Fig. 3).
Regarding claim 12, Blednov further discloses the power amplifier of Claim 10, wherein a first end (top surface of 104 in Fig. 3) of the central paddle (30 and 104 in Fig. 3) is positioned at an offset (see Fig. 3, wherein top surface of 104 and top surface of 20 are vertically offset) from the logical plane (top surface of 20 in Fig. 3) and a second end (bottom surface of 30 in Fig. 3) of the central paddle (30 and 104 in Fig. 3) is positionable on the heat sink 150 (Fig. 3).
Regarding claim 13, Blednov further discloses the power amplifier of Claim 10, wherein the plurality of leads (60, 70, 90, and 95 in Fig. 4) are positioned to prevent overlapping between the plurality of leads (60, 70, 90, and 95 in Fig. 4) and the central paddle 104 (Fig. 4) in the direction (stacking direction in Fig. 4) perpendicular to the logical plane (plane of 20 in Fig. 4).
Regarding claim 14, Blednov further discloses the power amplifier of Claim 10, wherein the central paddle (30 and 104 in Fig. 3) comprises an extended ground conductor 6 (Fig. 3, paragraph 0034).
Regarding claim 15, Blednov further discloses the power amplifier of Claim 10, wherein the power transistor package 200 (Fig. 3) is positionable in a slot (see Fig. 3, wherein 200 is formed between PCB) of the PCB (PCB in Fig. 3).
Regarding claim 16, Blednov further discloses the power amplifier of Claim 15, wherein the plurality of leads (60, 70, 90, and 95 in Fig. 3) are positionable to make contact with signal traces 40 (Fig. 3, paragraph 0031) on a first side (top surface of left PCB in Fig. 3) of the PCB (PCB in Fig. 3), the heat sink 150 (Fig. 3) is positioned on a second side (bottom surface of left PCB in Fig. 3) of the PCB (PCB in Fig. 3), and the central paddle (30 and 104 in Fig. 3) is configured to extend through the slot (see Fig. 3, wherein 104 is between 40 and 150) between the first and second sides of the PCB (PCB in Fig. 3).
Regarding claim 17, Blednov further discloses the power amplifier of Claim 10, wherein the power transistor package 200 (Fig. 3) includes at least one extension portion 85 (Fig. 3, paragraph 0043) that extends past the logical plane (top surface of 20 in Fig. 3) and parallel (see Fig. 3, wherein 85 is vertically parallel to lateral surface of 104) to the central paddle (30 and 104 in Fig. 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Blednov as applied to claims 1 and 10 above, and further in view of Sohn et al. (US 2013/0069213) (hereafter Sohn).
Regarding claim 9, Blednov further discloses the circuitry package of Claim 1, wherein the plurality of leads (60, 70, 90, and 95 in Fig. 3) are configured to be soldered (see paragraph 0044, wherein “metal strip lines soldered or pressed to the respective bondpads on the die 20”) directly to the PCB (PCB in Fig. 3).
Blednov does not disclose the central paddle is configured to be soldered directly to the heat sink.
Sohn discloses the central paddle 120 (Fig. 2, paragraph 0075) is configured to be soldered (see “solder” in paragraph 0075) directly to the heat sink 200 (Fig. 2, paragraph 0075).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Blednov to form the central paddle is configured to be soldered directly to the heat sink, as taught by Sohn, since an adhesive material (Sohn, paragraph 0075) having high thermal conductivity, such as solder or conductive epoxy may attach between the heat sink 200 and the second substrate 120.
Regarding claim 18, Blednov further discloses the power amplifier of Claim 10, wherein the plurality of leads (60, 70, 90, and 95 in Fig. 3) are configured to be soldered (see paragraph 0044, wherein “metal strip lines soldered or pressed to the respective bondpads on the die 20”) directly to the PCB (PCB in Fig. 3).
Blednov does not disclose the central paddle is configured to be soldered directly to the heat sink.
Sohn discloses the central paddle 120 (Fig. 2, paragraph 0075) is configured to be soldered (see “solder” in paragraph 0075) directly to the heat sink 200 (Fig. 2, paragraph 0075).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Blednov to form the central paddle is configured to be soldered directly to the heat sink, as taught by Sohn, since an adhesive material (Sohn, paragraph 0075) having high thermal conductivity, such as solder or conductive epoxy may attach between the heat sink 200 and the second substrate 120.
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813