Prosecution Insights
Last updated: July 17, 2026
Application No. 18/560,234

METHOD FOR SELECTING PHOTOSENSITIVE RESIN COMPOSITION, METHOD FOR PRODUCING PATTERNED CURED FILM, CURED FILM, SEMICONDUCTOR DEVICE, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

Non-Final OA §102§103
Filed
Nov 10, 2023
Priority
May 14, 2021 — nonprovisional of PCTJP2021018417
Examiner
CHAMPION, RICHARD DAVID
Art Unit
Tech Center
Assignee
RESONAC Corporation
OA Round
1 (Non-Final)
44%
Grant Probability
Moderate
1-2
OA Rounds
1y 1m
Est. Remaining
53%
With Interview

Examiner Intelligence

Grants 44% of resolved cases
44%
Career Allowance Rate
55 granted / 124 resolved
-15.6% vs TC avg
Moderate +9% lift
Without
With
+8.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 10m
Avg Prosecution
40 currently pending
Career history
172
Total Applications
across all art units

Statute-Specific Performance

§103
86.0%
+46.0% vs TC avg
§102
13.2%
-26.8% vs TC avg
§112
0.3%
-39.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 124 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 1. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: 3. A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 4. Claims 1-2, 5-6, and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Iwashita et al. (Japanese Patent Publication no. JP 2008-224984 A), hereinafter Iwashita. 5. Regarding Claims 1-2, 5-6, and 8, Iwashita teaches (Paragraph [0172]) a step of applying a photosensitive resin composition on a substrate. Iwashita teaches (Paragraph [0172]) drying the photosensitive resin composition to form a resin film. Iwashita teaches (Paragraph [0172]) a step of heat-treating the resin film in a nitrogen atmosphere to obtain a cured film. Iwashita teaches (Paragraph [0172]) a step of raising temperature from 25° C. to 300° C. at a rate of 10° C./min in a nitrogen atmosphere and then measuring weight loss of the cured film. Iwashita teaches (Paragraph [0172], Table 2) a photosensitive resin composition capable of producing the cured film having a weight loss ratio at 300° C. of 1.0% to 6.0% is selected. Iwashita teaches (Paragraph [0172]) a temperature for heat-treating the resin film is 170° C. to 260° C. Iwashita teaches (Table 4) a glass transition temperature of the cured film is 200° C. or higher. Iwashita teaches (Paragraphs [0109-0124]) a step of applying a photosensitive resin composition selected by the method for selecting a photosensitive resin composition on a portion or an entire surface of a substrate. Iwashita teaches (Paragraphs [0109-0124]) drying the photosensitive resin composition to form a resin film. Iwashita teaches (Paragraphs [0109-0124]) a step of exposing at least a portion of the resin film. Iwashita teaches (Paragraphs [0109-0124]) a step of developing the resin film after exposure to form a patterned resin film. Iwashita teaches (Paragraphs [0109-0124]) a step of heating the patterned resin film to obtain a patterned cured film. Iwashita teaches (Paragraphs [0125-0132], Fig. 1-5) a method for producing a semiconductor device including a patterned cured film formed by the method for producing a patterned cured film as an interlayer insulating layer or a surface protection layer. 6. Claims 1, 3, 6, and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ikeda et al. (Japanese Patent Publication no. JP 2015-184516 A), hereinafter Ikeda. 7. Regarding Claims 1, 3, 6, and 8, Ikeda teaches (Paragraphs [0084-0094], Table 1) a step of applying a photosensitive resin composition on a substrate. Ikeda teaches (Paragraphs [0084-0094], Table 1) drying the photosensitive resin composition to form a resin film. Ikeda teaches (Paragraphs [0084-0094], Table 1) a step of heat-treating the resin film in a nitrogen atmosphere to obtain a cured film. Ikeda teaches (Paragraphs [0084-0094], Table 1) a step of raising temperature from 25° C. to 300° C. at a rate of 10° C./min in a nitrogen atmosphere and then measuring weight loss of the cured film. Ikeda teaches (Paragraphs [0084-0094], Table 1) a photosensitive resin composition capable of producing the cured film having a weight loss ratio at 300° C. of 1.0% to 6.0% is selected. Ikeda teaches (Paragraphs [0084-0094], Table 1) a storage modulus at 130° C. of the cured film is 1.0 GPa or more. Ikeda teaches (Paragraphs [0070 and 0092]) a step of applying a photosensitive resin composition selected by the method for selecting a photosensitive resin composition on a portion or an entire surface of a substrate. Ikeda teaches (Paragraphs [0070 and 0092]) drying the photosensitive resin composition to form a resin film. Ikeda teaches (Paragraphs [0070 and 0092]) a step of exposing at least a portion of the resin film. Ikeda teaches (Paragraphs [0070 and 0092]) a step of developing the resin film after exposure to form a patterned resin film. Ikeda teaches (Paragraphs [0070 and 0092]) a step of heating the patterned resin film to obtain a patterned cured film. Ikeda teaches (Paragraphs [0068-0071, Fig. 1]) a method for producing a semiconductor device including a patterned cured film formed by the method for producing a patterned cured film as an interlayer insulating layer or a surface protection layer. 8. Claims 1, 2, 4, 6, and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kato et al. (Japanese Patent Publication no. JP 2010-020108 A), hereinafter Kato. 9. Regarding Claims 1, 2, 4, 6, and 8, Kato teaches (Paragraphs [0141 and 0150]) a step of applying a photosensitive resin composition on a substrate. Kato teaches (Paragraph [0150]) drying the photosensitive resin composition to form a resin film. Kato teaches (Paragraph [0150]) a step of heat-treating the resin film in a nitrogen atmosphere to obtain a cured film. Kato teaches (Paragraph [0150], Table 2) a step of raising temperature from 25° C. to 300° C. at a rate of 10° C./min in a nitrogen atmosphere and then measuring weight loss of the cured film. Kato teaches (Paragraph [0150], Table 2) a photosensitive resin composition capable of producing the cured film having a weight loss ratio at 300° C. of 1.0% to 6.0% is selected. Kato teaches (Paragraph [0150], Table 2) a temperature for heat-treating the resin film is 170° C. to 260° C. Kato teaches (Paragraph [0150], Table 2) a moisture absorption rate obtained after leaving the cured film to stand for 24 hours under conditions of 130° C. and 85 RH % is 1.2% or less. Kato teaches (Paragraph [0145]) a step of applying a photosensitive resin composition selected by the method for selecting a photosensitive resin composition on a portion or an entire surface of a substrate. Kato teaches (Paragraph [0145]) drying the photosensitive resin composition to form a resin film. Kato teaches (Paragraph [0145]) a step of exposing at least a portion of the resin film. Kato teaches (Paragraph [0145]) a step of developing the resin film after exposure to form a patterned resin film. Kato teaches (Paragraph [0145]) a step of heating the patterned resin film to obtain a patterned cured film. Kato teaches (Paragraph [0145]) a method for producing a semiconductor device including a patterned cured film formed by the method for producing a patterned cured film as an interlayer insulating layer or a surface protection layer. Claim Rejections - 35 USC § 103 10. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: 11. A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 12. Claims 7, 9 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Iwashita et al. (Japanese Patent Publication no. JP 2008-224984 A), hereinafter Iwashita; in view of Minami et al. (United States Patent Publication No. US 2005/0164129 A1), hereinafter Minami. 13. Regarding Claim 7, Iwashita teaches all limitations of Claim 6 above. However, Iwashita fails to explicitly teach wherein the substrate has a wiring pattern having a line width of 3 µm or less and an interline distance of 3 µm or less. 14. Minami teaches (Paragraphs [0040, 0044, 0047, and 0050]) the substrate has a wiring pattern having a line width of 2 µm or less and an interline distance of 2 µm or less. Minami teaches (Paragraph [0134 and 0252]) that said line width and space width is required for fine patterns which is essential for scaling down of a resultant device. 15. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Iwashita to incorporate the teachings of Minami wherein the substrate has a wiring pattern having a line width of 2 µm or less and an interline distance of 2 µm or less. Doing so would have resulted in fine patterns essential for scaling down of devices, as recognized by Minami. 16. Regarding Claims 9 and 12-13, Iwashita teaches (Paragraph [0172], Table 2) wherein a weight loss ratio measured by raising temperature of the cured film from 25° C to 300° C at a rate of 10° C/min in a nitrogen atmosphere is 1.0% to 6.0%. Iwashita teaches (Table 4) a glass transition temperature of the cured film is 200° C. or higher. Iwashita teaches (Paragraphs [0125-0132], Fig. 1-5) a semiconductor device comprising the cured film as an interlayer insulating layer or a surface protection layer. However, Iwashita fails to explicitly teach wherein the substrate has a wiring pattern having a line width of 3 µm or less and an interline distance of 3 µm or less. 17. Minami teaches (Paragraphs [0040, 0044, 0047, and 0050]) the substrate has a wiring pattern having a line width of 2 µm or less and an interline distance of 2 µm or less. Minami teaches (Paragraph [0134 and 0252]) that said line width and space width is required for fine patterns which is essential for scaling down of a resultant device. 18. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Iwashita to incorporate the teachings of Minami wherein the substrate has a wiring pattern having a line width of 2 µm or less and an interline distance of 2 µm or less. Doing so would have resulted in fine patterns essential for scaling down of devices, as recognized by Minami. 19. Claims 7, 9-10, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda et al. (Japanese Patent Publication no. JP 2015-184516 A), hereinafter Ikeda; in view of Minami et al. (United States Patent Publication No. US 2005/0164129 A1), hereinafter Minami. 20. Regarding Claim 7, Ikeda teaches all limitations of Claim 6 above. However, Ikeda fails to explicitly teach wherein the substrate has a wiring pattern having a line width of 3 µm or less and an interline distance of 3 µm or less. 21. Minami teaches (Paragraphs [0040, 0044, 0047, and 0050]) the substrate has a wiring pattern having a line width of 2 µm or less and an interline distance of 2 µm or less. Minami teaches (Paragraph [0134 and 0252]) that said line width and space width is required for fine patterns which is essential for scaling down of a resultant device. 22. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ikeda to incorporate the teachings of Minami wherein the substrate has a wiring pattern having a line width of 2 µm or less and an interline distance of 2 µm or less. Doing so would have resulted in fine patterns essential for scaling down of devices, as recognized by Minami. 23. Regarding Claims 9-10, and 13, Ikeda teaches (Paragraph [0084-0094], Table 1) wherein a weight loss ratio measured by raising temperature of the cured film from 25° C to 300° C at a rate of 10° C/min in a nitrogen atmosphere is 1.0% to 6.0%. Ikeda teaches (Paragraphs [0084-0094], Table 1) a storage modulus at 130° C. of the cured film is 1.0 GPa or more. Ikeda teaches (Paragraphs [0125-0132], Fig. 1-5) a semiconductor device comprising the cured film as an interlayer insulating layer or a surface protection layer. However, Ikeda fails to explicitly teach wherein the substrate has a wiring pattern having a line width of 3 µm or less and an interline distance of 3 µm or less. 24. Minami teaches (Paragraphs [0040, 0044, 0047, and 0050]) the substrate has a wiring pattern having a line width of 2 µm or less and an interline distance of 2 µm or less. Minami teaches (Paragraph [0134 and 0252]) that said line width and space width is required for fine patterns which is essential for scaling down of a resultant device. 25. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ikeda to incorporate the teachings of Minami wherein the substrate has a wiring pattern having a line width of 2 µm or less and an interline distance of 2 µm or less. Doing so would have resulted in fine patterns essential for scaling down of devices, as recognized by Minami. 26. Claims 7, 9, 11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kato et al. (Japanese Patent Publication no. JP 2010-020108 A), hereinafter Kato; in view of Minami et al. (United States Patent Publication No. US 2005/0164129 A1), hereinafter Minami. 27. Regarding Claim 7, Kato teaches all limitations of Claim 6 above. However, Ikeda fails to explicitly teach wherein the substrate has a wiring pattern having a line width of 3 µm or less and an interline distance of 3 µm or less. 28. Minami teaches (Paragraphs [0040, 0044, 0047, and 0050]) the substrate has a wiring pattern having a line width of 2 µm or less and an interline distance of 2 µm or less. Minami teaches (Paragraph [0134 and 0252]) that said line width and space width is required for fine patterns which is essential for scaling down of a resultant device. 29. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kato to incorporate the teachings of Minami wherein the substrate has a wiring pattern having a line width of 2 µm or less and an interline distance of 2 µm or less. Doing so would have resulted in fine patterns essential for scaling down of devices, as recognized by Minami. 30. Regarding Claims 9, 11, and 13, Kato teaches (Paragraph [0150], Table 2) wherein a weight loss ratio measured by raising temperature of the cured film from 25° C to 300° C at a rate of 10° C/min in a nitrogen atmosphere is 1.0% to 6.0%. Kato teaches (Paragraph [0150], Table 2) a moisture absorption rate obtained after leaving the cured film to stand for 24 hours under conditions of 130° C. and 85 RH % is 1.2% or less. Kato teaches (Paragraph [0150]) a semiconductor device comprising the cured film as an interlayer insulating layer or a surface protection layer. However, Kato fails to explicitly teach wherein the substrate has a wiring pattern having a line width of 3 µm or less and an interline distance of 3 µm or less. 31. Minami teaches (Paragraphs [0040, 0044, 0047, and 0050]) the substrate has a wiring pattern having a line width of 2 µm or less and an interline distance of 2 µm or less. Minami teaches (Paragraph [0134 and 0252]) that said line width and space width is required for fine patterns which is essential for scaling down of a resultant device. 32. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kato to incorporate the teachings of Minami wherein the substrate has a wiring pattern having a line width of 2 µm or less and an interline distance of 2 µm or less. Doing so would have resulted in fine patterns essential for scaling down of devices, as recognized by Minami. Conclusion 33. Any inquiry concerning this communication should be directed to RICHARD D CHAMPION at telephone number (571) 272-0750. The examiner can normally be reached on 8 a.m. - 5 p.m. Mon-Fri EST. 34. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, KEITH D HENDRICKS can be reached at (571) 272-1401. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 35. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://portal.uspto.gov/external/portal. Should you have questions about access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). 36. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. /Keith D. Hendricks/Supervisory Patent Examiner, Art Unit 1733 /R.D.C./Examiner, Art Unit 1737
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Prosecution Timeline

Nov 10, 2023
Application Filed
Jun 16, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
44%
Grant Probability
53%
With Interview (+8.8%)
3y 10m (~1y 1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 124 resolved cases by this examiner. Grant probability derived from career allowance rate.

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